1 /* 2 * Intel I/OAT DMA Linux driver 3 * Copyright(c) 2004 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 */ 18 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/slab.h> 22 #include <linux/pci.h> 23 #include <linux/interrupt.h> 24 #include <linux/dmaengine.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/workqueue.h> 28 #include <linux/prefetch.h> 29 #include <linux/dca.h> 30 #include "dma.h" 31 #include "registers.h" 32 #include "hw.h" 33 34 #include "../dmaengine.h" 35 36 MODULE_VERSION(IOAT_DMA_VERSION); 37 MODULE_LICENSE("Dual BSD/GPL"); 38 MODULE_AUTHOR("Intel Corporation"); 39 40 static struct pci_device_id ioat_pci_tbl[] = { 41 /* I/OAT v3 platforms */ 42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, 43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, 44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, 46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, 47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, 48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, 49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, 50 51 /* I/OAT v3.2 platforms */ 52 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, 53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, 54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, 55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, 56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, 57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, 58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, 59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, 60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, 61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, 62 63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, 64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, 65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, 66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, 67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, 68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, 69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, 70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, 71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, 72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, 73 74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, 75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, 76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, 77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, 78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, 79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, 80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, 81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, 82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, 83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, 84 85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, 86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, 87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, 88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, 89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, 90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, 91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, 92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, 93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, 94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, 95 96 /* I/OAT v3.3 platforms */ 97 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, 99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, 100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, 101 102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, 103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, 104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, 105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, 106 107 { 0, } 108 }; 109 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); 110 111 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 112 static void ioat_remove(struct pci_dev *pdev); 113 static void 114 ioat_init_channel(struct ioatdma_device *ioat_dma, 115 struct ioatdma_chan *ioat_chan, int idx); 116 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma); 117 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma); 118 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); 119 120 static int ioat_dca_enabled = 1; 121 module_param(ioat_dca_enabled, int, 0644); 122 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); 123 int ioat_pending_level = 4; 124 module_param(ioat_pending_level, int, 0644); 125 MODULE_PARM_DESC(ioat_pending_level, 126 "high-water mark for pushing ioat descriptors (default: 4)"); 127 int ioat_ring_alloc_order = 8; 128 module_param(ioat_ring_alloc_order, int, 0644); 129 MODULE_PARM_DESC(ioat_ring_alloc_order, 130 "ioat+: allocate 2^n descriptors per channel (default: 8 max: 16)"); 131 int ioat_ring_max_alloc_order = IOAT_MAX_ORDER; 132 module_param(ioat_ring_max_alloc_order, int, 0644); 133 MODULE_PARM_DESC(ioat_ring_max_alloc_order, 134 "ioat+: upper limit for ring size (default: 16)"); 135 static char ioat_interrupt_style[32] = "msix"; 136 module_param_string(ioat_interrupt_style, ioat_interrupt_style, 137 sizeof(ioat_interrupt_style), 0644); 138 MODULE_PARM_DESC(ioat_interrupt_style, 139 "set ioat interrupt style: msix (default), msi, intx"); 140 141 struct kmem_cache *ioat_cache; 142 struct kmem_cache *ioat_sed_cache; 143 144 static bool is_jf_ioat(struct pci_dev *pdev) 145 { 146 switch (pdev->device) { 147 case PCI_DEVICE_ID_INTEL_IOAT_JSF0: 148 case PCI_DEVICE_ID_INTEL_IOAT_JSF1: 149 case PCI_DEVICE_ID_INTEL_IOAT_JSF2: 150 case PCI_DEVICE_ID_INTEL_IOAT_JSF3: 151 case PCI_DEVICE_ID_INTEL_IOAT_JSF4: 152 case PCI_DEVICE_ID_INTEL_IOAT_JSF5: 153 case PCI_DEVICE_ID_INTEL_IOAT_JSF6: 154 case PCI_DEVICE_ID_INTEL_IOAT_JSF7: 155 case PCI_DEVICE_ID_INTEL_IOAT_JSF8: 156 case PCI_DEVICE_ID_INTEL_IOAT_JSF9: 157 return true; 158 default: 159 return false; 160 } 161 } 162 163 static bool is_snb_ioat(struct pci_dev *pdev) 164 { 165 switch (pdev->device) { 166 case PCI_DEVICE_ID_INTEL_IOAT_SNB0: 167 case PCI_DEVICE_ID_INTEL_IOAT_SNB1: 168 case PCI_DEVICE_ID_INTEL_IOAT_SNB2: 169 case PCI_DEVICE_ID_INTEL_IOAT_SNB3: 170 case PCI_DEVICE_ID_INTEL_IOAT_SNB4: 171 case PCI_DEVICE_ID_INTEL_IOAT_SNB5: 172 case PCI_DEVICE_ID_INTEL_IOAT_SNB6: 173 case PCI_DEVICE_ID_INTEL_IOAT_SNB7: 174 case PCI_DEVICE_ID_INTEL_IOAT_SNB8: 175 case PCI_DEVICE_ID_INTEL_IOAT_SNB9: 176 return true; 177 default: 178 return false; 179 } 180 } 181 182 static bool is_ivb_ioat(struct pci_dev *pdev) 183 { 184 switch (pdev->device) { 185 case PCI_DEVICE_ID_INTEL_IOAT_IVB0: 186 case PCI_DEVICE_ID_INTEL_IOAT_IVB1: 187 case PCI_DEVICE_ID_INTEL_IOAT_IVB2: 188 case PCI_DEVICE_ID_INTEL_IOAT_IVB3: 189 case PCI_DEVICE_ID_INTEL_IOAT_IVB4: 190 case PCI_DEVICE_ID_INTEL_IOAT_IVB5: 191 case PCI_DEVICE_ID_INTEL_IOAT_IVB6: 192 case PCI_DEVICE_ID_INTEL_IOAT_IVB7: 193 case PCI_DEVICE_ID_INTEL_IOAT_IVB8: 194 case PCI_DEVICE_ID_INTEL_IOAT_IVB9: 195 return true; 196 default: 197 return false; 198 } 199 200 } 201 202 static bool is_hsw_ioat(struct pci_dev *pdev) 203 { 204 switch (pdev->device) { 205 case PCI_DEVICE_ID_INTEL_IOAT_HSW0: 206 case PCI_DEVICE_ID_INTEL_IOAT_HSW1: 207 case PCI_DEVICE_ID_INTEL_IOAT_HSW2: 208 case PCI_DEVICE_ID_INTEL_IOAT_HSW3: 209 case PCI_DEVICE_ID_INTEL_IOAT_HSW4: 210 case PCI_DEVICE_ID_INTEL_IOAT_HSW5: 211 case PCI_DEVICE_ID_INTEL_IOAT_HSW6: 212 case PCI_DEVICE_ID_INTEL_IOAT_HSW7: 213 case PCI_DEVICE_ID_INTEL_IOAT_HSW8: 214 case PCI_DEVICE_ID_INTEL_IOAT_HSW9: 215 return true; 216 default: 217 return false; 218 } 219 220 } 221 222 static bool is_xeon_cb32(struct pci_dev *pdev) 223 { 224 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 225 is_hsw_ioat(pdev); 226 } 227 228 bool is_bwd_ioat(struct pci_dev *pdev) 229 { 230 switch (pdev->device) { 231 case PCI_DEVICE_ID_INTEL_IOAT_BWD0: 232 case PCI_DEVICE_ID_INTEL_IOAT_BWD1: 233 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 234 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 235 /* even though not Atom, BDX-DE has same DMA silicon */ 236 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 237 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 238 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 239 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 240 return true; 241 default: 242 return false; 243 } 244 } 245 246 static bool is_bwd_noraid(struct pci_dev *pdev) 247 { 248 switch (pdev->device) { 249 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 250 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 251 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 252 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 253 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 254 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 255 return true; 256 default: 257 return false; 258 } 259 260 } 261 262 /* 263 * Perform a IOAT transaction to verify the HW works. 264 */ 265 #define IOAT_TEST_SIZE 2000 266 267 static void ioat_dma_test_callback(void *dma_async_param) 268 { 269 struct completion *cmp = dma_async_param; 270 271 complete(cmp); 272 } 273 274 /** 275 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. 276 * @ioat_dma: dma device to be tested 277 */ 278 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) 279 { 280 int i; 281 u8 *src; 282 u8 *dest; 283 struct dma_device *dma = &ioat_dma->dma_dev; 284 struct device *dev = &ioat_dma->pdev->dev; 285 struct dma_chan *dma_chan; 286 struct dma_async_tx_descriptor *tx; 287 dma_addr_t dma_dest, dma_src; 288 dma_cookie_t cookie; 289 int err = 0; 290 struct completion cmp; 291 unsigned long tmo; 292 unsigned long flags; 293 294 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); 295 if (!src) 296 return -ENOMEM; 297 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); 298 if (!dest) { 299 kfree(src); 300 return -ENOMEM; 301 } 302 303 /* Fill in src buffer */ 304 for (i = 0; i < IOAT_TEST_SIZE; i++) 305 src[i] = (u8)i; 306 307 /* Start copy, using first DMA channel */ 308 dma_chan = container_of(dma->channels.next, struct dma_chan, 309 device_node); 310 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 311 dev_err(dev, "selftest cannot allocate chan resource\n"); 312 err = -ENODEV; 313 goto out; 314 } 315 316 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 317 if (dma_mapping_error(dev, dma_src)) { 318 dev_err(dev, "mapping src buffer failed\n"); 319 goto free_resources; 320 } 321 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 322 if (dma_mapping_error(dev, dma_dest)) { 323 dev_err(dev, "mapping dest buffer failed\n"); 324 goto unmap_src; 325 } 326 flags = DMA_PREP_INTERRUPT; 327 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, 328 dma_src, IOAT_TEST_SIZE, 329 flags); 330 if (!tx) { 331 dev_err(dev, "Self-test prep failed, disabling\n"); 332 err = -ENODEV; 333 goto unmap_dma; 334 } 335 336 async_tx_ack(tx); 337 init_completion(&cmp); 338 tx->callback = ioat_dma_test_callback; 339 tx->callback_param = &cmp; 340 cookie = tx->tx_submit(tx); 341 if (cookie < 0) { 342 dev_err(dev, "Self-test setup failed, disabling\n"); 343 err = -ENODEV; 344 goto unmap_dma; 345 } 346 dma->device_issue_pending(dma_chan); 347 348 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 349 350 if (tmo == 0 || 351 dma->device_tx_status(dma_chan, cookie, NULL) 352 != DMA_COMPLETE) { 353 dev_err(dev, "Self-test copy timed out, disabling\n"); 354 err = -ENODEV; 355 goto unmap_dma; 356 } 357 if (memcmp(src, dest, IOAT_TEST_SIZE)) { 358 dev_err(dev, "Self-test copy failed compare, disabling\n"); 359 err = -ENODEV; 360 goto free_resources; 361 } 362 363 unmap_dma: 364 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 365 unmap_src: 366 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 367 free_resources: 368 dma->device_free_chan_resources(dma_chan); 369 out: 370 kfree(src); 371 kfree(dest); 372 return err; 373 } 374 375 /** 376 * ioat_dma_setup_interrupts - setup interrupt handler 377 * @ioat_dma: ioat dma device 378 */ 379 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) 380 { 381 struct ioatdma_chan *ioat_chan; 382 struct pci_dev *pdev = ioat_dma->pdev; 383 struct device *dev = &pdev->dev; 384 struct msix_entry *msix; 385 int i, j, msixcnt; 386 int err = -EINVAL; 387 u8 intrctrl = 0; 388 389 if (!strcmp(ioat_interrupt_style, "msix")) 390 goto msix; 391 if (!strcmp(ioat_interrupt_style, "msi")) 392 goto msi; 393 if (!strcmp(ioat_interrupt_style, "intx")) 394 goto intx; 395 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); 396 goto err_no_irq; 397 398 msix: 399 /* The number of MSI-X vectors should equal the number of channels */ 400 msixcnt = ioat_dma->dma_dev.chancnt; 401 for (i = 0; i < msixcnt; i++) 402 ioat_dma->msix_entries[i].entry = i; 403 404 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); 405 if (err) 406 goto msi; 407 408 for (i = 0; i < msixcnt; i++) { 409 msix = &ioat_dma->msix_entries[i]; 410 ioat_chan = ioat_chan_by_index(ioat_dma, i); 411 err = devm_request_irq(dev, msix->vector, 412 ioat_dma_do_interrupt_msix, 0, 413 "ioat-msix", ioat_chan); 414 if (err) { 415 for (j = 0; j < i; j++) { 416 msix = &ioat_dma->msix_entries[j]; 417 ioat_chan = ioat_chan_by_index(ioat_dma, j); 418 devm_free_irq(dev, msix->vector, ioat_chan); 419 } 420 goto msi; 421 } 422 } 423 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; 424 ioat_dma->irq_mode = IOAT_MSIX; 425 goto done; 426 427 msi: 428 err = pci_enable_msi(pdev); 429 if (err) 430 goto intx; 431 432 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, 433 "ioat-msi", ioat_dma); 434 if (err) { 435 pci_disable_msi(pdev); 436 goto intx; 437 } 438 ioat_dma->irq_mode = IOAT_MSI; 439 goto done; 440 441 intx: 442 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 443 IRQF_SHARED, "ioat-intx", ioat_dma); 444 if (err) 445 goto err_no_irq; 446 447 ioat_dma->irq_mode = IOAT_INTX; 448 done: 449 if (is_bwd_ioat(pdev)) 450 ioat_intr_quirk(ioat_dma); 451 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; 452 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 453 return 0; 454 455 err_no_irq: 456 /* Disable all interrupt generation */ 457 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 458 ioat_dma->irq_mode = IOAT_NOIRQ; 459 dev_err(dev, "no usable interrupts\n"); 460 return err; 461 } 462 463 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) 464 { 465 /* Disable all interrupt generation */ 466 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 467 } 468 469 static int ioat_probe(struct ioatdma_device *ioat_dma) 470 { 471 int err = -ENODEV; 472 struct dma_device *dma = &ioat_dma->dma_dev; 473 struct pci_dev *pdev = ioat_dma->pdev; 474 struct device *dev = &pdev->dev; 475 476 /* DMA coherent memory pool for DMA descriptor allocations */ 477 ioat_dma->dma_pool = pci_pool_create("dma_desc_pool", pdev, 478 sizeof(struct ioat_dma_descriptor), 479 64, 0); 480 if (!ioat_dma->dma_pool) { 481 err = -ENOMEM; 482 goto err_dma_pool; 483 } 484 485 ioat_dma->completion_pool = pci_pool_create("completion_pool", pdev, 486 sizeof(u64), 487 SMP_CACHE_BYTES, 488 SMP_CACHE_BYTES); 489 490 if (!ioat_dma->completion_pool) { 491 err = -ENOMEM; 492 goto err_completion_pool; 493 } 494 495 ioat_enumerate_channels(ioat_dma); 496 497 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 498 dma->dev = &pdev->dev; 499 500 if (!dma->chancnt) { 501 dev_err(dev, "channel enumeration error\n"); 502 goto err_setup_interrupts; 503 } 504 505 err = ioat_dma_setup_interrupts(ioat_dma); 506 if (err) 507 goto err_setup_interrupts; 508 509 err = ioat3_dma_self_test(ioat_dma); 510 if (err) 511 goto err_self_test; 512 513 return 0; 514 515 err_self_test: 516 ioat_disable_interrupts(ioat_dma); 517 err_setup_interrupts: 518 pci_pool_destroy(ioat_dma->completion_pool); 519 err_completion_pool: 520 pci_pool_destroy(ioat_dma->dma_pool); 521 err_dma_pool: 522 return err; 523 } 524 525 static int ioat_register(struct ioatdma_device *ioat_dma) 526 { 527 int err = dma_async_device_register(&ioat_dma->dma_dev); 528 529 if (err) { 530 ioat_disable_interrupts(ioat_dma); 531 pci_pool_destroy(ioat_dma->completion_pool); 532 pci_pool_destroy(ioat_dma->dma_pool); 533 } 534 535 return err; 536 } 537 538 static void ioat_dma_remove(struct ioatdma_device *ioat_dma) 539 { 540 struct dma_device *dma = &ioat_dma->dma_dev; 541 542 ioat_disable_interrupts(ioat_dma); 543 544 ioat_kobject_del(ioat_dma); 545 546 dma_async_device_unregister(dma); 547 548 pci_pool_destroy(ioat_dma->dma_pool); 549 pci_pool_destroy(ioat_dma->completion_pool); 550 551 INIT_LIST_HEAD(&dma->channels); 552 } 553 554 /** 555 * ioat_enumerate_channels - find and initialize the device's channels 556 * @ioat_dma: the ioat dma device to be enumerated 557 */ 558 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma) 559 { 560 struct ioatdma_chan *ioat_chan; 561 struct device *dev = &ioat_dma->pdev->dev; 562 struct dma_device *dma = &ioat_dma->dma_dev; 563 u8 xfercap_log; 564 int i; 565 566 INIT_LIST_HEAD(&dma->channels); 567 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); 568 dma->chancnt &= 0x1f; /* bits [4:0] valid */ 569 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) { 570 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", 571 dma->chancnt, ARRAY_SIZE(ioat_dma->idx)); 572 dma->chancnt = ARRAY_SIZE(ioat_dma->idx); 573 } 574 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); 575 xfercap_log &= 0x1f; /* bits [4:0] valid */ 576 if (xfercap_log == 0) 577 return 0; 578 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); 579 580 for (i = 0; i < dma->chancnt; i++) { 581 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); 582 if (!ioat_chan) 583 break; 584 585 ioat_init_channel(ioat_dma, ioat_chan, i); 586 ioat_chan->xfercap_log = xfercap_log; 587 spin_lock_init(&ioat_chan->prep_lock); 588 if (ioat_reset_hw(ioat_chan)) { 589 i = 0; 590 break; 591 } 592 } 593 dma->chancnt = i; 594 return i; 595 } 596 597 /** 598 * ioat_free_chan_resources - release all the descriptors 599 * @chan: the channel to be cleaned 600 */ 601 static void ioat_free_chan_resources(struct dma_chan *c) 602 { 603 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 604 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; 605 struct ioat_ring_ent *desc; 606 const int total_descs = 1 << ioat_chan->alloc_order; 607 int descs; 608 int i; 609 610 /* Before freeing channel resources first check 611 * if they have been previously allocated for this channel. 612 */ 613 if (!ioat_chan->ring) 614 return; 615 616 ioat_stop(ioat_chan); 617 ioat_reset_hw(ioat_chan); 618 619 spin_lock_bh(&ioat_chan->cleanup_lock); 620 spin_lock_bh(&ioat_chan->prep_lock); 621 descs = ioat_ring_space(ioat_chan); 622 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); 623 for (i = 0; i < descs; i++) { 624 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); 625 ioat_free_ring_ent(desc, c); 626 } 627 628 if (descs < total_descs) 629 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", 630 total_descs - descs); 631 632 for (i = 0; i < total_descs - descs; i++) { 633 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); 634 dump_desc_dbg(ioat_chan, desc); 635 ioat_free_ring_ent(desc, c); 636 } 637 638 kfree(ioat_chan->ring); 639 ioat_chan->ring = NULL; 640 ioat_chan->alloc_order = 0; 641 pci_pool_free(ioat_dma->completion_pool, ioat_chan->completion, 642 ioat_chan->completion_dma); 643 spin_unlock_bh(&ioat_chan->prep_lock); 644 spin_unlock_bh(&ioat_chan->cleanup_lock); 645 646 ioat_chan->last_completion = 0; 647 ioat_chan->completion_dma = 0; 648 ioat_chan->dmacount = 0; 649 } 650 651 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring 652 * @chan: channel to be initialized 653 */ 654 static int ioat_alloc_chan_resources(struct dma_chan *c) 655 { 656 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 657 struct ioat_ring_ent **ring; 658 u64 status; 659 int order; 660 int i = 0; 661 u32 chanerr; 662 663 /* have we already been set up? */ 664 if (ioat_chan->ring) 665 return 1 << ioat_chan->alloc_order; 666 667 /* Setup register to interrupt and write completion status on error */ 668 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); 669 670 /* allocate a completion writeback area */ 671 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 672 ioat_chan->completion = 673 pci_pool_alloc(ioat_chan->ioat_dma->completion_pool, 674 GFP_KERNEL, &ioat_chan->completion_dma); 675 if (!ioat_chan->completion) 676 return -ENOMEM; 677 678 memset(ioat_chan->completion, 0, sizeof(*ioat_chan->completion)); 679 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, 680 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); 681 writel(((u64)ioat_chan->completion_dma) >> 32, 682 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 683 684 order = ioat_get_alloc_order(); 685 ring = ioat_alloc_ring(c, order, GFP_KERNEL); 686 if (!ring) 687 return -ENOMEM; 688 689 spin_lock_bh(&ioat_chan->cleanup_lock); 690 spin_lock_bh(&ioat_chan->prep_lock); 691 ioat_chan->ring = ring; 692 ioat_chan->head = 0; 693 ioat_chan->issued = 0; 694 ioat_chan->tail = 0; 695 ioat_chan->alloc_order = order; 696 set_bit(IOAT_RUN, &ioat_chan->state); 697 spin_unlock_bh(&ioat_chan->prep_lock); 698 spin_unlock_bh(&ioat_chan->cleanup_lock); 699 700 ioat_start_null_desc(ioat_chan); 701 702 /* check that we got off the ground */ 703 do { 704 udelay(1); 705 status = ioat_chansts(ioat_chan); 706 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); 707 708 if (is_ioat_active(status) || is_ioat_idle(status)) 709 return 1 << ioat_chan->alloc_order; 710 711 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 712 713 dev_WARN(to_dev(ioat_chan), 714 "failed to start channel chanerr: %#x\n", chanerr); 715 ioat_free_chan_resources(c); 716 return -EFAULT; 717 } 718 719 /* common channel initialization */ 720 static void 721 ioat_init_channel(struct ioatdma_device *ioat_dma, 722 struct ioatdma_chan *ioat_chan, int idx) 723 { 724 struct dma_device *dma = &ioat_dma->dma_dev; 725 struct dma_chan *c = &ioat_chan->dma_chan; 726 unsigned long data = (unsigned long) c; 727 728 ioat_chan->ioat_dma = ioat_dma; 729 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); 730 spin_lock_init(&ioat_chan->cleanup_lock); 731 ioat_chan->dma_chan.device = dma; 732 dma_cookie_init(&ioat_chan->dma_chan); 733 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); 734 ioat_dma->idx[idx] = ioat_chan; 735 init_timer(&ioat_chan->timer); 736 ioat_chan->timer.function = ioat_timer_event; 737 ioat_chan->timer.data = data; 738 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data); 739 } 740 741 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ 742 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) 743 { 744 int i, src_idx; 745 struct page *dest; 746 struct page *xor_srcs[IOAT_NUM_SRC_TEST]; 747 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; 748 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; 749 dma_addr_t dest_dma; 750 struct dma_async_tx_descriptor *tx; 751 struct dma_chan *dma_chan; 752 dma_cookie_t cookie; 753 u8 cmp_byte = 0; 754 u32 cmp_word; 755 u32 xor_val_result; 756 int err = 0; 757 struct completion cmp; 758 unsigned long tmo; 759 struct device *dev = &ioat_dma->pdev->dev; 760 struct dma_device *dma = &ioat_dma->dma_dev; 761 u8 op = 0; 762 763 dev_dbg(dev, "%s\n", __func__); 764 765 if (!dma_has_cap(DMA_XOR, dma->cap_mask)) 766 return 0; 767 768 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 769 xor_srcs[src_idx] = alloc_page(GFP_KERNEL); 770 if (!xor_srcs[src_idx]) { 771 while (src_idx--) 772 __free_page(xor_srcs[src_idx]); 773 return -ENOMEM; 774 } 775 } 776 777 dest = alloc_page(GFP_KERNEL); 778 if (!dest) { 779 while (src_idx--) 780 __free_page(xor_srcs[src_idx]); 781 return -ENOMEM; 782 } 783 784 /* Fill in src buffers */ 785 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 786 u8 *ptr = page_address(xor_srcs[src_idx]); 787 788 for (i = 0; i < PAGE_SIZE; i++) 789 ptr[i] = (1 << src_idx); 790 } 791 792 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) 793 cmp_byte ^= (u8) (1 << src_idx); 794 795 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | 796 (cmp_byte << 8) | cmp_byte; 797 798 memset(page_address(dest), 0, PAGE_SIZE); 799 800 dma_chan = container_of(dma->channels.next, struct dma_chan, 801 device_node); 802 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 803 err = -ENODEV; 804 goto out; 805 } 806 807 /* test xor */ 808 op = IOAT_OP_XOR; 809 810 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); 811 if (dma_mapping_error(dev, dest_dma)) 812 goto dma_unmap; 813 814 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 815 dma_srcs[i] = DMA_ERROR_CODE; 816 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { 817 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, 818 DMA_TO_DEVICE); 819 if (dma_mapping_error(dev, dma_srcs[i])) 820 goto dma_unmap; 821 } 822 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, 823 IOAT_NUM_SRC_TEST, PAGE_SIZE, 824 DMA_PREP_INTERRUPT); 825 826 if (!tx) { 827 dev_err(dev, "Self-test xor prep failed\n"); 828 err = -ENODEV; 829 goto dma_unmap; 830 } 831 832 async_tx_ack(tx); 833 init_completion(&cmp); 834 tx->callback = ioat_dma_test_callback; 835 tx->callback_param = &cmp; 836 cookie = tx->tx_submit(tx); 837 if (cookie < 0) { 838 dev_err(dev, "Self-test xor setup failed\n"); 839 err = -ENODEV; 840 goto dma_unmap; 841 } 842 dma->device_issue_pending(dma_chan); 843 844 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 845 846 if (tmo == 0 || 847 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 848 dev_err(dev, "Self-test xor timed out\n"); 849 err = -ENODEV; 850 goto dma_unmap; 851 } 852 853 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 854 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 855 856 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 857 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { 858 u32 *ptr = page_address(dest); 859 860 if (ptr[i] != cmp_word) { 861 dev_err(dev, "Self-test xor failed compare\n"); 862 err = -ENODEV; 863 goto free_resources; 864 } 865 } 866 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 867 868 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 869 870 /* skip validate if the capability is not present */ 871 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) 872 goto free_resources; 873 874 op = IOAT_OP_XOR_VAL; 875 876 /* validate the sources with the destintation page */ 877 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 878 xor_val_srcs[i] = xor_srcs[i]; 879 xor_val_srcs[i] = dest; 880 881 xor_val_result = 1; 882 883 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 884 dma_srcs[i] = DMA_ERROR_CODE; 885 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 886 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 887 DMA_TO_DEVICE); 888 if (dma_mapping_error(dev, dma_srcs[i])) 889 goto dma_unmap; 890 } 891 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 892 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 893 &xor_val_result, DMA_PREP_INTERRUPT); 894 if (!tx) { 895 dev_err(dev, "Self-test zero prep failed\n"); 896 err = -ENODEV; 897 goto dma_unmap; 898 } 899 900 async_tx_ack(tx); 901 init_completion(&cmp); 902 tx->callback = ioat_dma_test_callback; 903 tx->callback_param = &cmp; 904 cookie = tx->tx_submit(tx); 905 if (cookie < 0) { 906 dev_err(dev, "Self-test zero setup failed\n"); 907 err = -ENODEV; 908 goto dma_unmap; 909 } 910 dma->device_issue_pending(dma_chan); 911 912 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 913 914 if (tmo == 0 || 915 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 916 dev_err(dev, "Self-test validate timed out\n"); 917 err = -ENODEV; 918 goto dma_unmap; 919 } 920 921 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 922 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 923 924 if (xor_val_result != 0) { 925 dev_err(dev, "Self-test validate failed compare\n"); 926 err = -ENODEV; 927 goto free_resources; 928 } 929 930 memset(page_address(dest), 0, PAGE_SIZE); 931 932 /* test for non-zero parity sum */ 933 op = IOAT_OP_XOR_VAL; 934 935 xor_val_result = 0; 936 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 937 dma_srcs[i] = DMA_ERROR_CODE; 938 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 939 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 940 DMA_TO_DEVICE); 941 if (dma_mapping_error(dev, dma_srcs[i])) 942 goto dma_unmap; 943 } 944 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 945 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 946 &xor_val_result, DMA_PREP_INTERRUPT); 947 if (!tx) { 948 dev_err(dev, "Self-test 2nd zero prep failed\n"); 949 err = -ENODEV; 950 goto dma_unmap; 951 } 952 953 async_tx_ack(tx); 954 init_completion(&cmp); 955 tx->callback = ioat_dma_test_callback; 956 tx->callback_param = &cmp; 957 cookie = tx->tx_submit(tx); 958 if (cookie < 0) { 959 dev_err(dev, "Self-test 2nd zero setup failed\n"); 960 err = -ENODEV; 961 goto dma_unmap; 962 } 963 dma->device_issue_pending(dma_chan); 964 965 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 966 967 if (tmo == 0 || 968 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 969 dev_err(dev, "Self-test 2nd validate timed out\n"); 970 err = -ENODEV; 971 goto dma_unmap; 972 } 973 974 if (xor_val_result != SUM_CHECK_P_RESULT) { 975 dev_err(dev, "Self-test validate failed compare\n"); 976 err = -ENODEV; 977 goto dma_unmap; 978 } 979 980 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 981 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 982 983 goto free_resources; 984 dma_unmap: 985 if (op == IOAT_OP_XOR) { 986 if (dest_dma != DMA_ERROR_CODE) 987 dma_unmap_page(dev, dest_dma, PAGE_SIZE, 988 DMA_FROM_DEVICE); 989 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 990 if (dma_srcs[i] != DMA_ERROR_CODE) 991 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 992 DMA_TO_DEVICE); 993 } else if (op == IOAT_OP_XOR_VAL) { 994 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 995 if (dma_srcs[i] != DMA_ERROR_CODE) 996 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 997 DMA_TO_DEVICE); 998 } 999 free_resources: 1000 dma->device_free_chan_resources(dma_chan); 1001 out: 1002 src_idx = IOAT_NUM_SRC_TEST; 1003 while (src_idx--) 1004 __free_page(xor_srcs[src_idx]); 1005 __free_page(dest); 1006 return err; 1007 } 1008 1009 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) 1010 { 1011 int rc = ioat_dma_self_test(ioat_dma); 1012 1013 if (rc) 1014 return rc; 1015 1016 rc = ioat_xor_val_self_test(ioat_dma); 1017 if (rc) 1018 return rc; 1019 1020 return 0; 1021 } 1022 1023 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma) 1024 { 1025 struct dma_device *dma; 1026 struct dma_chan *c; 1027 struct ioatdma_chan *ioat_chan; 1028 u32 errmask; 1029 1030 dma = &ioat_dma->dma_dev; 1031 1032 /* 1033 * if we have descriptor write back error status, we mask the 1034 * error interrupts 1035 */ 1036 if (ioat_dma->cap & IOAT_CAP_DWBES) { 1037 list_for_each_entry(c, &dma->channels, device_node) { 1038 ioat_chan = to_ioat_chan(c); 1039 errmask = readl(ioat_chan->reg_base + 1040 IOAT_CHANERR_MASK_OFFSET); 1041 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | 1042 IOAT_CHANERR_XOR_Q_ERR; 1043 writel(errmask, ioat_chan->reg_base + 1044 IOAT_CHANERR_MASK_OFFSET); 1045 } 1046 } 1047 } 1048 1049 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 1050 { 1051 struct pci_dev *pdev = ioat_dma->pdev; 1052 int dca_en = system_has_dca_enabled(pdev); 1053 struct dma_device *dma; 1054 struct dma_chan *c; 1055 struct ioatdma_chan *ioat_chan; 1056 bool is_raid_device = false; 1057 int err; 1058 1059 dma = &ioat_dma->dma_dev; 1060 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; 1061 dma->device_issue_pending = ioat_issue_pending; 1062 dma->device_alloc_chan_resources = ioat_alloc_chan_resources; 1063 dma->device_free_chan_resources = ioat_free_chan_resources; 1064 1065 dma_cap_set(DMA_INTERRUPT, dma->cap_mask); 1066 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; 1067 1068 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); 1069 1070 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) 1071 ioat_dma->cap &= 1072 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); 1073 1074 /* dca is incompatible with raid operations */ 1075 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) 1076 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); 1077 1078 if (ioat_dma->cap & IOAT_CAP_XOR) { 1079 is_raid_device = true; 1080 dma->max_xor = 8; 1081 1082 dma_cap_set(DMA_XOR, dma->cap_mask); 1083 dma->device_prep_dma_xor = ioat_prep_xor; 1084 1085 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1086 dma->device_prep_dma_xor_val = ioat_prep_xor_val; 1087 } 1088 1089 if (ioat_dma->cap & IOAT_CAP_PQ) { 1090 is_raid_device = true; 1091 1092 dma->device_prep_dma_pq = ioat_prep_pq; 1093 dma->device_prep_dma_pq_val = ioat_prep_pq_val; 1094 dma_cap_set(DMA_PQ, dma->cap_mask); 1095 dma_cap_set(DMA_PQ_VAL, dma->cap_mask); 1096 1097 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1098 dma_set_maxpq(dma, 16, 0); 1099 else 1100 dma_set_maxpq(dma, 8, 0); 1101 1102 if (!(ioat_dma->cap & IOAT_CAP_XOR)) { 1103 dma->device_prep_dma_xor = ioat_prep_pqxor; 1104 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; 1105 dma_cap_set(DMA_XOR, dma->cap_mask); 1106 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1107 1108 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1109 dma->max_xor = 16; 1110 else 1111 dma->max_xor = 8; 1112 } 1113 } 1114 1115 dma->device_tx_status = ioat_tx_status; 1116 1117 /* starting with CB3.3 super extended descriptors are supported */ 1118 if (ioat_dma->cap & IOAT_CAP_RAID16SS) { 1119 char pool_name[14]; 1120 int i; 1121 1122 for (i = 0; i < MAX_SED_POOLS; i++) { 1123 snprintf(pool_name, 14, "ioat_hw%d_sed", i); 1124 1125 /* allocate SED DMA pool */ 1126 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, 1127 &pdev->dev, 1128 SED_SIZE * (i + 1), 64, 0); 1129 if (!ioat_dma->sed_hw_pool[i]) 1130 return -ENOMEM; 1131 1132 } 1133 } 1134 1135 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) 1136 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1137 1138 err = ioat_probe(ioat_dma); 1139 if (err) 1140 return err; 1141 1142 list_for_each_entry(c, &dma->channels, device_node) { 1143 ioat_chan = to_ioat_chan(c); 1144 writel(IOAT_DMA_DCA_ANY_CPU, 1145 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 1146 } 1147 1148 err = ioat_register(ioat_dma); 1149 if (err) 1150 return err; 1151 1152 ioat_kobject_add(ioat_dma, &ioat_ktype); 1153 1154 if (dca) 1155 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); 1156 1157 return 0; 1158 } 1159 1160 #define DRV_NAME "ioatdma" 1161 1162 static struct pci_driver ioat_pci_driver = { 1163 .name = DRV_NAME, 1164 .id_table = ioat_pci_tbl, 1165 .probe = ioat_pci_probe, 1166 .remove = ioat_remove, 1167 }; 1168 1169 static struct ioatdma_device * 1170 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) 1171 { 1172 struct device *dev = &pdev->dev; 1173 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 1174 1175 if (!d) 1176 return NULL; 1177 d->pdev = pdev; 1178 d->reg_base = iobase; 1179 return d; 1180 } 1181 1182 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1183 { 1184 void __iomem * const *iomap; 1185 struct device *dev = &pdev->dev; 1186 struct ioatdma_device *device; 1187 int err; 1188 1189 err = pcim_enable_device(pdev); 1190 if (err) 1191 return err; 1192 1193 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); 1194 if (err) 1195 return err; 1196 iomap = pcim_iomap_table(pdev); 1197 if (!iomap) 1198 return -ENOMEM; 1199 1200 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1201 if (err) 1202 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1203 if (err) 1204 return err; 1205 1206 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1207 if (err) 1208 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1209 if (err) 1210 return err; 1211 1212 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); 1213 if (!device) 1214 return -ENOMEM; 1215 pci_set_master(pdev); 1216 pci_set_drvdata(pdev, device); 1217 1218 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1219 if (device->version >= IOAT_VER_3_0) 1220 err = ioat3_dma_probe(device, ioat_dca_enabled); 1221 else 1222 return -ENODEV; 1223 1224 if (err) { 1225 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); 1226 return -ENODEV; 1227 } 1228 1229 return 0; 1230 } 1231 1232 static void ioat_remove(struct pci_dev *pdev) 1233 { 1234 struct ioatdma_device *device = pci_get_drvdata(pdev); 1235 1236 if (!device) 1237 return; 1238 1239 dev_err(&pdev->dev, "Removing dma and dca services\n"); 1240 if (device->dca) { 1241 unregister_dca_provider(device->dca, &pdev->dev); 1242 free_dca_provider(device->dca); 1243 device->dca = NULL; 1244 } 1245 ioat_dma_remove(device); 1246 } 1247 1248 static int __init ioat_init_module(void) 1249 { 1250 int err = -ENOMEM; 1251 1252 pr_info("%s: Intel(R) QuickData Technology Driver %s\n", 1253 DRV_NAME, IOAT_DMA_VERSION); 1254 1255 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), 1256 0, SLAB_HWCACHE_ALIGN, NULL); 1257 if (!ioat_cache) 1258 return -ENOMEM; 1259 1260 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); 1261 if (!ioat_sed_cache) 1262 goto err_ioat_cache; 1263 1264 err = pci_register_driver(&ioat_pci_driver); 1265 if (err) 1266 goto err_ioat3_cache; 1267 1268 return 0; 1269 1270 err_ioat3_cache: 1271 kmem_cache_destroy(ioat_sed_cache); 1272 1273 err_ioat_cache: 1274 kmem_cache_destroy(ioat_cache); 1275 1276 return err; 1277 } 1278 module_init(ioat_init_module); 1279 1280 static void __exit ioat_exit_module(void) 1281 { 1282 pci_unregister_driver(&ioat_pci_driver); 1283 kmem_cache_destroy(ioat_cache); 1284 } 1285 module_exit(ioat_exit_module); 1286