1 /* 2 * Intel I/OAT DMA Linux driver 3 * Copyright(c) 2004 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 */ 18 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/slab.h> 22 #include <linux/pci.h> 23 #include <linux/interrupt.h> 24 #include <linux/dmaengine.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/workqueue.h> 28 #include <linux/prefetch.h> 29 #include <linux/dca.h> 30 #include "dma.h" 31 #include "registers.h" 32 #include "hw.h" 33 34 #include "../dmaengine.h" 35 36 MODULE_VERSION(IOAT_DMA_VERSION); 37 MODULE_LICENSE("Dual BSD/GPL"); 38 MODULE_AUTHOR("Intel Corporation"); 39 40 static struct pci_device_id ioat_pci_tbl[] = { 41 /* I/OAT v3 platforms */ 42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, 43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, 44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, 46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, 47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, 48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, 49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, 50 51 /* I/OAT v3.2 platforms */ 52 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, 53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, 54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, 55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, 56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, 57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, 58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, 59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, 60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, 61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, 62 63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, 64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, 65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, 66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, 67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, 68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, 69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, 70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, 71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, 72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, 73 74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, 75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, 76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, 77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, 78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, 79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, 80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, 81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, 82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, 83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, 84 85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, 86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, 87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, 88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, 89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, 90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, 91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, 92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, 93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, 94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, 95 96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) }, 97 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) }, 98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) }, 99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) }, 100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) }, 101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) }, 102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) }, 103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) }, 104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) }, 105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) }, 106 107 /* I/OAT v3.3 platforms */ 108 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 109 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, 110 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, 111 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, 112 113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, 114 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, 115 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, 116 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, 117 118 { 0, } 119 }; 120 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); 121 122 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 123 static void ioat_remove(struct pci_dev *pdev); 124 static void 125 ioat_init_channel(struct ioatdma_device *ioat_dma, 126 struct ioatdma_chan *ioat_chan, int idx); 127 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma); 128 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma); 129 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); 130 131 static int ioat_dca_enabled = 1; 132 module_param(ioat_dca_enabled, int, 0644); 133 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); 134 int ioat_pending_level = 4; 135 module_param(ioat_pending_level, int, 0644); 136 MODULE_PARM_DESC(ioat_pending_level, 137 "high-water mark for pushing ioat descriptors (default: 4)"); 138 int ioat_ring_alloc_order = 8; 139 module_param(ioat_ring_alloc_order, int, 0644); 140 MODULE_PARM_DESC(ioat_ring_alloc_order, 141 "ioat+: allocate 2^n descriptors per channel (default: 8 max: 16)"); 142 int ioat_ring_max_alloc_order = IOAT_MAX_ORDER; 143 module_param(ioat_ring_max_alloc_order, int, 0644); 144 MODULE_PARM_DESC(ioat_ring_max_alloc_order, 145 "ioat+: upper limit for ring size (default: 16)"); 146 static char ioat_interrupt_style[32] = "msix"; 147 module_param_string(ioat_interrupt_style, ioat_interrupt_style, 148 sizeof(ioat_interrupt_style), 0644); 149 MODULE_PARM_DESC(ioat_interrupt_style, 150 "set ioat interrupt style: msix (default), msi, intx"); 151 152 struct kmem_cache *ioat_cache; 153 struct kmem_cache *ioat_sed_cache; 154 155 static bool is_jf_ioat(struct pci_dev *pdev) 156 { 157 switch (pdev->device) { 158 case PCI_DEVICE_ID_INTEL_IOAT_JSF0: 159 case PCI_DEVICE_ID_INTEL_IOAT_JSF1: 160 case PCI_DEVICE_ID_INTEL_IOAT_JSF2: 161 case PCI_DEVICE_ID_INTEL_IOAT_JSF3: 162 case PCI_DEVICE_ID_INTEL_IOAT_JSF4: 163 case PCI_DEVICE_ID_INTEL_IOAT_JSF5: 164 case PCI_DEVICE_ID_INTEL_IOAT_JSF6: 165 case PCI_DEVICE_ID_INTEL_IOAT_JSF7: 166 case PCI_DEVICE_ID_INTEL_IOAT_JSF8: 167 case PCI_DEVICE_ID_INTEL_IOAT_JSF9: 168 return true; 169 default: 170 return false; 171 } 172 } 173 174 static bool is_snb_ioat(struct pci_dev *pdev) 175 { 176 switch (pdev->device) { 177 case PCI_DEVICE_ID_INTEL_IOAT_SNB0: 178 case PCI_DEVICE_ID_INTEL_IOAT_SNB1: 179 case PCI_DEVICE_ID_INTEL_IOAT_SNB2: 180 case PCI_DEVICE_ID_INTEL_IOAT_SNB3: 181 case PCI_DEVICE_ID_INTEL_IOAT_SNB4: 182 case PCI_DEVICE_ID_INTEL_IOAT_SNB5: 183 case PCI_DEVICE_ID_INTEL_IOAT_SNB6: 184 case PCI_DEVICE_ID_INTEL_IOAT_SNB7: 185 case PCI_DEVICE_ID_INTEL_IOAT_SNB8: 186 case PCI_DEVICE_ID_INTEL_IOAT_SNB9: 187 return true; 188 default: 189 return false; 190 } 191 } 192 193 static bool is_ivb_ioat(struct pci_dev *pdev) 194 { 195 switch (pdev->device) { 196 case PCI_DEVICE_ID_INTEL_IOAT_IVB0: 197 case PCI_DEVICE_ID_INTEL_IOAT_IVB1: 198 case PCI_DEVICE_ID_INTEL_IOAT_IVB2: 199 case PCI_DEVICE_ID_INTEL_IOAT_IVB3: 200 case PCI_DEVICE_ID_INTEL_IOAT_IVB4: 201 case PCI_DEVICE_ID_INTEL_IOAT_IVB5: 202 case PCI_DEVICE_ID_INTEL_IOAT_IVB6: 203 case PCI_DEVICE_ID_INTEL_IOAT_IVB7: 204 case PCI_DEVICE_ID_INTEL_IOAT_IVB8: 205 case PCI_DEVICE_ID_INTEL_IOAT_IVB9: 206 return true; 207 default: 208 return false; 209 } 210 211 } 212 213 static bool is_hsw_ioat(struct pci_dev *pdev) 214 { 215 switch (pdev->device) { 216 case PCI_DEVICE_ID_INTEL_IOAT_HSW0: 217 case PCI_DEVICE_ID_INTEL_IOAT_HSW1: 218 case PCI_DEVICE_ID_INTEL_IOAT_HSW2: 219 case PCI_DEVICE_ID_INTEL_IOAT_HSW3: 220 case PCI_DEVICE_ID_INTEL_IOAT_HSW4: 221 case PCI_DEVICE_ID_INTEL_IOAT_HSW5: 222 case PCI_DEVICE_ID_INTEL_IOAT_HSW6: 223 case PCI_DEVICE_ID_INTEL_IOAT_HSW7: 224 case PCI_DEVICE_ID_INTEL_IOAT_HSW8: 225 case PCI_DEVICE_ID_INTEL_IOAT_HSW9: 226 return true; 227 default: 228 return false; 229 } 230 231 } 232 233 static bool is_bdx_ioat(struct pci_dev *pdev) 234 { 235 switch (pdev->device) { 236 case PCI_DEVICE_ID_INTEL_IOAT_BDX0: 237 case PCI_DEVICE_ID_INTEL_IOAT_BDX1: 238 case PCI_DEVICE_ID_INTEL_IOAT_BDX2: 239 case PCI_DEVICE_ID_INTEL_IOAT_BDX3: 240 case PCI_DEVICE_ID_INTEL_IOAT_BDX4: 241 case PCI_DEVICE_ID_INTEL_IOAT_BDX5: 242 case PCI_DEVICE_ID_INTEL_IOAT_BDX6: 243 case PCI_DEVICE_ID_INTEL_IOAT_BDX7: 244 case PCI_DEVICE_ID_INTEL_IOAT_BDX8: 245 case PCI_DEVICE_ID_INTEL_IOAT_BDX9: 246 return true; 247 default: 248 return false; 249 } 250 } 251 252 static bool is_xeon_cb32(struct pci_dev *pdev) 253 { 254 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 255 is_hsw_ioat(pdev) || is_bdx_ioat(pdev); 256 } 257 258 bool is_bwd_ioat(struct pci_dev *pdev) 259 { 260 switch (pdev->device) { 261 case PCI_DEVICE_ID_INTEL_IOAT_BWD0: 262 case PCI_DEVICE_ID_INTEL_IOAT_BWD1: 263 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 264 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 265 /* even though not Atom, BDX-DE has same DMA silicon */ 266 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 267 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 268 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 269 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 270 return true; 271 default: 272 return false; 273 } 274 } 275 276 static bool is_bwd_noraid(struct pci_dev *pdev) 277 { 278 switch (pdev->device) { 279 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 280 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 281 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 282 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 283 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 284 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 285 return true; 286 default: 287 return false; 288 } 289 290 } 291 292 /* 293 * Perform a IOAT transaction to verify the HW works. 294 */ 295 #define IOAT_TEST_SIZE 2000 296 297 static void ioat_dma_test_callback(void *dma_async_param) 298 { 299 struct completion *cmp = dma_async_param; 300 301 complete(cmp); 302 } 303 304 /** 305 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. 306 * @ioat_dma: dma device to be tested 307 */ 308 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) 309 { 310 int i; 311 u8 *src; 312 u8 *dest; 313 struct dma_device *dma = &ioat_dma->dma_dev; 314 struct device *dev = &ioat_dma->pdev->dev; 315 struct dma_chan *dma_chan; 316 struct dma_async_tx_descriptor *tx; 317 dma_addr_t dma_dest, dma_src; 318 dma_cookie_t cookie; 319 int err = 0; 320 struct completion cmp; 321 unsigned long tmo; 322 unsigned long flags; 323 324 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); 325 if (!src) 326 return -ENOMEM; 327 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); 328 if (!dest) { 329 kfree(src); 330 return -ENOMEM; 331 } 332 333 /* Fill in src buffer */ 334 for (i = 0; i < IOAT_TEST_SIZE; i++) 335 src[i] = (u8)i; 336 337 /* Start copy, using first DMA channel */ 338 dma_chan = container_of(dma->channels.next, struct dma_chan, 339 device_node); 340 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 341 dev_err(dev, "selftest cannot allocate chan resource\n"); 342 err = -ENODEV; 343 goto out; 344 } 345 346 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 347 if (dma_mapping_error(dev, dma_src)) { 348 dev_err(dev, "mapping src buffer failed\n"); 349 goto free_resources; 350 } 351 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 352 if (dma_mapping_error(dev, dma_dest)) { 353 dev_err(dev, "mapping dest buffer failed\n"); 354 goto unmap_src; 355 } 356 flags = DMA_PREP_INTERRUPT; 357 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, 358 dma_src, IOAT_TEST_SIZE, 359 flags); 360 if (!tx) { 361 dev_err(dev, "Self-test prep failed, disabling\n"); 362 err = -ENODEV; 363 goto unmap_dma; 364 } 365 366 async_tx_ack(tx); 367 init_completion(&cmp); 368 tx->callback = ioat_dma_test_callback; 369 tx->callback_param = &cmp; 370 cookie = tx->tx_submit(tx); 371 if (cookie < 0) { 372 dev_err(dev, "Self-test setup failed, disabling\n"); 373 err = -ENODEV; 374 goto unmap_dma; 375 } 376 dma->device_issue_pending(dma_chan); 377 378 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 379 380 if (tmo == 0 || 381 dma->device_tx_status(dma_chan, cookie, NULL) 382 != DMA_COMPLETE) { 383 dev_err(dev, "Self-test copy timed out, disabling\n"); 384 err = -ENODEV; 385 goto unmap_dma; 386 } 387 if (memcmp(src, dest, IOAT_TEST_SIZE)) { 388 dev_err(dev, "Self-test copy failed compare, disabling\n"); 389 err = -ENODEV; 390 goto free_resources; 391 } 392 393 unmap_dma: 394 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 395 unmap_src: 396 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 397 free_resources: 398 dma->device_free_chan_resources(dma_chan); 399 out: 400 kfree(src); 401 kfree(dest); 402 return err; 403 } 404 405 /** 406 * ioat_dma_setup_interrupts - setup interrupt handler 407 * @ioat_dma: ioat dma device 408 */ 409 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) 410 { 411 struct ioatdma_chan *ioat_chan; 412 struct pci_dev *pdev = ioat_dma->pdev; 413 struct device *dev = &pdev->dev; 414 struct msix_entry *msix; 415 int i, j, msixcnt; 416 int err = -EINVAL; 417 u8 intrctrl = 0; 418 419 if (!strcmp(ioat_interrupt_style, "msix")) 420 goto msix; 421 if (!strcmp(ioat_interrupt_style, "msi")) 422 goto msi; 423 if (!strcmp(ioat_interrupt_style, "intx")) 424 goto intx; 425 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); 426 goto err_no_irq; 427 428 msix: 429 /* The number of MSI-X vectors should equal the number of channels */ 430 msixcnt = ioat_dma->dma_dev.chancnt; 431 for (i = 0; i < msixcnt; i++) 432 ioat_dma->msix_entries[i].entry = i; 433 434 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); 435 if (err) 436 goto msi; 437 438 for (i = 0; i < msixcnt; i++) { 439 msix = &ioat_dma->msix_entries[i]; 440 ioat_chan = ioat_chan_by_index(ioat_dma, i); 441 err = devm_request_irq(dev, msix->vector, 442 ioat_dma_do_interrupt_msix, 0, 443 "ioat-msix", ioat_chan); 444 if (err) { 445 for (j = 0; j < i; j++) { 446 msix = &ioat_dma->msix_entries[j]; 447 ioat_chan = ioat_chan_by_index(ioat_dma, j); 448 devm_free_irq(dev, msix->vector, ioat_chan); 449 } 450 goto msi; 451 } 452 } 453 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; 454 ioat_dma->irq_mode = IOAT_MSIX; 455 goto done; 456 457 msi: 458 err = pci_enable_msi(pdev); 459 if (err) 460 goto intx; 461 462 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, 463 "ioat-msi", ioat_dma); 464 if (err) { 465 pci_disable_msi(pdev); 466 goto intx; 467 } 468 ioat_dma->irq_mode = IOAT_MSI; 469 goto done; 470 471 intx: 472 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 473 IRQF_SHARED, "ioat-intx", ioat_dma); 474 if (err) 475 goto err_no_irq; 476 477 ioat_dma->irq_mode = IOAT_INTX; 478 done: 479 if (is_bwd_ioat(pdev)) 480 ioat_intr_quirk(ioat_dma); 481 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; 482 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 483 return 0; 484 485 err_no_irq: 486 /* Disable all interrupt generation */ 487 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 488 ioat_dma->irq_mode = IOAT_NOIRQ; 489 dev_err(dev, "no usable interrupts\n"); 490 return err; 491 } 492 493 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) 494 { 495 /* Disable all interrupt generation */ 496 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 497 } 498 499 static int ioat_probe(struct ioatdma_device *ioat_dma) 500 { 501 int err = -ENODEV; 502 struct dma_device *dma = &ioat_dma->dma_dev; 503 struct pci_dev *pdev = ioat_dma->pdev; 504 struct device *dev = &pdev->dev; 505 506 /* DMA coherent memory pool for DMA descriptor allocations */ 507 ioat_dma->dma_pool = pci_pool_create("dma_desc_pool", pdev, 508 sizeof(struct ioat_dma_descriptor), 509 64, 0); 510 if (!ioat_dma->dma_pool) { 511 err = -ENOMEM; 512 goto err_dma_pool; 513 } 514 515 ioat_dma->completion_pool = pci_pool_create("completion_pool", pdev, 516 sizeof(u64), 517 SMP_CACHE_BYTES, 518 SMP_CACHE_BYTES); 519 520 if (!ioat_dma->completion_pool) { 521 err = -ENOMEM; 522 goto err_completion_pool; 523 } 524 525 ioat_enumerate_channels(ioat_dma); 526 527 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 528 dma->dev = &pdev->dev; 529 530 if (!dma->chancnt) { 531 dev_err(dev, "channel enumeration error\n"); 532 goto err_setup_interrupts; 533 } 534 535 err = ioat_dma_setup_interrupts(ioat_dma); 536 if (err) 537 goto err_setup_interrupts; 538 539 err = ioat3_dma_self_test(ioat_dma); 540 if (err) 541 goto err_self_test; 542 543 return 0; 544 545 err_self_test: 546 ioat_disable_interrupts(ioat_dma); 547 err_setup_interrupts: 548 pci_pool_destroy(ioat_dma->completion_pool); 549 err_completion_pool: 550 pci_pool_destroy(ioat_dma->dma_pool); 551 err_dma_pool: 552 return err; 553 } 554 555 static int ioat_register(struct ioatdma_device *ioat_dma) 556 { 557 int err = dma_async_device_register(&ioat_dma->dma_dev); 558 559 if (err) { 560 ioat_disable_interrupts(ioat_dma); 561 pci_pool_destroy(ioat_dma->completion_pool); 562 pci_pool_destroy(ioat_dma->dma_pool); 563 } 564 565 return err; 566 } 567 568 static void ioat_dma_remove(struct ioatdma_device *ioat_dma) 569 { 570 struct dma_device *dma = &ioat_dma->dma_dev; 571 572 ioat_disable_interrupts(ioat_dma); 573 574 ioat_kobject_del(ioat_dma); 575 576 dma_async_device_unregister(dma); 577 578 pci_pool_destroy(ioat_dma->dma_pool); 579 pci_pool_destroy(ioat_dma->completion_pool); 580 581 INIT_LIST_HEAD(&dma->channels); 582 } 583 584 /** 585 * ioat_enumerate_channels - find and initialize the device's channels 586 * @ioat_dma: the ioat dma device to be enumerated 587 */ 588 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma) 589 { 590 struct ioatdma_chan *ioat_chan; 591 struct device *dev = &ioat_dma->pdev->dev; 592 struct dma_device *dma = &ioat_dma->dma_dev; 593 u8 xfercap_log; 594 int i; 595 596 INIT_LIST_HEAD(&dma->channels); 597 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); 598 dma->chancnt &= 0x1f; /* bits [4:0] valid */ 599 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) { 600 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", 601 dma->chancnt, ARRAY_SIZE(ioat_dma->idx)); 602 dma->chancnt = ARRAY_SIZE(ioat_dma->idx); 603 } 604 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); 605 xfercap_log &= 0x1f; /* bits [4:0] valid */ 606 if (xfercap_log == 0) 607 return 0; 608 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); 609 610 for (i = 0; i < dma->chancnt; i++) { 611 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); 612 if (!ioat_chan) 613 break; 614 615 ioat_init_channel(ioat_dma, ioat_chan, i); 616 ioat_chan->xfercap_log = xfercap_log; 617 spin_lock_init(&ioat_chan->prep_lock); 618 if (ioat_reset_hw(ioat_chan)) { 619 i = 0; 620 break; 621 } 622 } 623 dma->chancnt = i; 624 return i; 625 } 626 627 /** 628 * ioat_free_chan_resources - release all the descriptors 629 * @chan: the channel to be cleaned 630 */ 631 static void ioat_free_chan_resources(struct dma_chan *c) 632 { 633 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 634 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; 635 struct ioat_ring_ent *desc; 636 const int total_descs = 1 << ioat_chan->alloc_order; 637 int descs; 638 int i; 639 640 /* Before freeing channel resources first check 641 * if they have been previously allocated for this channel. 642 */ 643 if (!ioat_chan->ring) 644 return; 645 646 ioat_stop(ioat_chan); 647 ioat_reset_hw(ioat_chan); 648 649 spin_lock_bh(&ioat_chan->cleanup_lock); 650 spin_lock_bh(&ioat_chan->prep_lock); 651 descs = ioat_ring_space(ioat_chan); 652 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); 653 for (i = 0; i < descs; i++) { 654 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); 655 ioat_free_ring_ent(desc, c); 656 } 657 658 if (descs < total_descs) 659 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", 660 total_descs - descs); 661 662 for (i = 0; i < total_descs - descs; i++) { 663 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); 664 dump_desc_dbg(ioat_chan, desc); 665 ioat_free_ring_ent(desc, c); 666 } 667 668 kfree(ioat_chan->ring); 669 ioat_chan->ring = NULL; 670 ioat_chan->alloc_order = 0; 671 pci_pool_free(ioat_dma->completion_pool, ioat_chan->completion, 672 ioat_chan->completion_dma); 673 spin_unlock_bh(&ioat_chan->prep_lock); 674 spin_unlock_bh(&ioat_chan->cleanup_lock); 675 676 ioat_chan->last_completion = 0; 677 ioat_chan->completion_dma = 0; 678 ioat_chan->dmacount = 0; 679 } 680 681 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring 682 * @chan: channel to be initialized 683 */ 684 static int ioat_alloc_chan_resources(struct dma_chan *c) 685 { 686 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 687 struct ioat_ring_ent **ring; 688 u64 status; 689 int order; 690 int i = 0; 691 u32 chanerr; 692 693 /* have we already been set up? */ 694 if (ioat_chan->ring) 695 return 1 << ioat_chan->alloc_order; 696 697 /* Setup register to interrupt and write completion status on error */ 698 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); 699 700 /* allocate a completion writeback area */ 701 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 702 ioat_chan->completion = 703 pci_pool_alloc(ioat_chan->ioat_dma->completion_pool, 704 GFP_KERNEL, &ioat_chan->completion_dma); 705 if (!ioat_chan->completion) 706 return -ENOMEM; 707 708 memset(ioat_chan->completion, 0, sizeof(*ioat_chan->completion)); 709 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, 710 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); 711 writel(((u64)ioat_chan->completion_dma) >> 32, 712 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 713 714 order = ioat_get_alloc_order(); 715 ring = ioat_alloc_ring(c, order, GFP_KERNEL); 716 if (!ring) 717 return -ENOMEM; 718 719 spin_lock_bh(&ioat_chan->cleanup_lock); 720 spin_lock_bh(&ioat_chan->prep_lock); 721 ioat_chan->ring = ring; 722 ioat_chan->head = 0; 723 ioat_chan->issued = 0; 724 ioat_chan->tail = 0; 725 ioat_chan->alloc_order = order; 726 set_bit(IOAT_RUN, &ioat_chan->state); 727 spin_unlock_bh(&ioat_chan->prep_lock); 728 spin_unlock_bh(&ioat_chan->cleanup_lock); 729 730 ioat_start_null_desc(ioat_chan); 731 732 /* check that we got off the ground */ 733 do { 734 udelay(1); 735 status = ioat_chansts(ioat_chan); 736 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); 737 738 if (is_ioat_active(status) || is_ioat_idle(status)) 739 return 1 << ioat_chan->alloc_order; 740 741 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 742 743 dev_WARN(to_dev(ioat_chan), 744 "failed to start channel chanerr: %#x\n", chanerr); 745 ioat_free_chan_resources(c); 746 return -EFAULT; 747 } 748 749 /* common channel initialization */ 750 static void 751 ioat_init_channel(struct ioatdma_device *ioat_dma, 752 struct ioatdma_chan *ioat_chan, int idx) 753 { 754 struct dma_device *dma = &ioat_dma->dma_dev; 755 struct dma_chan *c = &ioat_chan->dma_chan; 756 unsigned long data = (unsigned long) c; 757 758 ioat_chan->ioat_dma = ioat_dma; 759 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); 760 spin_lock_init(&ioat_chan->cleanup_lock); 761 ioat_chan->dma_chan.device = dma; 762 dma_cookie_init(&ioat_chan->dma_chan); 763 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); 764 ioat_dma->idx[idx] = ioat_chan; 765 init_timer(&ioat_chan->timer); 766 ioat_chan->timer.function = ioat_timer_event; 767 ioat_chan->timer.data = data; 768 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data); 769 } 770 771 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ 772 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) 773 { 774 int i, src_idx; 775 struct page *dest; 776 struct page *xor_srcs[IOAT_NUM_SRC_TEST]; 777 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; 778 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; 779 dma_addr_t dest_dma; 780 struct dma_async_tx_descriptor *tx; 781 struct dma_chan *dma_chan; 782 dma_cookie_t cookie; 783 u8 cmp_byte = 0; 784 u32 cmp_word; 785 u32 xor_val_result; 786 int err = 0; 787 struct completion cmp; 788 unsigned long tmo; 789 struct device *dev = &ioat_dma->pdev->dev; 790 struct dma_device *dma = &ioat_dma->dma_dev; 791 u8 op = 0; 792 793 dev_dbg(dev, "%s\n", __func__); 794 795 if (!dma_has_cap(DMA_XOR, dma->cap_mask)) 796 return 0; 797 798 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 799 xor_srcs[src_idx] = alloc_page(GFP_KERNEL); 800 if (!xor_srcs[src_idx]) { 801 while (src_idx--) 802 __free_page(xor_srcs[src_idx]); 803 return -ENOMEM; 804 } 805 } 806 807 dest = alloc_page(GFP_KERNEL); 808 if (!dest) { 809 while (src_idx--) 810 __free_page(xor_srcs[src_idx]); 811 return -ENOMEM; 812 } 813 814 /* Fill in src buffers */ 815 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 816 u8 *ptr = page_address(xor_srcs[src_idx]); 817 818 for (i = 0; i < PAGE_SIZE; i++) 819 ptr[i] = (1 << src_idx); 820 } 821 822 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) 823 cmp_byte ^= (u8) (1 << src_idx); 824 825 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | 826 (cmp_byte << 8) | cmp_byte; 827 828 memset(page_address(dest), 0, PAGE_SIZE); 829 830 dma_chan = container_of(dma->channels.next, struct dma_chan, 831 device_node); 832 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 833 err = -ENODEV; 834 goto out; 835 } 836 837 /* test xor */ 838 op = IOAT_OP_XOR; 839 840 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); 841 if (dma_mapping_error(dev, dest_dma)) 842 goto dma_unmap; 843 844 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 845 dma_srcs[i] = DMA_ERROR_CODE; 846 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { 847 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, 848 DMA_TO_DEVICE); 849 if (dma_mapping_error(dev, dma_srcs[i])) 850 goto dma_unmap; 851 } 852 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, 853 IOAT_NUM_SRC_TEST, PAGE_SIZE, 854 DMA_PREP_INTERRUPT); 855 856 if (!tx) { 857 dev_err(dev, "Self-test xor prep failed\n"); 858 err = -ENODEV; 859 goto dma_unmap; 860 } 861 862 async_tx_ack(tx); 863 init_completion(&cmp); 864 tx->callback = ioat_dma_test_callback; 865 tx->callback_param = &cmp; 866 cookie = tx->tx_submit(tx); 867 if (cookie < 0) { 868 dev_err(dev, "Self-test xor setup failed\n"); 869 err = -ENODEV; 870 goto dma_unmap; 871 } 872 dma->device_issue_pending(dma_chan); 873 874 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 875 876 if (tmo == 0 || 877 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 878 dev_err(dev, "Self-test xor timed out\n"); 879 err = -ENODEV; 880 goto dma_unmap; 881 } 882 883 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 884 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 885 886 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 887 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { 888 u32 *ptr = page_address(dest); 889 890 if (ptr[i] != cmp_word) { 891 dev_err(dev, "Self-test xor failed compare\n"); 892 err = -ENODEV; 893 goto free_resources; 894 } 895 } 896 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 897 898 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 899 900 /* skip validate if the capability is not present */ 901 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) 902 goto free_resources; 903 904 op = IOAT_OP_XOR_VAL; 905 906 /* validate the sources with the destintation page */ 907 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 908 xor_val_srcs[i] = xor_srcs[i]; 909 xor_val_srcs[i] = dest; 910 911 xor_val_result = 1; 912 913 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 914 dma_srcs[i] = DMA_ERROR_CODE; 915 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 916 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 917 DMA_TO_DEVICE); 918 if (dma_mapping_error(dev, dma_srcs[i])) 919 goto dma_unmap; 920 } 921 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 922 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 923 &xor_val_result, DMA_PREP_INTERRUPT); 924 if (!tx) { 925 dev_err(dev, "Self-test zero prep failed\n"); 926 err = -ENODEV; 927 goto dma_unmap; 928 } 929 930 async_tx_ack(tx); 931 init_completion(&cmp); 932 tx->callback = ioat_dma_test_callback; 933 tx->callback_param = &cmp; 934 cookie = tx->tx_submit(tx); 935 if (cookie < 0) { 936 dev_err(dev, "Self-test zero setup failed\n"); 937 err = -ENODEV; 938 goto dma_unmap; 939 } 940 dma->device_issue_pending(dma_chan); 941 942 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 943 944 if (tmo == 0 || 945 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 946 dev_err(dev, "Self-test validate timed out\n"); 947 err = -ENODEV; 948 goto dma_unmap; 949 } 950 951 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 952 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 953 954 if (xor_val_result != 0) { 955 dev_err(dev, "Self-test validate failed compare\n"); 956 err = -ENODEV; 957 goto free_resources; 958 } 959 960 memset(page_address(dest), 0, PAGE_SIZE); 961 962 /* test for non-zero parity sum */ 963 op = IOAT_OP_XOR_VAL; 964 965 xor_val_result = 0; 966 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 967 dma_srcs[i] = DMA_ERROR_CODE; 968 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 969 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 970 DMA_TO_DEVICE); 971 if (dma_mapping_error(dev, dma_srcs[i])) 972 goto dma_unmap; 973 } 974 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 975 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 976 &xor_val_result, DMA_PREP_INTERRUPT); 977 if (!tx) { 978 dev_err(dev, "Self-test 2nd zero prep failed\n"); 979 err = -ENODEV; 980 goto dma_unmap; 981 } 982 983 async_tx_ack(tx); 984 init_completion(&cmp); 985 tx->callback = ioat_dma_test_callback; 986 tx->callback_param = &cmp; 987 cookie = tx->tx_submit(tx); 988 if (cookie < 0) { 989 dev_err(dev, "Self-test 2nd zero setup failed\n"); 990 err = -ENODEV; 991 goto dma_unmap; 992 } 993 dma->device_issue_pending(dma_chan); 994 995 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 996 997 if (tmo == 0 || 998 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 999 dev_err(dev, "Self-test 2nd validate timed out\n"); 1000 err = -ENODEV; 1001 goto dma_unmap; 1002 } 1003 1004 if (xor_val_result != SUM_CHECK_P_RESULT) { 1005 dev_err(dev, "Self-test validate failed compare\n"); 1006 err = -ENODEV; 1007 goto dma_unmap; 1008 } 1009 1010 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 1011 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 1012 1013 goto free_resources; 1014 dma_unmap: 1015 if (op == IOAT_OP_XOR) { 1016 if (dest_dma != DMA_ERROR_CODE) 1017 dma_unmap_page(dev, dest_dma, PAGE_SIZE, 1018 DMA_FROM_DEVICE); 1019 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 1020 if (dma_srcs[i] != DMA_ERROR_CODE) 1021 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1022 DMA_TO_DEVICE); 1023 } else if (op == IOAT_OP_XOR_VAL) { 1024 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 1025 if (dma_srcs[i] != DMA_ERROR_CODE) 1026 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1027 DMA_TO_DEVICE); 1028 } 1029 free_resources: 1030 dma->device_free_chan_resources(dma_chan); 1031 out: 1032 src_idx = IOAT_NUM_SRC_TEST; 1033 while (src_idx--) 1034 __free_page(xor_srcs[src_idx]); 1035 __free_page(dest); 1036 return err; 1037 } 1038 1039 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) 1040 { 1041 int rc; 1042 1043 rc = ioat_dma_self_test(ioat_dma); 1044 if (rc) 1045 return rc; 1046 1047 rc = ioat_xor_val_self_test(ioat_dma); 1048 1049 return rc; 1050 } 1051 1052 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma) 1053 { 1054 struct dma_device *dma; 1055 struct dma_chan *c; 1056 struct ioatdma_chan *ioat_chan; 1057 u32 errmask; 1058 1059 dma = &ioat_dma->dma_dev; 1060 1061 /* 1062 * if we have descriptor write back error status, we mask the 1063 * error interrupts 1064 */ 1065 if (ioat_dma->cap & IOAT_CAP_DWBES) { 1066 list_for_each_entry(c, &dma->channels, device_node) { 1067 ioat_chan = to_ioat_chan(c); 1068 errmask = readl(ioat_chan->reg_base + 1069 IOAT_CHANERR_MASK_OFFSET); 1070 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | 1071 IOAT_CHANERR_XOR_Q_ERR; 1072 writel(errmask, ioat_chan->reg_base + 1073 IOAT_CHANERR_MASK_OFFSET); 1074 } 1075 } 1076 } 1077 1078 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 1079 { 1080 struct pci_dev *pdev = ioat_dma->pdev; 1081 int dca_en = system_has_dca_enabled(pdev); 1082 struct dma_device *dma; 1083 struct dma_chan *c; 1084 struct ioatdma_chan *ioat_chan; 1085 bool is_raid_device = false; 1086 int err; 1087 1088 dma = &ioat_dma->dma_dev; 1089 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; 1090 dma->device_issue_pending = ioat_issue_pending; 1091 dma->device_alloc_chan_resources = ioat_alloc_chan_resources; 1092 dma->device_free_chan_resources = ioat_free_chan_resources; 1093 1094 dma_cap_set(DMA_INTERRUPT, dma->cap_mask); 1095 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; 1096 1097 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); 1098 1099 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) 1100 ioat_dma->cap &= 1101 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); 1102 1103 /* dca is incompatible with raid operations */ 1104 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) 1105 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); 1106 1107 if (ioat_dma->cap & IOAT_CAP_XOR) { 1108 is_raid_device = true; 1109 dma->max_xor = 8; 1110 1111 dma_cap_set(DMA_XOR, dma->cap_mask); 1112 dma->device_prep_dma_xor = ioat_prep_xor; 1113 1114 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1115 dma->device_prep_dma_xor_val = ioat_prep_xor_val; 1116 } 1117 1118 if (ioat_dma->cap & IOAT_CAP_PQ) { 1119 is_raid_device = true; 1120 1121 dma->device_prep_dma_pq = ioat_prep_pq; 1122 dma->device_prep_dma_pq_val = ioat_prep_pq_val; 1123 dma_cap_set(DMA_PQ, dma->cap_mask); 1124 dma_cap_set(DMA_PQ_VAL, dma->cap_mask); 1125 1126 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1127 dma_set_maxpq(dma, 16, 0); 1128 else 1129 dma_set_maxpq(dma, 8, 0); 1130 1131 if (!(ioat_dma->cap & IOAT_CAP_XOR)) { 1132 dma->device_prep_dma_xor = ioat_prep_pqxor; 1133 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; 1134 dma_cap_set(DMA_XOR, dma->cap_mask); 1135 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1136 1137 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1138 dma->max_xor = 16; 1139 else 1140 dma->max_xor = 8; 1141 } 1142 } 1143 1144 dma->device_tx_status = ioat_tx_status; 1145 1146 /* starting with CB3.3 super extended descriptors are supported */ 1147 if (ioat_dma->cap & IOAT_CAP_RAID16SS) { 1148 char pool_name[14]; 1149 int i; 1150 1151 for (i = 0; i < MAX_SED_POOLS; i++) { 1152 snprintf(pool_name, 14, "ioat_hw%d_sed", i); 1153 1154 /* allocate SED DMA pool */ 1155 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, 1156 &pdev->dev, 1157 SED_SIZE * (i + 1), 64, 0); 1158 if (!ioat_dma->sed_hw_pool[i]) 1159 return -ENOMEM; 1160 1161 } 1162 } 1163 1164 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) 1165 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1166 1167 err = ioat_probe(ioat_dma); 1168 if (err) 1169 return err; 1170 1171 list_for_each_entry(c, &dma->channels, device_node) { 1172 ioat_chan = to_ioat_chan(c); 1173 writel(IOAT_DMA_DCA_ANY_CPU, 1174 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 1175 } 1176 1177 err = ioat_register(ioat_dma); 1178 if (err) 1179 return err; 1180 1181 ioat_kobject_add(ioat_dma, &ioat_ktype); 1182 1183 if (dca) 1184 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); 1185 1186 return 0; 1187 } 1188 1189 static void ioat_shutdown(struct pci_dev *pdev) 1190 { 1191 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1192 struct ioatdma_chan *ioat_chan; 1193 int i; 1194 1195 if (!ioat_dma) 1196 return; 1197 1198 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1199 ioat_chan = ioat_dma->idx[i]; 1200 if (!ioat_chan) 1201 continue; 1202 1203 spin_lock_bh(&ioat_chan->prep_lock); 1204 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1205 del_timer_sync(&ioat_chan->timer); 1206 spin_unlock_bh(&ioat_chan->prep_lock); 1207 /* this should quiesce then reset */ 1208 ioat_reset_hw(ioat_chan); 1209 } 1210 1211 ioat_disable_interrupts(ioat_dma); 1212 } 1213 1214 #define DRV_NAME "ioatdma" 1215 1216 static struct pci_driver ioat_pci_driver = { 1217 .name = DRV_NAME, 1218 .id_table = ioat_pci_tbl, 1219 .probe = ioat_pci_probe, 1220 .remove = ioat_remove, 1221 .shutdown = ioat_shutdown, 1222 }; 1223 1224 static struct ioatdma_device * 1225 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) 1226 { 1227 struct device *dev = &pdev->dev; 1228 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 1229 1230 if (!d) 1231 return NULL; 1232 d->pdev = pdev; 1233 d->reg_base = iobase; 1234 return d; 1235 } 1236 1237 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1238 { 1239 void __iomem * const *iomap; 1240 struct device *dev = &pdev->dev; 1241 struct ioatdma_device *device; 1242 int err; 1243 1244 err = pcim_enable_device(pdev); 1245 if (err) 1246 return err; 1247 1248 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); 1249 if (err) 1250 return err; 1251 iomap = pcim_iomap_table(pdev); 1252 if (!iomap) 1253 return -ENOMEM; 1254 1255 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1256 if (err) 1257 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1258 if (err) 1259 return err; 1260 1261 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1262 if (err) 1263 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1264 if (err) 1265 return err; 1266 1267 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); 1268 if (!device) 1269 return -ENOMEM; 1270 pci_set_master(pdev); 1271 pci_set_drvdata(pdev, device); 1272 1273 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1274 if (device->version >= IOAT_VER_3_0) 1275 err = ioat3_dma_probe(device, ioat_dca_enabled); 1276 else 1277 return -ENODEV; 1278 1279 if (err) { 1280 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); 1281 return -ENODEV; 1282 } 1283 1284 return 0; 1285 } 1286 1287 static void ioat_remove(struct pci_dev *pdev) 1288 { 1289 struct ioatdma_device *device = pci_get_drvdata(pdev); 1290 1291 if (!device) 1292 return; 1293 1294 dev_err(&pdev->dev, "Removing dma and dca services\n"); 1295 if (device->dca) { 1296 unregister_dca_provider(device->dca, &pdev->dev); 1297 free_dca_provider(device->dca); 1298 device->dca = NULL; 1299 } 1300 ioat_dma_remove(device); 1301 } 1302 1303 static int __init ioat_init_module(void) 1304 { 1305 int err = -ENOMEM; 1306 1307 pr_info("%s: Intel(R) QuickData Technology Driver %s\n", 1308 DRV_NAME, IOAT_DMA_VERSION); 1309 1310 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), 1311 0, SLAB_HWCACHE_ALIGN, NULL); 1312 if (!ioat_cache) 1313 return -ENOMEM; 1314 1315 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); 1316 if (!ioat_sed_cache) 1317 goto err_ioat_cache; 1318 1319 err = pci_register_driver(&ioat_pci_driver); 1320 if (err) 1321 goto err_ioat3_cache; 1322 1323 return 0; 1324 1325 err_ioat3_cache: 1326 kmem_cache_destroy(ioat_sed_cache); 1327 1328 err_ioat_cache: 1329 kmem_cache_destroy(ioat_cache); 1330 1331 return err; 1332 } 1333 module_init(ioat_init_module); 1334 1335 static void __exit ioat_exit_module(void) 1336 { 1337 pci_unregister_driver(&ioat_pci_driver); 1338 kmem_cache_destroy(ioat_cache); 1339 } 1340 module_exit(ioat_exit_module); 1341