1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel I/OAT DMA Linux driver 4 * Copyright(c) 2004 - 2015 Intel Corporation. 5 */ 6 7 #include <linux/init.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/pci.h> 11 #include <linux/interrupt.h> 12 #include <linux/dmaengine.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/workqueue.h> 16 #include <linux/prefetch.h> 17 #include <linux/dca.h> 18 #include <linux/sizes.h> 19 #include "dma.h" 20 #include "registers.h" 21 #include "hw.h" 22 23 #include "../dmaengine.h" 24 25 MODULE_VERSION(IOAT_DMA_VERSION); 26 MODULE_DESCRIPTION("Intel I/OAT DMA Linux driver"); 27 MODULE_LICENSE("Dual BSD/GPL"); 28 MODULE_AUTHOR("Intel Corporation"); 29 30 static const struct pci_device_id ioat_pci_tbl[] = { 31 /* I/OAT v3 platforms */ 32 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, 33 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, 34 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, 35 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, 36 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, 37 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, 38 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, 39 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, 40 41 /* I/OAT v3.2 platforms */ 42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, 43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, 44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, 46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, 47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, 48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, 49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, 50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, 51 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, 52 53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, 54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, 55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, 56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, 57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, 58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, 59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, 60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, 61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, 62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, 63 64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, 65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, 66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, 67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, 68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, 69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, 70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, 71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, 72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, 73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, 74 75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, 76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, 77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, 78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, 79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, 80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, 81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, 82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, 83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, 84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, 85 86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) }, 87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) }, 88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) }, 89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) }, 90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) }, 91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) }, 92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) }, 93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) }, 94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) }, 95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) }, 96 97 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) }, 98 99 /* I/OAT v3.3 platforms */ 100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, 102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, 103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, 104 105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, 106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, 107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, 108 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, 109 110 /* I/OAT v3.4 platforms */ 111 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_ICX) }, 112 113 { 0, } 114 }; 115 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); 116 117 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 118 static void ioat_remove(struct pci_dev *pdev); 119 static void 120 ioat_init_channel(struct ioatdma_device *ioat_dma, 121 struct ioatdma_chan *ioat_chan, int idx); 122 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma); 123 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma); 124 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); 125 126 static int ioat_dca_enabled = 1; 127 module_param(ioat_dca_enabled, int, 0644); 128 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); 129 int ioat_pending_level = 7; 130 module_param(ioat_pending_level, int, 0644); 131 MODULE_PARM_DESC(ioat_pending_level, 132 "high-water mark for pushing ioat descriptors (default: 7)"); 133 static char ioat_interrupt_style[32] = "msix"; 134 module_param_string(ioat_interrupt_style, ioat_interrupt_style, 135 sizeof(ioat_interrupt_style), 0644); 136 MODULE_PARM_DESC(ioat_interrupt_style, 137 "set ioat interrupt style: msix (default), msi, intx"); 138 139 struct kmem_cache *ioat_cache; 140 struct kmem_cache *ioat_sed_cache; 141 142 static bool is_jf_ioat(struct pci_dev *pdev) 143 { 144 switch (pdev->device) { 145 case PCI_DEVICE_ID_INTEL_IOAT_JSF0: 146 case PCI_DEVICE_ID_INTEL_IOAT_JSF1: 147 case PCI_DEVICE_ID_INTEL_IOAT_JSF2: 148 case PCI_DEVICE_ID_INTEL_IOAT_JSF3: 149 case PCI_DEVICE_ID_INTEL_IOAT_JSF4: 150 case PCI_DEVICE_ID_INTEL_IOAT_JSF5: 151 case PCI_DEVICE_ID_INTEL_IOAT_JSF6: 152 case PCI_DEVICE_ID_INTEL_IOAT_JSF7: 153 case PCI_DEVICE_ID_INTEL_IOAT_JSF8: 154 case PCI_DEVICE_ID_INTEL_IOAT_JSF9: 155 return true; 156 default: 157 return false; 158 } 159 } 160 161 static bool is_snb_ioat(struct pci_dev *pdev) 162 { 163 switch (pdev->device) { 164 case PCI_DEVICE_ID_INTEL_IOAT_SNB0: 165 case PCI_DEVICE_ID_INTEL_IOAT_SNB1: 166 case PCI_DEVICE_ID_INTEL_IOAT_SNB2: 167 case PCI_DEVICE_ID_INTEL_IOAT_SNB3: 168 case PCI_DEVICE_ID_INTEL_IOAT_SNB4: 169 case PCI_DEVICE_ID_INTEL_IOAT_SNB5: 170 case PCI_DEVICE_ID_INTEL_IOAT_SNB6: 171 case PCI_DEVICE_ID_INTEL_IOAT_SNB7: 172 case PCI_DEVICE_ID_INTEL_IOAT_SNB8: 173 case PCI_DEVICE_ID_INTEL_IOAT_SNB9: 174 return true; 175 default: 176 return false; 177 } 178 } 179 180 static bool is_ivb_ioat(struct pci_dev *pdev) 181 { 182 switch (pdev->device) { 183 case PCI_DEVICE_ID_INTEL_IOAT_IVB0: 184 case PCI_DEVICE_ID_INTEL_IOAT_IVB1: 185 case PCI_DEVICE_ID_INTEL_IOAT_IVB2: 186 case PCI_DEVICE_ID_INTEL_IOAT_IVB3: 187 case PCI_DEVICE_ID_INTEL_IOAT_IVB4: 188 case PCI_DEVICE_ID_INTEL_IOAT_IVB5: 189 case PCI_DEVICE_ID_INTEL_IOAT_IVB6: 190 case PCI_DEVICE_ID_INTEL_IOAT_IVB7: 191 case PCI_DEVICE_ID_INTEL_IOAT_IVB8: 192 case PCI_DEVICE_ID_INTEL_IOAT_IVB9: 193 return true; 194 default: 195 return false; 196 } 197 198 } 199 200 static bool is_hsw_ioat(struct pci_dev *pdev) 201 { 202 switch (pdev->device) { 203 case PCI_DEVICE_ID_INTEL_IOAT_HSW0: 204 case PCI_DEVICE_ID_INTEL_IOAT_HSW1: 205 case PCI_DEVICE_ID_INTEL_IOAT_HSW2: 206 case PCI_DEVICE_ID_INTEL_IOAT_HSW3: 207 case PCI_DEVICE_ID_INTEL_IOAT_HSW4: 208 case PCI_DEVICE_ID_INTEL_IOAT_HSW5: 209 case PCI_DEVICE_ID_INTEL_IOAT_HSW6: 210 case PCI_DEVICE_ID_INTEL_IOAT_HSW7: 211 case PCI_DEVICE_ID_INTEL_IOAT_HSW8: 212 case PCI_DEVICE_ID_INTEL_IOAT_HSW9: 213 return true; 214 default: 215 return false; 216 } 217 218 } 219 220 static bool is_bdx_ioat(struct pci_dev *pdev) 221 { 222 switch (pdev->device) { 223 case PCI_DEVICE_ID_INTEL_IOAT_BDX0: 224 case PCI_DEVICE_ID_INTEL_IOAT_BDX1: 225 case PCI_DEVICE_ID_INTEL_IOAT_BDX2: 226 case PCI_DEVICE_ID_INTEL_IOAT_BDX3: 227 case PCI_DEVICE_ID_INTEL_IOAT_BDX4: 228 case PCI_DEVICE_ID_INTEL_IOAT_BDX5: 229 case PCI_DEVICE_ID_INTEL_IOAT_BDX6: 230 case PCI_DEVICE_ID_INTEL_IOAT_BDX7: 231 case PCI_DEVICE_ID_INTEL_IOAT_BDX8: 232 case PCI_DEVICE_ID_INTEL_IOAT_BDX9: 233 return true; 234 default: 235 return false; 236 } 237 } 238 239 static inline bool is_skx_ioat(struct pci_dev *pdev) 240 { 241 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false; 242 } 243 244 static bool is_xeon_cb32(struct pci_dev *pdev) 245 { 246 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 247 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev); 248 } 249 250 bool is_bwd_ioat(struct pci_dev *pdev) 251 { 252 switch (pdev->device) { 253 case PCI_DEVICE_ID_INTEL_IOAT_BWD0: 254 case PCI_DEVICE_ID_INTEL_IOAT_BWD1: 255 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 256 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 257 /* even though not Atom, BDX-DE has same DMA silicon */ 258 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 259 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 260 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 261 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 262 return true; 263 default: 264 return false; 265 } 266 } 267 268 static bool is_bwd_noraid(struct pci_dev *pdev) 269 { 270 switch (pdev->device) { 271 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 272 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 273 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 274 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 275 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 276 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 277 return true; 278 default: 279 return false; 280 } 281 282 } 283 284 /* 285 * Perform a IOAT transaction to verify the HW works. 286 */ 287 #define IOAT_TEST_SIZE 2000 288 289 static void ioat_dma_test_callback(void *dma_async_param) 290 { 291 struct completion *cmp = dma_async_param; 292 293 complete(cmp); 294 } 295 296 /** 297 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. 298 * @ioat_dma: dma device to be tested 299 */ 300 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) 301 { 302 int i; 303 u8 *src; 304 u8 *dest; 305 struct dma_device *dma = &ioat_dma->dma_dev; 306 struct device *dev = &ioat_dma->pdev->dev; 307 struct dma_chan *dma_chan; 308 struct dma_async_tx_descriptor *tx; 309 dma_addr_t dma_dest, dma_src; 310 dma_cookie_t cookie; 311 int err = 0; 312 struct completion cmp; 313 unsigned long tmo; 314 unsigned long flags; 315 316 src = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL); 317 if (!src) 318 return -ENOMEM; 319 dest = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL); 320 if (!dest) { 321 kfree(src); 322 return -ENOMEM; 323 } 324 325 /* Fill in src buffer */ 326 for (i = 0; i < IOAT_TEST_SIZE; i++) 327 src[i] = (u8)i; 328 329 /* Start copy, using first DMA channel */ 330 dma_chan = container_of(dma->channels.next, struct dma_chan, 331 device_node); 332 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 333 dev_err(dev, "selftest cannot allocate chan resource\n"); 334 err = -ENODEV; 335 goto out; 336 } 337 338 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 339 if (dma_mapping_error(dev, dma_src)) { 340 dev_err(dev, "mapping src buffer failed\n"); 341 err = -ENOMEM; 342 goto free_resources; 343 } 344 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 345 if (dma_mapping_error(dev, dma_dest)) { 346 dev_err(dev, "mapping dest buffer failed\n"); 347 err = -ENOMEM; 348 goto unmap_src; 349 } 350 flags = DMA_PREP_INTERRUPT; 351 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, 352 dma_src, IOAT_TEST_SIZE, 353 flags); 354 if (!tx) { 355 dev_err(dev, "Self-test prep failed, disabling\n"); 356 err = -ENODEV; 357 goto unmap_dma; 358 } 359 360 async_tx_ack(tx); 361 init_completion(&cmp); 362 tx->callback = ioat_dma_test_callback; 363 tx->callback_param = &cmp; 364 cookie = tx->tx_submit(tx); 365 if (cookie < 0) { 366 dev_err(dev, "Self-test setup failed, disabling\n"); 367 err = -ENODEV; 368 goto unmap_dma; 369 } 370 dma->device_issue_pending(dma_chan); 371 372 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 373 374 if (tmo == 0 || 375 dma->device_tx_status(dma_chan, cookie, NULL) 376 != DMA_COMPLETE) { 377 dev_err(dev, "Self-test copy timed out, disabling\n"); 378 err = -ENODEV; 379 goto unmap_dma; 380 } 381 if (memcmp(src, dest, IOAT_TEST_SIZE)) { 382 dev_err(dev, "Self-test copy failed compare, disabling\n"); 383 err = -ENODEV; 384 goto unmap_dma; 385 } 386 387 unmap_dma: 388 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 389 unmap_src: 390 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 391 free_resources: 392 dma->device_free_chan_resources(dma_chan); 393 out: 394 kfree(src); 395 kfree(dest); 396 return err; 397 } 398 399 /** 400 * ioat_dma_setup_interrupts - setup interrupt handler 401 * @ioat_dma: ioat dma device 402 */ 403 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) 404 { 405 struct ioatdma_chan *ioat_chan; 406 struct pci_dev *pdev = ioat_dma->pdev; 407 struct device *dev = &pdev->dev; 408 struct msix_entry *msix; 409 int i, j, msixcnt; 410 int err = -EINVAL; 411 u8 intrctrl = 0; 412 413 if (!strcmp(ioat_interrupt_style, "msix")) 414 goto msix; 415 if (!strcmp(ioat_interrupt_style, "msi")) 416 goto msi; 417 if (!strcmp(ioat_interrupt_style, "intx")) 418 goto intx; 419 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); 420 goto err_no_irq; 421 422 msix: 423 /* The number of MSI-X vectors should equal the number of channels */ 424 msixcnt = ioat_dma->chancnt; 425 for (i = 0; i < msixcnt; i++) 426 ioat_dma->msix_entries[i].entry = i; 427 428 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); 429 if (err) 430 goto msi; 431 432 for (i = 0; i < msixcnt; i++) { 433 msix = &ioat_dma->msix_entries[i]; 434 ioat_chan = ioat_chan_by_index(ioat_dma, i); 435 err = devm_request_irq(dev, msix->vector, 436 ioat_dma_do_interrupt_msix, 0, 437 "ioat-msix", ioat_chan); 438 if (err) { 439 for (j = 0; j < i; j++) { 440 msix = &ioat_dma->msix_entries[j]; 441 ioat_chan = ioat_chan_by_index(ioat_dma, j); 442 devm_free_irq(dev, msix->vector, ioat_chan); 443 } 444 goto msi; 445 } 446 } 447 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; 448 ioat_dma->irq_mode = IOAT_MSIX; 449 goto done; 450 451 msi: 452 err = pci_enable_msi(pdev); 453 if (err) 454 goto intx; 455 456 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, 457 "ioat-msi", ioat_dma); 458 if (err) { 459 pci_disable_msi(pdev); 460 goto intx; 461 } 462 ioat_dma->irq_mode = IOAT_MSI; 463 goto done; 464 465 intx: 466 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 467 IRQF_SHARED, "ioat-intx", ioat_dma); 468 if (err) 469 goto err_no_irq; 470 471 ioat_dma->irq_mode = IOAT_INTX; 472 done: 473 if (is_bwd_ioat(pdev)) 474 ioat_intr_quirk(ioat_dma); 475 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; 476 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 477 return 0; 478 479 err_no_irq: 480 /* Disable all interrupt generation */ 481 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 482 ioat_dma->irq_mode = IOAT_NOIRQ; 483 dev_err(dev, "no usable interrupts\n"); 484 return err; 485 } 486 487 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) 488 { 489 /* Disable all interrupt generation */ 490 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 491 } 492 493 static int ioat_probe(struct ioatdma_device *ioat_dma) 494 { 495 int err = -ENODEV; 496 struct dma_device *dma = &ioat_dma->dma_dev; 497 struct pci_dev *pdev = ioat_dma->pdev; 498 struct device *dev = &pdev->dev; 499 500 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev, 501 sizeof(u64), 502 SMP_CACHE_BYTES, 503 SMP_CACHE_BYTES); 504 505 if (!ioat_dma->completion_pool) { 506 err = -ENOMEM; 507 goto err_out; 508 } 509 510 ioat_enumerate_channels(ioat_dma); 511 512 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 513 dma->dev = &pdev->dev; 514 515 if (!ioat_dma->chancnt) { 516 dev_err(dev, "channel enumeration error\n"); 517 goto err_setup_interrupts; 518 } 519 520 err = ioat_dma_setup_interrupts(ioat_dma); 521 if (err) 522 goto err_setup_interrupts; 523 524 err = ioat3_dma_self_test(ioat_dma); 525 if (err) 526 goto err_self_test; 527 528 return 0; 529 530 err_self_test: 531 ioat_disable_interrupts(ioat_dma); 532 err_setup_interrupts: 533 dma_pool_destroy(ioat_dma->completion_pool); 534 err_out: 535 return err; 536 } 537 538 static int ioat_register(struct ioatdma_device *ioat_dma) 539 { 540 int err = dma_async_device_register(&ioat_dma->dma_dev); 541 542 if (err) { 543 ioat_disable_interrupts(ioat_dma); 544 dma_pool_destroy(ioat_dma->completion_pool); 545 } 546 547 return err; 548 } 549 550 static void ioat_dma_remove(struct ioatdma_device *ioat_dma) 551 { 552 struct dma_device *dma = &ioat_dma->dma_dev; 553 554 ioat_disable_interrupts(ioat_dma); 555 556 ioat_kobject_del(ioat_dma); 557 558 dma_async_device_unregister(dma); 559 } 560 561 /** 562 * ioat_enumerate_channels - find and initialize the device's channels 563 * @ioat_dma: the ioat dma device to be enumerated 564 */ 565 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma) 566 { 567 struct ioatdma_chan *ioat_chan; 568 struct device *dev = &ioat_dma->pdev->dev; 569 struct dma_device *dma = &ioat_dma->dma_dev; 570 u8 xfercap_log; 571 int chancnt; 572 int i; 573 574 INIT_LIST_HEAD(&dma->channels); 575 chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); 576 chancnt &= 0x1f; /* bits [4:0] valid */ 577 if (chancnt > ARRAY_SIZE(ioat_dma->idx)) { 578 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", 579 chancnt, ARRAY_SIZE(ioat_dma->idx)); 580 chancnt = ARRAY_SIZE(ioat_dma->idx); 581 } 582 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); 583 xfercap_log &= 0x1f; /* bits [4:0] valid */ 584 if (xfercap_log == 0) 585 return; 586 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); 587 588 for (i = 0; i < chancnt; i++) { 589 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL); 590 if (!ioat_chan) 591 break; 592 593 ioat_init_channel(ioat_dma, ioat_chan, i); 594 ioat_chan->xfercap_log = xfercap_log; 595 spin_lock_init(&ioat_chan->prep_lock); 596 if (ioat_reset_hw(ioat_chan)) { 597 i = 0; 598 break; 599 } 600 } 601 ioat_dma->chancnt = i; 602 } 603 604 /** 605 * ioat_free_chan_resources - release all the descriptors 606 * @c: the channel to be cleaned 607 */ 608 static void ioat_free_chan_resources(struct dma_chan *c) 609 { 610 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 611 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; 612 struct ioat_ring_ent *desc; 613 const int total_descs = 1 << ioat_chan->alloc_order; 614 int descs; 615 int i; 616 617 /* Before freeing channel resources first check 618 * if they have been previously allocated for this channel. 619 */ 620 if (!ioat_chan->ring) 621 return; 622 623 ioat_stop(ioat_chan); 624 625 if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) { 626 ioat_reset_hw(ioat_chan); 627 628 /* Put LTR to idle */ 629 if (ioat_dma->version >= IOAT_VER_3_4) 630 writeb(IOAT_CHAN_LTR_SWSEL_IDLE, 631 ioat_chan->reg_base + 632 IOAT_CHAN_LTR_SWSEL_OFFSET); 633 } 634 635 spin_lock_bh(&ioat_chan->cleanup_lock); 636 spin_lock_bh(&ioat_chan->prep_lock); 637 descs = ioat_ring_space(ioat_chan); 638 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); 639 for (i = 0; i < descs; i++) { 640 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); 641 ioat_free_ring_ent(desc, c); 642 } 643 644 if (descs < total_descs) 645 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", 646 total_descs - descs); 647 648 for (i = 0; i < total_descs - descs; i++) { 649 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); 650 dump_desc_dbg(ioat_chan, desc); 651 ioat_free_ring_ent(desc, c); 652 } 653 654 for (i = 0; i < ioat_chan->desc_chunks; i++) { 655 dma_free_coherent(to_dev(ioat_chan), IOAT_CHUNK_SIZE, 656 ioat_chan->descs[i].virt, 657 ioat_chan->descs[i].hw); 658 ioat_chan->descs[i].virt = NULL; 659 ioat_chan->descs[i].hw = 0; 660 } 661 ioat_chan->desc_chunks = 0; 662 663 kfree(ioat_chan->ring); 664 ioat_chan->ring = NULL; 665 ioat_chan->alloc_order = 0; 666 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion, 667 ioat_chan->completion_dma); 668 spin_unlock_bh(&ioat_chan->prep_lock); 669 spin_unlock_bh(&ioat_chan->cleanup_lock); 670 671 ioat_chan->last_completion = 0; 672 ioat_chan->completion_dma = 0; 673 ioat_chan->dmacount = 0; 674 } 675 676 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring 677 * @chan: channel to be initialized 678 */ 679 static int ioat_alloc_chan_resources(struct dma_chan *c) 680 { 681 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 682 struct ioat_ring_ent **ring; 683 u64 status; 684 int order; 685 int i = 0; 686 u32 chanerr; 687 688 /* have we already been set up? */ 689 if (ioat_chan->ring) 690 return 1 << ioat_chan->alloc_order; 691 692 /* Setup register to interrupt and write completion status on error */ 693 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); 694 695 /* allocate a completion writeback area */ 696 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 697 ioat_chan->completion = 698 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool, 699 GFP_NOWAIT, &ioat_chan->completion_dma); 700 if (!ioat_chan->completion) 701 return -ENOMEM; 702 703 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, 704 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); 705 writel(((u64)ioat_chan->completion_dma) >> 32, 706 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 707 708 order = IOAT_MAX_ORDER; 709 ring = ioat_alloc_ring(c, order, GFP_NOWAIT); 710 if (!ring) 711 return -ENOMEM; 712 713 spin_lock_bh(&ioat_chan->cleanup_lock); 714 spin_lock_bh(&ioat_chan->prep_lock); 715 ioat_chan->ring = ring; 716 ioat_chan->head = 0; 717 ioat_chan->issued = 0; 718 ioat_chan->tail = 0; 719 ioat_chan->alloc_order = order; 720 set_bit(IOAT_RUN, &ioat_chan->state); 721 spin_unlock_bh(&ioat_chan->prep_lock); 722 spin_unlock_bh(&ioat_chan->cleanup_lock); 723 724 /* Setting up LTR values for 3.4 or later */ 725 if (ioat_chan->ioat_dma->version >= IOAT_VER_3_4) { 726 u32 lat_val; 727 728 lat_val = IOAT_CHAN_LTR_ACTIVE_SNVAL | 729 IOAT_CHAN_LTR_ACTIVE_SNLATSCALE | 730 IOAT_CHAN_LTR_ACTIVE_SNREQMNT; 731 writel(lat_val, ioat_chan->reg_base + 732 IOAT_CHAN_LTR_ACTIVE_OFFSET); 733 734 lat_val = IOAT_CHAN_LTR_IDLE_SNVAL | 735 IOAT_CHAN_LTR_IDLE_SNLATSCALE | 736 IOAT_CHAN_LTR_IDLE_SNREQMNT; 737 writel(lat_val, ioat_chan->reg_base + 738 IOAT_CHAN_LTR_IDLE_OFFSET); 739 740 /* Select to active */ 741 writeb(IOAT_CHAN_LTR_SWSEL_ACTIVE, 742 ioat_chan->reg_base + 743 IOAT_CHAN_LTR_SWSEL_OFFSET); 744 } 745 746 ioat_start_null_desc(ioat_chan); 747 748 /* check that we got off the ground */ 749 do { 750 udelay(1); 751 status = ioat_chansts(ioat_chan); 752 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); 753 754 if (is_ioat_active(status) || is_ioat_idle(status)) 755 return 1 << ioat_chan->alloc_order; 756 757 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 758 759 dev_WARN(to_dev(ioat_chan), 760 "failed to start channel chanerr: %#x\n", chanerr); 761 ioat_free_chan_resources(c); 762 return -EFAULT; 763 } 764 765 /* common channel initialization */ 766 static void 767 ioat_init_channel(struct ioatdma_device *ioat_dma, 768 struct ioatdma_chan *ioat_chan, int idx) 769 { 770 struct dma_device *dma = &ioat_dma->dma_dev; 771 772 ioat_chan->ioat_dma = ioat_dma; 773 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); 774 spin_lock_init(&ioat_chan->cleanup_lock); 775 ioat_chan->dma_chan.device = dma; 776 dma_cookie_init(&ioat_chan->dma_chan); 777 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); 778 ioat_dma->idx[idx] = ioat_chan; 779 timer_setup(&ioat_chan->timer, ioat_timer_event, 0); 780 tasklet_setup(&ioat_chan->cleanup_task, ioat_cleanup_event); 781 } 782 783 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ 784 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) 785 { 786 int i, src_idx; 787 struct page *dest; 788 struct page *xor_srcs[IOAT_NUM_SRC_TEST]; 789 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; 790 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; 791 dma_addr_t dest_dma; 792 struct dma_async_tx_descriptor *tx; 793 struct dma_chan *dma_chan; 794 dma_cookie_t cookie; 795 u8 cmp_byte = 0; 796 u32 cmp_word; 797 u32 xor_val_result; 798 int err = 0; 799 struct completion cmp; 800 unsigned long tmo; 801 struct device *dev = &ioat_dma->pdev->dev; 802 struct dma_device *dma = &ioat_dma->dma_dev; 803 u8 op = 0; 804 805 dev_dbg(dev, "%s\n", __func__); 806 807 if (!dma_has_cap(DMA_XOR, dma->cap_mask)) 808 return 0; 809 810 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 811 xor_srcs[src_idx] = alloc_page(GFP_KERNEL); 812 if (!xor_srcs[src_idx]) { 813 while (src_idx--) 814 __free_page(xor_srcs[src_idx]); 815 return -ENOMEM; 816 } 817 } 818 819 dest = alloc_page(GFP_KERNEL); 820 if (!dest) { 821 while (src_idx--) 822 __free_page(xor_srcs[src_idx]); 823 return -ENOMEM; 824 } 825 826 /* Fill in src buffers */ 827 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 828 u8 *ptr = page_address(xor_srcs[src_idx]); 829 830 for (i = 0; i < PAGE_SIZE; i++) 831 ptr[i] = (1 << src_idx); 832 } 833 834 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) 835 cmp_byte ^= (u8) (1 << src_idx); 836 837 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | 838 (cmp_byte << 8) | cmp_byte; 839 840 memset(page_address(dest), 0, PAGE_SIZE); 841 842 dma_chan = container_of(dma->channels.next, struct dma_chan, 843 device_node); 844 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 845 err = -ENODEV; 846 goto out; 847 } 848 849 /* test xor */ 850 op = IOAT_OP_XOR; 851 852 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); 853 if (dma_mapping_error(dev, dest_dma)) { 854 err = -ENOMEM; 855 goto free_resources; 856 } 857 858 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { 859 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, 860 DMA_TO_DEVICE); 861 if (dma_mapping_error(dev, dma_srcs[i])) { 862 err = -ENOMEM; 863 goto dma_unmap; 864 } 865 } 866 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, 867 IOAT_NUM_SRC_TEST, PAGE_SIZE, 868 DMA_PREP_INTERRUPT); 869 870 if (!tx) { 871 dev_err(dev, "Self-test xor prep failed\n"); 872 err = -ENODEV; 873 goto dma_unmap; 874 } 875 876 async_tx_ack(tx); 877 init_completion(&cmp); 878 tx->callback = ioat_dma_test_callback; 879 tx->callback_param = &cmp; 880 cookie = tx->tx_submit(tx); 881 if (cookie < 0) { 882 dev_err(dev, "Self-test xor setup failed\n"); 883 err = -ENODEV; 884 goto dma_unmap; 885 } 886 dma->device_issue_pending(dma_chan); 887 888 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 889 890 if (tmo == 0 || 891 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 892 dev_err(dev, "Self-test xor timed out\n"); 893 err = -ENODEV; 894 goto dma_unmap; 895 } 896 897 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 898 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 899 900 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 901 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { 902 u32 *ptr = page_address(dest); 903 904 if (ptr[i] != cmp_word) { 905 dev_err(dev, "Self-test xor failed compare\n"); 906 err = -ENODEV; 907 goto free_resources; 908 } 909 } 910 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 911 912 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 913 914 /* skip validate if the capability is not present */ 915 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) 916 goto free_resources; 917 918 op = IOAT_OP_XOR_VAL; 919 920 /* validate the sources with the destintation page */ 921 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 922 xor_val_srcs[i] = xor_srcs[i]; 923 xor_val_srcs[i] = dest; 924 925 xor_val_result = 1; 926 927 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 928 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 929 DMA_TO_DEVICE); 930 if (dma_mapping_error(dev, dma_srcs[i])) { 931 err = -ENOMEM; 932 goto dma_unmap; 933 } 934 } 935 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 936 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 937 &xor_val_result, DMA_PREP_INTERRUPT); 938 if (!tx) { 939 dev_err(dev, "Self-test zero prep failed\n"); 940 err = -ENODEV; 941 goto dma_unmap; 942 } 943 944 async_tx_ack(tx); 945 init_completion(&cmp); 946 tx->callback = ioat_dma_test_callback; 947 tx->callback_param = &cmp; 948 cookie = tx->tx_submit(tx); 949 if (cookie < 0) { 950 dev_err(dev, "Self-test zero setup failed\n"); 951 err = -ENODEV; 952 goto dma_unmap; 953 } 954 dma->device_issue_pending(dma_chan); 955 956 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 957 958 if (tmo == 0 || 959 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 960 dev_err(dev, "Self-test validate timed out\n"); 961 err = -ENODEV; 962 goto dma_unmap; 963 } 964 965 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 966 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 967 968 if (xor_val_result != 0) { 969 dev_err(dev, "Self-test validate failed compare\n"); 970 err = -ENODEV; 971 goto free_resources; 972 } 973 974 memset(page_address(dest), 0, PAGE_SIZE); 975 976 /* test for non-zero parity sum */ 977 op = IOAT_OP_XOR_VAL; 978 979 xor_val_result = 0; 980 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 981 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 982 DMA_TO_DEVICE); 983 if (dma_mapping_error(dev, dma_srcs[i])) { 984 err = -ENOMEM; 985 goto dma_unmap; 986 } 987 } 988 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 989 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 990 &xor_val_result, DMA_PREP_INTERRUPT); 991 if (!tx) { 992 dev_err(dev, "Self-test 2nd zero prep failed\n"); 993 err = -ENODEV; 994 goto dma_unmap; 995 } 996 997 async_tx_ack(tx); 998 init_completion(&cmp); 999 tx->callback = ioat_dma_test_callback; 1000 tx->callback_param = &cmp; 1001 cookie = tx->tx_submit(tx); 1002 if (cookie < 0) { 1003 dev_err(dev, "Self-test 2nd zero setup failed\n"); 1004 err = -ENODEV; 1005 goto dma_unmap; 1006 } 1007 dma->device_issue_pending(dma_chan); 1008 1009 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 1010 1011 if (tmo == 0 || 1012 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 1013 dev_err(dev, "Self-test 2nd validate timed out\n"); 1014 err = -ENODEV; 1015 goto dma_unmap; 1016 } 1017 1018 if (xor_val_result != SUM_CHECK_P_RESULT) { 1019 dev_err(dev, "Self-test validate failed compare\n"); 1020 err = -ENODEV; 1021 goto dma_unmap; 1022 } 1023 1024 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 1025 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 1026 1027 goto free_resources; 1028 dma_unmap: 1029 if (op == IOAT_OP_XOR) { 1030 while (--i >= 0) 1031 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1032 DMA_TO_DEVICE); 1033 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 1034 } else if (op == IOAT_OP_XOR_VAL) { 1035 while (--i >= 0) 1036 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1037 DMA_TO_DEVICE); 1038 } 1039 free_resources: 1040 dma->device_free_chan_resources(dma_chan); 1041 out: 1042 src_idx = IOAT_NUM_SRC_TEST; 1043 while (src_idx--) 1044 __free_page(xor_srcs[src_idx]); 1045 __free_page(dest); 1046 return err; 1047 } 1048 1049 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) 1050 { 1051 int rc; 1052 1053 rc = ioat_dma_self_test(ioat_dma); 1054 if (rc) 1055 return rc; 1056 1057 rc = ioat_xor_val_self_test(ioat_dma); 1058 1059 return rc; 1060 } 1061 1062 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma) 1063 { 1064 struct dma_device *dma; 1065 struct dma_chan *c; 1066 struct ioatdma_chan *ioat_chan; 1067 u32 errmask; 1068 1069 dma = &ioat_dma->dma_dev; 1070 1071 /* 1072 * if we have descriptor write back error status, we mask the 1073 * error interrupts 1074 */ 1075 if (ioat_dma->cap & IOAT_CAP_DWBES) { 1076 list_for_each_entry(c, &dma->channels, device_node) { 1077 ioat_chan = to_ioat_chan(c); 1078 errmask = readl(ioat_chan->reg_base + 1079 IOAT_CHANERR_MASK_OFFSET); 1080 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | 1081 IOAT_CHANERR_XOR_Q_ERR; 1082 writel(errmask, ioat_chan->reg_base + 1083 IOAT_CHANERR_MASK_OFFSET); 1084 } 1085 } 1086 } 1087 1088 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 1089 { 1090 struct pci_dev *pdev = ioat_dma->pdev; 1091 int dca_en = system_has_dca_enabled(pdev); 1092 struct dma_device *dma; 1093 struct dma_chan *c; 1094 struct ioatdma_chan *ioat_chan; 1095 int err; 1096 u16 val16; 1097 1098 dma = &ioat_dma->dma_dev; 1099 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; 1100 dma->device_issue_pending = ioat_issue_pending; 1101 dma->device_alloc_chan_resources = ioat_alloc_chan_resources; 1102 dma->device_free_chan_resources = ioat_free_chan_resources; 1103 1104 dma_cap_set(DMA_INTERRUPT, dma->cap_mask); 1105 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; 1106 1107 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); 1108 1109 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) 1110 ioat_dma->cap &= 1111 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); 1112 1113 /* dca is incompatible with raid operations */ 1114 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) 1115 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); 1116 1117 if (ioat_dma->cap & IOAT_CAP_XOR) { 1118 dma->max_xor = 8; 1119 1120 dma_cap_set(DMA_XOR, dma->cap_mask); 1121 dma->device_prep_dma_xor = ioat_prep_xor; 1122 1123 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1124 dma->device_prep_dma_xor_val = ioat_prep_xor_val; 1125 } 1126 1127 if (ioat_dma->cap & IOAT_CAP_PQ) { 1128 1129 dma->device_prep_dma_pq = ioat_prep_pq; 1130 dma->device_prep_dma_pq_val = ioat_prep_pq_val; 1131 dma_cap_set(DMA_PQ, dma->cap_mask); 1132 dma_cap_set(DMA_PQ_VAL, dma->cap_mask); 1133 1134 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1135 dma_set_maxpq(dma, 16, 0); 1136 else 1137 dma_set_maxpq(dma, 8, 0); 1138 1139 if (!(ioat_dma->cap & IOAT_CAP_XOR)) { 1140 dma->device_prep_dma_xor = ioat_prep_pqxor; 1141 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; 1142 dma_cap_set(DMA_XOR, dma->cap_mask); 1143 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1144 1145 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1146 dma->max_xor = 16; 1147 else 1148 dma->max_xor = 8; 1149 } 1150 } 1151 1152 dma->device_tx_status = ioat_tx_status; 1153 1154 /* starting with CB3.3 super extended descriptors are supported */ 1155 if (ioat_dma->cap & IOAT_CAP_RAID16SS) { 1156 char pool_name[14]; 1157 int i; 1158 1159 for (i = 0; i < MAX_SED_POOLS; i++) { 1160 snprintf(pool_name, 14, "ioat_hw%d_sed", i); 1161 1162 /* allocate SED DMA pool */ 1163 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, 1164 &pdev->dev, 1165 SED_SIZE * (i + 1), 64, 0); 1166 if (!ioat_dma->sed_hw_pool[i]) 1167 return -ENOMEM; 1168 1169 } 1170 } 1171 1172 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) 1173 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1174 1175 err = ioat_probe(ioat_dma); 1176 if (err) 1177 return err; 1178 1179 list_for_each_entry(c, &dma->channels, device_node) { 1180 ioat_chan = to_ioat_chan(c); 1181 writel(IOAT_DMA_DCA_ANY_CPU, 1182 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 1183 } 1184 1185 err = ioat_register(ioat_dma); 1186 if (err) 1187 return err; 1188 1189 ioat_kobject_add(ioat_dma, &ioat_ktype); 1190 1191 if (dca) 1192 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); 1193 1194 /* disable relaxed ordering */ 1195 err = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &val16); 1196 if (err) 1197 return pcibios_err_to_errno(err); 1198 1199 /* clear relaxed ordering enable */ 1200 val16 &= ~PCI_EXP_DEVCTL_RELAX_EN; 1201 err = pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, val16); 1202 if (err) 1203 return pcibios_err_to_errno(err); 1204 1205 if (ioat_dma->cap & IOAT_CAP_DPS) 1206 writeb(ioat_pending_level + 1, 1207 ioat_dma->reg_base + IOAT_PREFETCH_LIMIT_OFFSET); 1208 1209 return 0; 1210 } 1211 1212 static void ioat_shutdown(struct pci_dev *pdev) 1213 { 1214 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1215 struct ioatdma_chan *ioat_chan; 1216 int i; 1217 1218 if (!ioat_dma) 1219 return; 1220 1221 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1222 ioat_chan = ioat_dma->idx[i]; 1223 if (!ioat_chan) 1224 continue; 1225 1226 spin_lock_bh(&ioat_chan->prep_lock); 1227 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1228 spin_unlock_bh(&ioat_chan->prep_lock); 1229 /* 1230 * Synchronization rule for del_timer_sync(): 1231 * - The caller must not hold locks which would prevent 1232 * completion of the timer's handler. 1233 * So prep_lock cannot be held before calling it. 1234 */ 1235 del_timer_sync(&ioat_chan->timer); 1236 1237 /* this should quiesce then reset */ 1238 ioat_reset_hw(ioat_chan); 1239 } 1240 1241 ioat_disable_interrupts(ioat_dma); 1242 } 1243 1244 static void ioat_resume(struct ioatdma_device *ioat_dma) 1245 { 1246 struct ioatdma_chan *ioat_chan; 1247 u32 chanerr; 1248 int i; 1249 1250 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1251 ioat_chan = ioat_dma->idx[i]; 1252 if (!ioat_chan) 1253 continue; 1254 1255 spin_lock_bh(&ioat_chan->prep_lock); 1256 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1257 spin_unlock_bh(&ioat_chan->prep_lock); 1258 1259 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1260 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1261 1262 /* no need to reset as shutdown already did that */ 1263 } 1264 } 1265 1266 #define DRV_NAME "ioatdma" 1267 1268 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev, 1269 pci_channel_state_t error) 1270 { 1271 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error); 1272 1273 /* quiesce and block I/O */ 1274 ioat_shutdown(pdev); 1275 1276 return PCI_ERS_RESULT_NEED_RESET; 1277 } 1278 1279 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev) 1280 { 1281 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 1282 1283 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME); 1284 1285 if (pci_enable_device_mem(pdev) < 0) { 1286 dev_err(&pdev->dev, 1287 "Failed to enable PCIe device after reset.\n"); 1288 result = PCI_ERS_RESULT_DISCONNECT; 1289 } else { 1290 pci_set_master(pdev); 1291 pci_restore_state(pdev); 1292 pci_save_state(pdev); 1293 pci_wake_from_d3(pdev, false); 1294 } 1295 1296 return result; 1297 } 1298 1299 static void ioat_pcie_error_resume(struct pci_dev *pdev) 1300 { 1301 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1302 1303 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME); 1304 1305 /* initialize and bring everything back */ 1306 ioat_resume(ioat_dma); 1307 } 1308 1309 static const struct pci_error_handlers ioat_err_handler = { 1310 .error_detected = ioat_pcie_error_detected, 1311 .slot_reset = ioat_pcie_error_slot_reset, 1312 .resume = ioat_pcie_error_resume, 1313 }; 1314 1315 static struct pci_driver ioat_pci_driver = { 1316 .name = DRV_NAME, 1317 .id_table = ioat_pci_tbl, 1318 .probe = ioat_pci_probe, 1319 .remove = ioat_remove, 1320 .shutdown = ioat_shutdown, 1321 .err_handler = &ioat_err_handler, 1322 }; 1323 1324 static void release_ioatdma(struct dma_device *device) 1325 { 1326 struct ioatdma_device *d = to_ioatdma_device(device); 1327 int i; 1328 1329 for (i = 0; i < IOAT_MAX_CHANS; i++) 1330 kfree(d->idx[i]); 1331 1332 dma_pool_destroy(d->completion_pool); 1333 kfree(d); 1334 } 1335 1336 static struct ioatdma_device * 1337 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) 1338 { 1339 struct ioatdma_device *d = kzalloc(sizeof(*d), GFP_KERNEL); 1340 1341 if (!d) 1342 return NULL; 1343 d->pdev = pdev; 1344 d->reg_base = iobase; 1345 d->dma_dev.device_release = release_ioatdma; 1346 return d; 1347 } 1348 1349 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1350 { 1351 void __iomem * const *iomap; 1352 struct device *dev = &pdev->dev; 1353 struct ioatdma_device *device; 1354 int err; 1355 1356 err = pcim_enable_device(pdev); 1357 if (err) 1358 return err; 1359 1360 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); 1361 if (err) 1362 return err; 1363 iomap = pcim_iomap_table(pdev); 1364 if (!iomap) 1365 return -ENOMEM; 1366 1367 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1368 if (err) 1369 return err; 1370 1371 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); 1372 if (!device) 1373 return -ENOMEM; 1374 pci_set_master(pdev); 1375 pci_set_drvdata(pdev, device); 1376 1377 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1378 if (device->version >= IOAT_VER_3_4) 1379 ioat_dca_enabled = 0; 1380 if (device->version >= IOAT_VER_3_0) { 1381 if (is_skx_ioat(pdev)) 1382 device->version = IOAT_VER_3_2; 1383 err = ioat3_dma_probe(device, ioat_dca_enabled); 1384 } else 1385 return -ENODEV; 1386 1387 if (err) { 1388 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); 1389 return -ENODEV; 1390 } 1391 1392 return 0; 1393 } 1394 1395 static void ioat_remove(struct pci_dev *pdev) 1396 { 1397 struct ioatdma_device *device = pci_get_drvdata(pdev); 1398 1399 if (!device) 1400 return; 1401 1402 ioat_shutdown(pdev); 1403 1404 dev_err(&pdev->dev, "Removing dma and dca services\n"); 1405 if (device->dca) { 1406 unregister_dca_provider(device->dca, &pdev->dev); 1407 free_dca_provider(device->dca); 1408 device->dca = NULL; 1409 } 1410 1411 ioat_dma_remove(device); 1412 } 1413 1414 static int __init ioat_init_module(void) 1415 { 1416 int err = -ENOMEM; 1417 1418 pr_info("%s: Intel(R) QuickData Technology Driver %s\n", 1419 DRV_NAME, IOAT_DMA_VERSION); 1420 1421 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), 1422 0, SLAB_HWCACHE_ALIGN, NULL); 1423 if (!ioat_cache) 1424 return -ENOMEM; 1425 1426 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); 1427 if (!ioat_sed_cache) 1428 goto err_ioat_cache; 1429 1430 err = pci_register_driver(&ioat_pci_driver); 1431 if (err) 1432 goto err_ioat3_cache; 1433 1434 return 0; 1435 1436 err_ioat3_cache: 1437 kmem_cache_destroy(ioat_sed_cache); 1438 1439 err_ioat_cache: 1440 kmem_cache_destroy(ioat_cache); 1441 1442 return err; 1443 } 1444 module_init(ioat_init_module); 1445 1446 static void __exit ioat_exit_module(void) 1447 { 1448 pci_unregister_driver(&ioat_pci_driver); 1449 kmem_cache_destroy(ioat_cache); 1450 } 1451 module_exit(ioat_exit_module); 1452