1 /* 2 * Intel I/OAT DMA Linux driver 3 * Copyright(c) 2004 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 */ 18 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/slab.h> 22 #include <linux/pci.h> 23 #include <linux/interrupt.h> 24 #include <linux/dmaengine.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/workqueue.h> 28 #include <linux/prefetch.h> 29 #include <linux/dca.h> 30 #include "dma.h" 31 #include "registers.h" 32 #include "hw.h" 33 34 #include "../dmaengine.h" 35 36 MODULE_VERSION(IOAT_DMA_VERSION); 37 MODULE_LICENSE("Dual BSD/GPL"); 38 MODULE_AUTHOR("Intel Corporation"); 39 40 static struct pci_device_id ioat_pci_tbl[] = { 41 /* I/OAT v3 platforms */ 42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, 43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, 44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, 46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, 47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, 48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, 49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, 50 51 /* I/OAT v3.2 platforms */ 52 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, 53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, 54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, 55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, 56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, 57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, 58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, 59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, 60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, 61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, 62 63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, 64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, 65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, 66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, 67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, 68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, 69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, 70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, 71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, 72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, 73 74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, 75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, 76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, 77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, 78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, 79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, 80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, 81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, 82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, 83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, 84 85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, 86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, 87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, 88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, 89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, 90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, 91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, 92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, 93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, 94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, 95 96 /* I/OAT v3.3 platforms */ 97 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, 99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, 100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, 101 102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, 103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, 104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, 105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, 106 107 { 0, } 108 }; 109 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); 110 111 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 112 static void ioat_remove(struct pci_dev *pdev); 113 static void 114 ioat_init_channel(struct ioatdma_device *ioat_dma, 115 struct ioatdma_chan *ioat_chan, int idx); 116 117 static int ioat_dca_enabled = 1; 118 module_param(ioat_dca_enabled, int, 0644); 119 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); 120 int ioat_pending_level = 4; 121 module_param(ioat_pending_level, int, 0644); 122 MODULE_PARM_DESC(ioat_pending_level, 123 "high-water mark for pushing ioat descriptors (default: 4)"); 124 int ioat_ring_alloc_order = 8; 125 module_param(ioat_ring_alloc_order, int, 0644); 126 MODULE_PARM_DESC(ioat_ring_alloc_order, 127 "ioat+: allocate 2^n descriptors per channel (default: 8 max: 16)"); 128 int ioat_ring_max_alloc_order = IOAT_MAX_ORDER; 129 module_param(ioat_ring_max_alloc_order, int, 0644); 130 MODULE_PARM_DESC(ioat_ring_max_alloc_order, 131 "ioat+: upper limit for ring size (default: 16)"); 132 static char ioat_interrupt_style[32] = "msix"; 133 module_param_string(ioat_interrupt_style, ioat_interrupt_style, 134 sizeof(ioat_interrupt_style), 0644); 135 MODULE_PARM_DESC(ioat_interrupt_style, 136 "set ioat interrupt style: msix (default), msi, intx"); 137 138 struct kmem_cache *ioat_cache; 139 struct kmem_cache *ioat_sed_cache; 140 141 static bool is_jf_ioat(struct pci_dev *pdev) 142 { 143 switch (pdev->device) { 144 case PCI_DEVICE_ID_INTEL_IOAT_JSF0: 145 case PCI_DEVICE_ID_INTEL_IOAT_JSF1: 146 case PCI_DEVICE_ID_INTEL_IOAT_JSF2: 147 case PCI_DEVICE_ID_INTEL_IOAT_JSF3: 148 case PCI_DEVICE_ID_INTEL_IOAT_JSF4: 149 case PCI_DEVICE_ID_INTEL_IOAT_JSF5: 150 case PCI_DEVICE_ID_INTEL_IOAT_JSF6: 151 case PCI_DEVICE_ID_INTEL_IOAT_JSF7: 152 case PCI_DEVICE_ID_INTEL_IOAT_JSF8: 153 case PCI_DEVICE_ID_INTEL_IOAT_JSF9: 154 return true; 155 default: 156 return false; 157 } 158 } 159 160 static bool is_snb_ioat(struct pci_dev *pdev) 161 { 162 switch (pdev->device) { 163 case PCI_DEVICE_ID_INTEL_IOAT_SNB0: 164 case PCI_DEVICE_ID_INTEL_IOAT_SNB1: 165 case PCI_DEVICE_ID_INTEL_IOAT_SNB2: 166 case PCI_DEVICE_ID_INTEL_IOAT_SNB3: 167 case PCI_DEVICE_ID_INTEL_IOAT_SNB4: 168 case PCI_DEVICE_ID_INTEL_IOAT_SNB5: 169 case PCI_DEVICE_ID_INTEL_IOAT_SNB6: 170 case PCI_DEVICE_ID_INTEL_IOAT_SNB7: 171 case PCI_DEVICE_ID_INTEL_IOAT_SNB8: 172 case PCI_DEVICE_ID_INTEL_IOAT_SNB9: 173 return true; 174 default: 175 return false; 176 } 177 } 178 179 static bool is_ivb_ioat(struct pci_dev *pdev) 180 { 181 switch (pdev->device) { 182 case PCI_DEVICE_ID_INTEL_IOAT_IVB0: 183 case PCI_DEVICE_ID_INTEL_IOAT_IVB1: 184 case PCI_DEVICE_ID_INTEL_IOAT_IVB2: 185 case PCI_DEVICE_ID_INTEL_IOAT_IVB3: 186 case PCI_DEVICE_ID_INTEL_IOAT_IVB4: 187 case PCI_DEVICE_ID_INTEL_IOAT_IVB5: 188 case PCI_DEVICE_ID_INTEL_IOAT_IVB6: 189 case PCI_DEVICE_ID_INTEL_IOAT_IVB7: 190 case PCI_DEVICE_ID_INTEL_IOAT_IVB8: 191 case PCI_DEVICE_ID_INTEL_IOAT_IVB9: 192 return true; 193 default: 194 return false; 195 } 196 197 } 198 199 static bool is_hsw_ioat(struct pci_dev *pdev) 200 { 201 switch (pdev->device) { 202 case PCI_DEVICE_ID_INTEL_IOAT_HSW0: 203 case PCI_DEVICE_ID_INTEL_IOAT_HSW1: 204 case PCI_DEVICE_ID_INTEL_IOAT_HSW2: 205 case PCI_DEVICE_ID_INTEL_IOAT_HSW3: 206 case PCI_DEVICE_ID_INTEL_IOAT_HSW4: 207 case PCI_DEVICE_ID_INTEL_IOAT_HSW5: 208 case PCI_DEVICE_ID_INTEL_IOAT_HSW6: 209 case PCI_DEVICE_ID_INTEL_IOAT_HSW7: 210 case PCI_DEVICE_ID_INTEL_IOAT_HSW8: 211 case PCI_DEVICE_ID_INTEL_IOAT_HSW9: 212 return true; 213 default: 214 return false; 215 } 216 217 } 218 219 static bool is_xeon_cb32(struct pci_dev *pdev) 220 { 221 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 222 is_hsw_ioat(pdev); 223 } 224 225 bool is_bwd_ioat(struct pci_dev *pdev) 226 { 227 switch (pdev->device) { 228 case PCI_DEVICE_ID_INTEL_IOAT_BWD0: 229 case PCI_DEVICE_ID_INTEL_IOAT_BWD1: 230 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 231 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 232 /* even though not Atom, BDX-DE has same DMA silicon */ 233 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 234 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 235 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 236 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 237 return true; 238 default: 239 return false; 240 } 241 } 242 243 static bool is_bwd_noraid(struct pci_dev *pdev) 244 { 245 switch (pdev->device) { 246 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 247 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 248 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 249 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 250 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 251 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 252 return true; 253 default: 254 return false; 255 } 256 257 } 258 259 /* 260 * Perform a IOAT transaction to verify the HW works. 261 */ 262 #define IOAT_TEST_SIZE 2000 263 264 static void ioat_dma_test_callback(void *dma_async_param) 265 { 266 struct completion *cmp = dma_async_param; 267 268 complete(cmp); 269 } 270 271 /** 272 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. 273 * @ioat_dma: dma device to be tested 274 */ 275 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) 276 { 277 int i; 278 u8 *src; 279 u8 *dest; 280 struct dma_device *dma = &ioat_dma->dma_dev; 281 struct device *dev = &ioat_dma->pdev->dev; 282 struct dma_chan *dma_chan; 283 struct dma_async_tx_descriptor *tx; 284 dma_addr_t dma_dest, dma_src; 285 dma_cookie_t cookie; 286 int err = 0; 287 struct completion cmp; 288 unsigned long tmo; 289 unsigned long flags; 290 291 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); 292 if (!src) 293 return -ENOMEM; 294 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); 295 if (!dest) { 296 kfree(src); 297 return -ENOMEM; 298 } 299 300 /* Fill in src buffer */ 301 for (i = 0; i < IOAT_TEST_SIZE; i++) 302 src[i] = (u8)i; 303 304 /* Start copy, using first DMA channel */ 305 dma_chan = container_of(dma->channels.next, struct dma_chan, 306 device_node); 307 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 308 dev_err(dev, "selftest cannot allocate chan resource\n"); 309 err = -ENODEV; 310 goto out; 311 } 312 313 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 314 if (dma_mapping_error(dev, dma_src)) { 315 dev_err(dev, "mapping src buffer failed\n"); 316 goto free_resources; 317 } 318 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 319 if (dma_mapping_error(dev, dma_dest)) { 320 dev_err(dev, "mapping dest buffer failed\n"); 321 goto unmap_src; 322 } 323 flags = DMA_PREP_INTERRUPT; 324 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, 325 dma_src, IOAT_TEST_SIZE, 326 flags); 327 if (!tx) { 328 dev_err(dev, "Self-test prep failed, disabling\n"); 329 err = -ENODEV; 330 goto unmap_dma; 331 } 332 333 async_tx_ack(tx); 334 init_completion(&cmp); 335 tx->callback = ioat_dma_test_callback; 336 tx->callback_param = &cmp; 337 cookie = tx->tx_submit(tx); 338 if (cookie < 0) { 339 dev_err(dev, "Self-test setup failed, disabling\n"); 340 err = -ENODEV; 341 goto unmap_dma; 342 } 343 dma->device_issue_pending(dma_chan); 344 345 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 346 347 if (tmo == 0 || 348 dma->device_tx_status(dma_chan, cookie, NULL) 349 != DMA_COMPLETE) { 350 dev_err(dev, "Self-test copy timed out, disabling\n"); 351 err = -ENODEV; 352 goto unmap_dma; 353 } 354 if (memcmp(src, dest, IOAT_TEST_SIZE)) { 355 dev_err(dev, "Self-test copy failed compare, disabling\n"); 356 err = -ENODEV; 357 goto free_resources; 358 } 359 360 unmap_dma: 361 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 362 unmap_src: 363 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 364 free_resources: 365 dma->device_free_chan_resources(dma_chan); 366 out: 367 kfree(src); 368 kfree(dest); 369 return err; 370 } 371 372 /** 373 * ioat_dma_setup_interrupts - setup interrupt handler 374 * @ioat_dma: ioat dma device 375 */ 376 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) 377 { 378 struct ioatdma_chan *ioat_chan; 379 struct pci_dev *pdev = ioat_dma->pdev; 380 struct device *dev = &pdev->dev; 381 struct msix_entry *msix; 382 int i, j, msixcnt; 383 int err = -EINVAL; 384 u8 intrctrl = 0; 385 386 if (!strcmp(ioat_interrupt_style, "msix")) 387 goto msix; 388 if (!strcmp(ioat_interrupt_style, "msi")) 389 goto msi; 390 if (!strcmp(ioat_interrupt_style, "intx")) 391 goto intx; 392 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); 393 goto err_no_irq; 394 395 msix: 396 /* The number of MSI-X vectors should equal the number of channels */ 397 msixcnt = ioat_dma->dma_dev.chancnt; 398 for (i = 0; i < msixcnt; i++) 399 ioat_dma->msix_entries[i].entry = i; 400 401 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); 402 if (err) 403 goto msi; 404 405 for (i = 0; i < msixcnt; i++) { 406 msix = &ioat_dma->msix_entries[i]; 407 ioat_chan = ioat_chan_by_index(ioat_dma, i); 408 err = devm_request_irq(dev, msix->vector, 409 ioat_dma_do_interrupt_msix, 0, 410 "ioat-msix", ioat_chan); 411 if (err) { 412 for (j = 0; j < i; j++) { 413 msix = &ioat_dma->msix_entries[j]; 414 ioat_chan = ioat_chan_by_index(ioat_dma, j); 415 devm_free_irq(dev, msix->vector, ioat_chan); 416 } 417 goto msi; 418 } 419 } 420 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; 421 ioat_dma->irq_mode = IOAT_MSIX; 422 goto done; 423 424 msi: 425 err = pci_enable_msi(pdev); 426 if (err) 427 goto intx; 428 429 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, 430 "ioat-msi", ioat_dma); 431 if (err) { 432 pci_disable_msi(pdev); 433 goto intx; 434 } 435 ioat_dma->irq_mode = IOAT_MSI; 436 goto done; 437 438 intx: 439 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 440 IRQF_SHARED, "ioat-intx", ioat_dma); 441 if (err) 442 goto err_no_irq; 443 444 ioat_dma->irq_mode = IOAT_INTX; 445 done: 446 if (ioat_dma->intr_quirk) 447 ioat_dma->intr_quirk(ioat_dma); 448 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; 449 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 450 return 0; 451 452 err_no_irq: 453 /* Disable all interrupt generation */ 454 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 455 ioat_dma->irq_mode = IOAT_NOIRQ; 456 dev_err(dev, "no usable interrupts\n"); 457 return err; 458 } 459 460 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) 461 { 462 /* Disable all interrupt generation */ 463 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 464 } 465 466 static int ioat_probe(struct ioatdma_device *ioat_dma) 467 { 468 int err = -ENODEV; 469 struct dma_device *dma = &ioat_dma->dma_dev; 470 struct pci_dev *pdev = ioat_dma->pdev; 471 struct device *dev = &pdev->dev; 472 473 /* DMA coherent memory pool for DMA descriptor allocations */ 474 ioat_dma->dma_pool = pci_pool_create("dma_desc_pool", pdev, 475 sizeof(struct ioat_dma_descriptor), 476 64, 0); 477 if (!ioat_dma->dma_pool) { 478 err = -ENOMEM; 479 goto err_dma_pool; 480 } 481 482 ioat_dma->completion_pool = pci_pool_create("completion_pool", pdev, 483 sizeof(u64), 484 SMP_CACHE_BYTES, 485 SMP_CACHE_BYTES); 486 487 if (!ioat_dma->completion_pool) { 488 err = -ENOMEM; 489 goto err_completion_pool; 490 } 491 492 ioat_dma->enumerate_channels(ioat_dma); 493 494 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 495 dma->dev = &pdev->dev; 496 497 if (!dma->chancnt) { 498 dev_err(dev, "channel enumeration error\n"); 499 goto err_setup_interrupts; 500 } 501 502 err = ioat_dma_setup_interrupts(ioat_dma); 503 if (err) 504 goto err_setup_interrupts; 505 506 err = ioat_dma->self_test(ioat_dma); 507 if (err) 508 goto err_self_test; 509 510 return 0; 511 512 err_self_test: 513 ioat_disable_interrupts(ioat_dma); 514 err_setup_interrupts: 515 pci_pool_destroy(ioat_dma->completion_pool); 516 err_completion_pool: 517 pci_pool_destroy(ioat_dma->dma_pool); 518 err_dma_pool: 519 return err; 520 } 521 522 static int ioat_register(struct ioatdma_device *ioat_dma) 523 { 524 int err = dma_async_device_register(&ioat_dma->dma_dev); 525 526 if (err) { 527 ioat_disable_interrupts(ioat_dma); 528 pci_pool_destroy(ioat_dma->completion_pool); 529 pci_pool_destroy(ioat_dma->dma_pool); 530 } 531 532 return err; 533 } 534 535 static void ioat_dma_remove(struct ioatdma_device *ioat_dma) 536 { 537 struct dma_device *dma = &ioat_dma->dma_dev; 538 539 ioat_disable_interrupts(ioat_dma); 540 541 ioat_kobject_del(ioat_dma); 542 543 dma_async_device_unregister(dma); 544 545 pci_pool_destroy(ioat_dma->dma_pool); 546 pci_pool_destroy(ioat_dma->completion_pool); 547 548 INIT_LIST_HEAD(&dma->channels); 549 } 550 551 /** 552 * ioat_enumerate_channels - find and initialize the device's channels 553 * @ioat_dma: the ioat dma device to be enumerated 554 */ 555 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma) 556 { 557 struct ioatdma_chan *ioat_chan; 558 struct device *dev = &ioat_dma->pdev->dev; 559 struct dma_device *dma = &ioat_dma->dma_dev; 560 u8 xfercap_log; 561 int i; 562 563 INIT_LIST_HEAD(&dma->channels); 564 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); 565 dma->chancnt &= 0x1f; /* bits [4:0] valid */ 566 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) { 567 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", 568 dma->chancnt, ARRAY_SIZE(ioat_dma->idx)); 569 dma->chancnt = ARRAY_SIZE(ioat_dma->idx); 570 } 571 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); 572 xfercap_log &= 0x1f; /* bits [4:0] valid */ 573 if (xfercap_log == 0) 574 return 0; 575 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); 576 577 for (i = 0; i < dma->chancnt; i++) { 578 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); 579 if (!ioat_chan) 580 break; 581 582 ioat_init_channel(ioat_dma, ioat_chan, i); 583 ioat_chan->xfercap_log = xfercap_log; 584 spin_lock_init(&ioat_chan->prep_lock); 585 if (ioat_dma->reset_hw(ioat_chan)) { 586 i = 0; 587 break; 588 } 589 } 590 dma->chancnt = i; 591 return i; 592 } 593 594 /** 595 * ioat_free_chan_resources - release all the descriptors 596 * @chan: the channel to be cleaned 597 */ 598 static void ioat_free_chan_resources(struct dma_chan *c) 599 { 600 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 601 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; 602 struct ioat_ring_ent *desc; 603 const int total_descs = 1 << ioat_chan->alloc_order; 604 int descs; 605 int i; 606 607 /* Before freeing channel resources first check 608 * if they have been previously allocated for this channel. 609 */ 610 if (!ioat_chan->ring) 611 return; 612 613 ioat_stop(ioat_chan); 614 ioat_dma->reset_hw(ioat_chan); 615 616 spin_lock_bh(&ioat_chan->cleanup_lock); 617 spin_lock_bh(&ioat_chan->prep_lock); 618 descs = ioat_ring_space(ioat_chan); 619 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); 620 for (i = 0; i < descs; i++) { 621 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); 622 ioat_free_ring_ent(desc, c); 623 } 624 625 if (descs < total_descs) 626 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", 627 total_descs - descs); 628 629 for (i = 0; i < total_descs - descs; i++) { 630 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); 631 dump_desc_dbg(ioat_chan, desc); 632 ioat_free_ring_ent(desc, c); 633 } 634 635 kfree(ioat_chan->ring); 636 ioat_chan->ring = NULL; 637 ioat_chan->alloc_order = 0; 638 pci_pool_free(ioat_dma->completion_pool, ioat_chan->completion, 639 ioat_chan->completion_dma); 640 spin_unlock_bh(&ioat_chan->prep_lock); 641 spin_unlock_bh(&ioat_chan->cleanup_lock); 642 643 ioat_chan->last_completion = 0; 644 ioat_chan->completion_dma = 0; 645 ioat_chan->dmacount = 0; 646 } 647 648 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring 649 * @chan: channel to be initialized 650 */ 651 static int ioat_alloc_chan_resources(struct dma_chan *c) 652 { 653 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 654 struct ioat_ring_ent **ring; 655 u64 status; 656 int order; 657 int i = 0; 658 u32 chanerr; 659 660 /* have we already been set up? */ 661 if (ioat_chan->ring) 662 return 1 << ioat_chan->alloc_order; 663 664 /* Setup register to interrupt and write completion status on error */ 665 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); 666 667 /* allocate a completion writeback area */ 668 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 669 ioat_chan->completion = 670 pci_pool_alloc(ioat_chan->ioat_dma->completion_pool, 671 GFP_KERNEL, &ioat_chan->completion_dma); 672 if (!ioat_chan->completion) 673 return -ENOMEM; 674 675 memset(ioat_chan->completion, 0, sizeof(*ioat_chan->completion)); 676 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, 677 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); 678 writel(((u64)ioat_chan->completion_dma) >> 32, 679 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 680 681 order = ioat_get_alloc_order(); 682 ring = ioat_alloc_ring(c, order, GFP_KERNEL); 683 if (!ring) 684 return -ENOMEM; 685 686 spin_lock_bh(&ioat_chan->cleanup_lock); 687 spin_lock_bh(&ioat_chan->prep_lock); 688 ioat_chan->ring = ring; 689 ioat_chan->head = 0; 690 ioat_chan->issued = 0; 691 ioat_chan->tail = 0; 692 ioat_chan->alloc_order = order; 693 set_bit(IOAT_RUN, &ioat_chan->state); 694 spin_unlock_bh(&ioat_chan->prep_lock); 695 spin_unlock_bh(&ioat_chan->cleanup_lock); 696 697 ioat_start_null_desc(ioat_chan); 698 699 /* check that we got off the ground */ 700 do { 701 udelay(1); 702 status = ioat_chansts(ioat_chan); 703 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); 704 705 if (is_ioat_active(status) || is_ioat_idle(status)) 706 return 1 << ioat_chan->alloc_order; 707 708 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 709 710 dev_WARN(to_dev(ioat_chan), 711 "failed to start channel chanerr: %#x\n", chanerr); 712 ioat_free_chan_resources(c); 713 return -EFAULT; 714 } 715 716 /* common channel initialization */ 717 static void 718 ioat_init_channel(struct ioatdma_device *ioat_dma, 719 struct ioatdma_chan *ioat_chan, int idx) 720 { 721 struct dma_device *dma = &ioat_dma->dma_dev; 722 struct dma_chan *c = &ioat_chan->dma_chan; 723 unsigned long data = (unsigned long) c; 724 725 ioat_chan->ioat_dma = ioat_dma; 726 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); 727 spin_lock_init(&ioat_chan->cleanup_lock); 728 ioat_chan->dma_chan.device = dma; 729 dma_cookie_init(&ioat_chan->dma_chan); 730 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); 731 ioat_dma->idx[idx] = ioat_chan; 732 init_timer(&ioat_chan->timer); 733 ioat_chan->timer.function = ioat_dma->timer_fn; 734 ioat_chan->timer.data = data; 735 tasklet_init(&ioat_chan->cleanup_task, ioat_dma->cleanup_fn, data); 736 } 737 738 static void ioat3_dma_test_callback(void *dma_async_param) 739 { 740 struct completion *cmp = dma_async_param; 741 742 complete(cmp); 743 } 744 745 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ 746 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) 747 { 748 int i, src_idx; 749 struct page *dest; 750 struct page *xor_srcs[IOAT_NUM_SRC_TEST]; 751 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; 752 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; 753 dma_addr_t dest_dma; 754 struct dma_async_tx_descriptor *tx; 755 struct dma_chan *dma_chan; 756 dma_cookie_t cookie; 757 u8 cmp_byte = 0; 758 u32 cmp_word; 759 u32 xor_val_result; 760 int err = 0; 761 struct completion cmp; 762 unsigned long tmo; 763 struct device *dev = &ioat_dma->pdev->dev; 764 struct dma_device *dma = &ioat_dma->dma_dev; 765 u8 op = 0; 766 767 dev_dbg(dev, "%s\n", __func__); 768 769 if (!dma_has_cap(DMA_XOR, dma->cap_mask)) 770 return 0; 771 772 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 773 xor_srcs[src_idx] = alloc_page(GFP_KERNEL); 774 if (!xor_srcs[src_idx]) { 775 while (src_idx--) 776 __free_page(xor_srcs[src_idx]); 777 return -ENOMEM; 778 } 779 } 780 781 dest = alloc_page(GFP_KERNEL); 782 if (!dest) { 783 while (src_idx--) 784 __free_page(xor_srcs[src_idx]); 785 return -ENOMEM; 786 } 787 788 /* Fill in src buffers */ 789 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 790 u8 *ptr = page_address(xor_srcs[src_idx]); 791 792 for (i = 0; i < PAGE_SIZE; i++) 793 ptr[i] = (1 << src_idx); 794 } 795 796 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) 797 cmp_byte ^= (u8) (1 << src_idx); 798 799 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | 800 (cmp_byte << 8) | cmp_byte; 801 802 memset(page_address(dest), 0, PAGE_SIZE); 803 804 dma_chan = container_of(dma->channels.next, struct dma_chan, 805 device_node); 806 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 807 err = -ENODEV; 808 goto out; 809 } 810 811 /* test xor */ 812 op = IOAT_OP_XOR; 813 814 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); 815 if (dma_mapping_error(dev, dest_dma)) 816 goto dma_unmap; 817 818 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 819 dma_srcs[i] = DMA_ERROR_CODE; 820 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { 821 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, 822 DMA_TO_DEVICE); 823 if (dma_mapping_error(dev, dma_srcs[i])) 824 goto dma_unmap; 825 } 826 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, 827 IOAT_NUM_SRC_TEST, PAGE_SIZE, 828 DMA_PREP_INTERRUPT); 829 830 if (!tx) { 831 dev_err(dev, "Self-test xor prep failed\n"); 832 err = -ENODEV; 833 goto dma_unmap; 834 } 835 836 async_tx_ack(tx); 837 init_completion(&cmp); 838 tx->callback = ioat3_dma_test_callback; 839 tx->callback_param = &cmp; 840 cookie = tx->tx_submit(tx); 841 if (cookie < 0) { 842 dev_err(dev, "Self-test xor setup failed\n"); 843 err = -ENODEV; 844 goto dma_unmap; 845 } 846 dma->device_issue_pending(dma_chan); 847 848 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 849 850 if (tmo == 0 || 851 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 852 dev_err(dev, "Self-test xor timed out\n"); 853 err = -ENODEV; 854 goto dma_unmap; 855 } 856 857 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 858 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 859 860 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 861 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { 862 u32 *ptr = page_address(dest); 863 864 if (ptr[i] != cmp_word) { 865 dev_err(dev, "Self-test xor failed compare\n"); 866 err = -ENODEV; 867 goto free_resources; 868 } 869 } 870 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 871 872 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 873 874 /* skip validate if the capability is not present */ 875 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) 876 goto free_resources; 877 878 op = IOAT_OP_XOR_VAL; 879 880 /* validate the sources with the destintation page */ 881 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 882 xor_val_srcs[i] = xor_srcs[i]; 883 xor_val_srcs[i] = dest; 884 885 xor_val_result = 1; 886 887 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 888 dma_srcs[i] = DMA_ERROR_CODE; 889 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 890 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 891 DMA_TO_DEVICE); 892 if (dma_mapping_error(dev, dma_srcs[i])) 893 goto dma_unmap; 894 } 895 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 896 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 897 &xor_val_result, DMA_PREP_INTERRUPT); 898 if (!tx) { 899 dev_err(dev, "Self-test zero prep failed\n"); 900 err = -ENODEV; 901 goto dma_unmap; 902 } 903 904 async_tx_ack(tx); 905 init_completion(&cmp); 906 tx->callback = ioat3_dma_test_callback; 907 tx->callback_param = &cmp; 908 cookie = tx->tx_submit(tx); 909 if (cookie < 0) { 910 dev_err(dev, "Self-test zero setup failed\n"); 911 err = -ENODEV; 912 goto dma_unmap; 913 } 914 dma->device_issue_pending(dma_chan); 915 916 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 917 918 if (tmo == 0 || 919 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 920 dev_err(dev, "Self-test validate timed out\n"); 921 err = -ENODEV; 922 goto dma_unmap; 923 } 924 925 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 926 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 927 928 if (xor_val_result != 0) { 929 dev_err(dev, "Self-test validate failed compare\n"); 930 err = -ENODEV; 931 goto free_resources; 932 } 933 934 memset(page_address(dest), 0, PAGE_SIZE); 935 936 /* test for non-zero parity sum */ 937 op = IOAT_OP_XOR_VAL; 938 939 xor_val_result = 0; 940 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 941 dma_srcs[i] = DMA_ERROR_CODE; 942 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 943 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 944 DMA_TO_DEVICE); 945 if (dma_mapping_error(dev, dma_srcs[i])) 946 goto dma_unmap; 947 } 948 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 949 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 950 &xor_val_result, DMA_PREP_INTERRUPT); 951 if (!tx) { 952 dev_err(dev, "Self-test 2nd zero prep failed\n"); 953 err = -ENODEV; 954 goto dma_unmap; 955 } 956 957 async_tx_ack(tx); 958 init_completion(&cmp); 959 tx->callback = ioat3_dma_test_callback; 960 tx->callback_param = &cmp; 961 cookie = tx->tx_submit(tx); 962 if (cookie < 0) { 963 dev_err(dev, "Self-test 2nd zero setup failed\n"); 964 err = -ENODEV; 965 goto dma_unmap; 966 } 967 dma->device_issue_pending(dma_chan); 968 969 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 970 971 if (tmo == 0 || 972 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 973 dev_err(dev, "Self-test 2nd validate timed out\n"); 974 err = -ENODEV; 975 goto dma_unmap; 976 } 977 978 if (xor_val_result != SUM_CHECK_P_RESULT) { 979 dev_err(dev, "Self-test validate failed compare\n"); 980 err = -ENODEV; 981 goto dma_unmap; 982 } 983 984 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 985 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 986 987 goto free_resources; 988 dma_unmap: 989 if (op == IOAT_OP_XOR) { 990 if (dest_dma != DMA_ERROR_CODE) 991 dma_unmap_page(dev, dest_dma, PAGE_SIZE, 992 DMA_FROM_DEVICE); 993 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 994 if (dma_srcs[i] != DMA_ERROR_CODE) 995 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 996 DMA_TO_DEVICE); 997 } else if (op == IOAT_OP_XOR_VAL) { 998 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 999 if (dma_srcs[i] != DMA_ERROR_CODE) 1000 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1001 DMA_TO_DEVICE); 1002 } 1003 free_resources: 1004 dma->device_free_chan_resources(dma_chan); 1005 out: 1006 src_idx = IOAT_NUM_SRC_TEST; 1007 while (src_idx--) 1008 __free_page(xor_srcs[src_idx]); 1009 __free_page(dest); 1010 return err; 1011 } 1012 1013 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) 1014 { 1015 int rc = ioat_dma_self_test(ioat_dma); 1016 1017 if (rc) 1018 return rc; 1019 1020 rc = ioat_xor_val_self_test(ioat_dma); 1021 if (rc) 1022 return rc; 1023 1024 return 0; 1025 } 1026 1027 static void ioat3_intr_quirk(struct ioatdma_device *ioat_dma) 1028 { 1029 struct dma_device *dma; 1030 struct dma_chan *c; 1031 struct ioatdma_chan *ioat_chan; 1032 u32 errmask; 1033 1034 dma = &ioat_dma->dma_dev; 1035 1036 /* 1037 * if we have descriptor write back error status, we mask the 1038 * error interrupts 1039 */ 1040 if (ioat_dma->cap & IOAT_CAP_DWBES) { 1041 list_for_each_entry(c, &dma->channels, device_node) { 1042 ioat_chan = to_ioat_chan(c); 1043 errmask = readl(ioat_chan->reg_base + 1044 IOAT_CHANERR_MASK_OFFSET); 1045 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | 1046 IOAT_CHANERR_XOR_Q_ERR; 1047 writel(errmask, ioat_chan->reg_base + 1048 IOAT_CHANERR_MASK_OFFSET); 1049 } 1050 } 1051 } 1052 1053 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 1054 { 1055 struct pci_dev *pdev = ioat_dma->pdev; 1056 int dca_en = system_has_dca_enabled(pdev); 1057 struct dma_device *dma; 1058 struct dma_chan *c; 1059 struct ioatdma_chan *ioat_chan; 1060 bool is_raid_device = false; 1061 int err; 1062 1063 ioat_dma->enumerate_channels = ioat_enumerate_channels; 1064 ioat_dma->reset_hw = ioat_reset_hw; 1065 ioat_dma->self_test = ioat3_dma_self_test; 1066 ioat_dma->intr_quirk = ioat3_intr_quirk; 1067 dma = &ioat_dma->dma_dev; 1068 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; 1069 dma->device_issue_pending = ioat_issue_pending; 1070 dma->device_alloc_chan_resources = ioat_alloc_chan_resources; 1071 dma->device_free_chan_resources = ioat_free_chan_resources; 1072 1073 dma_cap_set(DMA_INTERRUPT, dma->cap_mask); 1074 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; 1075 1076 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); 1077 1078 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) 1079 ioat_dma->cap &= 1080 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); 1081 1082 /* dca is incompatible with raid operations */ 1083 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) 1084 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); 1085 1086 if (ioat_dma->cap & IOAT_CAP_XOR) { 1087 is_raid_device = true; 1088 dma->max_xor = 8; 1089 1090 dma_cap_set(DMA_XOR, dma->cap_mask); 1091 dma->device_prep_dma_xor = ioat_prep_xor; 1092 1093 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1094 dma->device_prep_dma_xor_val = ioat_prep_xor_val; 1095 } 1096 1097 if (ioat_dma->cap & IOAT_CAP_PQ) { 1098 is_raid_device = true; 1099 1100 dma->device_prep_dma_pq = ioat_prep_pq; 1101 dma->device_prep_dma_pq_val = ioat_prep_pq_val; 1102 dma_cap_set(DMA_PQ, dma->cap_mask); 1103 dma_cap_set(DMA_PQ_VAL, dma->cap_mask); 1104 1105 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1106 dma_set_maxpq(dma, 16, 0); 1107 else 1108 dma_set_maxpq(dma, 8, 0); 1109 1110 if (!(ioat_dma->cap & IOAT_CAP_XOR)) { 1111 dma->device_prep_dma_xor = ioat_prep_pqxor; 1112 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; 1113 dma_cap_set(DMA_XOR, dma->cap_mask); 1114 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1115 1116 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1117 dma->max_xor = 16; 1118 else 1119 dma->max_xor = 8; 1120 } 1121 } 1122 1123 dma->device_tx_status = ioat_tx_status; 1124 ioat_dma->cleanup_fn = ioat_cleanup_event; 1125 ioat_dma->timer_fn = ioat_timer_event; 1126 1127 /* starting with CB3.3 super extended descriptors are supported */ 1128 if (ioat_dma->cap & IOAT_CAP_RAID16SS) { 1129 char pool_name[14]; 1130 int i; 1131 1132 for (i = 0; i < MAX_SED_POOLS; i++) { 1133 snprintf(pool_name, 14, "ioat_hw%d_sed", i); 1134 1135 /* allocate SED DMA pool */ 1136 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, 1137 &pdev->dev, 1138 SED_SIZE * (i + 1), 64, 0); 1139 if (!ioat_dma->sed_hw_pool[i]) 1140 return -ENOMEM; 1141 1142 } 1143 } 1144 1145 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) 1146 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1147 1148 err = ioat_probe(ioat_dma); 1149 if (err) 1150 return err; 1151 1152 list_for_each_entry(c, &dma->channels, device_node) { 1153 ioat_chan = to_ioat_chan(c); 1154 writel(IOAT_DMA_DCA_ANY_CPU, 1155 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 1156 } 1157 1158 err = ioat_register(ioat_dma); 1159 if (err) 1160 return err; 1161 1162 ioat_kobject_add(ioat_dma, &ioat_ktype); 1163 1164 if (dca) 1165 ioat_dma->dca = ioat3_dca_init(pdev, ioat_dma->reg_base); 1166 1167 return 0; 1168 } 1169 1170 #define DRV_NAME "ioatdma" 1171 1172 static struct pci_driver ioat_pci_driver = { 1173 .name = DRV_NAME, 1174 .id_table = ioat_pci_tbl, 1175 .probe = ioat_pci_probe, 1176 .remove = ioat_remove, 1177 }; 1178 1179 static struct ioatdma_device * 1180 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) 1181 { 1182 struct device *dev = &pdev->dev; 1183 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 1184 1185 if (!d) 1186 return NULL; 1187 d->pdev = pdev; 1188 d->reg_base = iobase; 1189 return d; 1190 } 1191 1192 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1193 { 1194 void __iomem * const *iomap; 1195 struct device *dev = &pdev->dev; 1196 struct ioatdma_device *device; 1197 int err; 1198 1199 err = pcim_enable_device(pdev); 1200 if (err) 1201 return err; 1202 1203 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); 1204 if (err) 1205 return err; 1206 iomap = pcim_iomap_table(pdev); 1207 if (!iomap) 1208 return -ENOMEM; 1209 1210 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1211 if (err) 1212 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1213 if (err) 1214 return err; 1215 1216 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1217 if (err) 1218 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1219 if (err) 1220 return err; 1221 1222 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); 1223 if (!device) 1224 return -ENOMEM; 1225 pci_set_master(pdev); 1226 pci_set_drvdata(pdev, device); 1227 1228 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1229 if (device->version >= IOAT_VER_3_0) 1230 err = ioat3_dma_probe(device, ioat_dca_enabled); 1231 else 1232 return -ENODEV; 1233 1234 if (err) { 1235 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); 1236 return -ENODEV; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static void ioat_remove(struct pci_dev *pdev) 1243 { 1244 struct ioatdma_device *device = pci_get_drvdata(pdev); 1245 1246 if (!device) 1247 return; 1248 1249 dev_err(&pdev->dev, "Removing dma and dca services\n"); 1250 if (device->dca) { 1251 unregister_dca_provider(device->dca, &pdev->dev); 1252 free_dca_provider(device->dca); 1253 device->dca = NULL; 1254 } 1255 ioat_dma_remove(device); 1256 } 1257 1258 static int __init ioat_init_module(void) 1259 { 1260 int err = -ENOMEM; 1261 1262 pr_info("%s: Intel(R) QuickData Technology Driver %s\n", 1263 DRV_NAME, IOAT_DMA_VERSION); 1264 1265 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), 1266 0, SLAB_HWCACHE_ALIGN, NULL); 1267 if (!ioat_cache) 1268 return -ENOMEM; 1269 1270 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); 1271 if (!ioat_sed_cache) 1272 goto err_ioat_cache; 1273 1274 err = pci_register_driver(&ioat_pci_driver); 1275 if (err) 1276 goto err_ioat3_cache; 1277 1278 return 0; 1279 1280 err_ioat3_cache: 1281 kmem_cache_destroy(ioat_sed_cache); 1282 1283 err_ioat_cache: 1284 kmem_cache_destroy(ioat_cache); 1285 1286 return err; 1287 } 1288 module_init(ioat_init_module); 1289 1290 static void __exit ioat_exit_module(void) 1291 { 1292 pci_unregister_driver(&ioat_pci_driver); 1293 kmem_cache_destroy(ioat_cache); 1294 } 1295 module_exit(ioat_exit_module); 1296