1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel I/OAT DMA Linux driver 4 * Copyright(c) 2004 - 2015 Intel Corporation. 5 */ 6 7 #include <linux/init.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/pci.h> 11 #include <linux/interrupt.h> 12 #include <linux/dmaengine.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/workqueue.h> 16 #include <linux/prefetch.h> 17 #include <linux/dca.h> 18 #include <linux/sizes.h> 19 #include "dma.h" 20 #include "registers.h" 21 #include "hw.h" 22 23 #include "../dmaengine.h" 24 25 MODULE_VERSION(IOAT_DMA_VERSION); 26 MODULE_LICENSE("Dual BSD/GPL"); 27 MODULE_AUTHOR("Intel Corporation"); 28 29 static const struct pci_device_id ioat_pci_tbl[] = { 30 /* I/OAT v3 platforms */ 31 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, 32 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, 33 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, 34 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, 35 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, 36 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, 37 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, 38 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, 39 40 /* I/OAT v3.2 platforms */ 41 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, 42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, 43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, 44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, 46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, 47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, 48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, 49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, 50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, 51 52 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, 53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, 54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, 55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, 56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, 57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, 58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, 59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, 60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, 61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, 62 63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, 64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, 65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, 66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, 67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, 68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, 69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, 70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, 71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, 72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, 73 74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, 75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, 76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, 77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, 78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, 79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, 80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, 81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, 82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, 83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, 84 85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) }, 86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) }, 87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) }, 88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) }, 89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) }, 90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) }, 91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) }, 92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) }, 93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) }, 94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) }, 95 96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) }, 97 98 /* I/OAT v3.3 platforms */ 99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, 101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, 102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, 103 104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, 105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, 106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, 107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, 108 109 /* I/OAT v3.4 platforms */ 110 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_ICX) }, 111 112 { 0, } 113 }; 114 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); 115 116 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 117 static void ioat_remove(struct pci_dev *pdev); 118 static void 119 ioat_init_channel(struct ioatdma_device *ioat_dma, 120 struct ioatdma_chan *ioat_chan, int idx); 121 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma); 122 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma); 123 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); 124 125 static int ioat_dca_enabled = 1; 126 module_param(ioat_dca_enabled, int, 0644); 127 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); 128 int ioat_pending_level = 7; 129 module_param(ioat_pending_level, int, 0644); 130 MODULE_PARM_DESC(ioat_pending_level, 131 "high-water mark for pushing ioat descriptors (default: 7)"); 132 static char ioat_interrupt_style[32] = "msix"; 133 module_param_string(ioat_interrupt_style, ioat_interrupt_style, 134 sizeof(ioat_interrupt_style), 0644); 135 MODULE_PARM_DESC(ioat_interrupt_style, 136 "set ioat interrupt style: msix (default), msi, intx"); 137 138 struct kmem_cache *ioat_cache; 139 struct kmem_cache *ioat_sed_cache; 140 141 static bool is_jf_ioat(struct pci_dev *pdev) 142 { 143 switch (pdev->device) { 144 case PCI_DEVICE_ID_INTEL_IOAT_JSF0: 145 case PCI_DEVICE_ID_INTEL_IOAT_JSF1: 146 case PCI_DEVICE_ID_INTEL_IOAT_JSF2: 147 case PCI_DEVICE_ID_INTEL_IOAT_JSF3: 148 case PCI_DEVICE_ID_INTEL_IOAT_JSF4: 149 case PCI_DEVICE_ID_INTEL_IOAT_JSF5: 150 case PCI_DEVICE_ID_INTEL_IOAT_JSF6: 151 case PCI_DEVICE_ID_INTEL_IOAT_JSF7: 152 case PCI_DEVICE_ID_INTEL_IOAT_JSF8: 153 case PCI_DEVICE_ID_INTEL_IOAT_JSF9: 154 return true; 155 default: 156 return false; 157 } 158 } 159 160 static bool is_snb_ioat(struct pci_dev *pdev) 161 { 162 switch (pdev->device) { 163 case PCI_DEVICE_ID_INTEL_IOAT_SNB0: 164 case PCI_DEVICE_ID_INTEL_IOAT_SNB1: 165 case PCI_DEVICE_ID_INTEL_IOAT_SNB2: 166 case PCI_DEVICE_ID_INTEL_IOAT_SNB3: 167 case PCI_DEVICE_ID_INTEL_IOAT_SNB4: 168 case PCI_DEVICE_ID_INTEL_IOAT_SNB5: 169 case PCI_DEVICE_ID_INTEL_IOAT_SNB6: 170 case PCI_DEVICE_ID_INTEL_IOAT_SNB7: 171 case PCI_DEVICE_ID_INTEL_IOAT_SNB8: 172 case PCI_DEVICE_ID_INTEL_IOAT_SNB9: 173 return true; 174 default: 175 return false; 176 } 177 } 178 179 static bool is_ivb_ioat(struct pci_dev *pdev) 180 { 181 switch (pdev->device) { 182 case PCI_DEVICE_ID_INTEL_IOAT_IVB0: 183 case PCI_DEVICE_ID_INTEL_IOAT_IVB1: 184 case PCI_DEVICE_ID_INTEL_IOAT_IVB2: 185 case PCI_DEVICE_ID_INTEL_IOAT_IVB3: 186 case PCI_DEVICE_ID_INTEL_IOAT_IVB4: 187 case PCI_DEVICE_ID_INTEL_IOAT_IVB5: 188 case PCI_DEVICE_ID_INTEL_IOAT_IVB6: 189 case PCI_DEVICE_ID_INTEL_IOAT_IVB7: 190 case PCI_DEVICE_ID_INTEL_IOAT_IVB8: 191 case PCI_DEVICE_ID_INTEL_IOAT_IVB9: 192 return true; 193 default: 194 return false; 195 } 196 197 } 198 199 static bool is_hsw_ioat(struct pci_dev *pdev) 200 { 201 switch (pdev->device) { 202 case PCI_DEVICE_ID_INTEL_IOAT_HSW0: 203 case PCI_DEVICE_ID_INTEL_IOAT_HSW1: 204 case PCI_DEVICE_ID_INTEL_IOAT_HSW2: 205 case PCI_DEVICE_ID_INTEL_IOAT_HSW3: 206 case PCI_DEVICE_ID_INTEL_IOAT_HSW4: 207 case PCI_DEVICE_ID_INTEL_IOAT_HSW5: 208 case PCI_DEVICE_ID_INTEL_IOAT_HSW6: 209 case PCI_DEVICE_ID_INTEL_IOAT_HSW7: 210 case PCI_DEVICE_ID_INTEL_IOAT_HSW8: 211 case PCI_DEVICE_ID_INTEL_IOAT_HSW9: 212 return true; 213 default: 214 return false; 215 } 216 217 } 218 219 static bool is_bdx_ioat(struct pci_dev *pdev) 220 { 221 switch (pdev->device) { 222 case PCI_DEVICE_ID_INTEL_IOAT_BDX0: 223 case PCI_DEVICE_ID_INTEL_IOAT_BDX1: 224 case PCI_DEVICE_ID_INTEL_IOAT_BDX2: 225 case PCI_DEVICE_ID_INTEL_IOAT_BDX3: 226 case PCI_DEVICE_ID_INTEL_IOAT_BDX4: 227 case PCI_DEVICE_ID_INTEL_IOAT_BDX5: 228 case PCI_DEVICE_ID_INTEL_IOAT_BDX6: 229 case PCI_DEVICE_ID_INTEL_IOAT_BDX7: 230 case PCI_DEVICE_ID_INTEL_IOAT_BDX8: 231 case PCI_DEVICE_ID_INTEL_IOAT_BDX9: 232 return true; 233 default: 234 return false; 235 } 236 } 237 238 static inline bool is_skx_ioat(struct pci_dev *pdev) 239 { 240 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false; 241 } 242 243 static bool is_xeon_cb32(struct pci_dev *pdev) 244 { 245 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 246 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev); 247 } 248 249 bool is_bwd_ioat(struct pci_dev *pdev) 250 { 251 switch (pdev->device) { 252 case PCI_DEVICE_ID_INTEL_IOAT_BWD0: 253 case PCI_DEVICE_ID_INTEL_IOAT_BWD1: 254 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 255 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 256 /* even though not Atom, BDX-DE has same DMA silicon */ 257 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 258 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 259 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 260 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 261 return true; 262 default: 263 return false; 264 } 265 } 266 267 static bool is_bwd_noraid(struct pci_dev *pdev) 268 { 269 switch (pdev->device) { 270 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 271 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 272 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 273 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 274 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 275 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 276 return true; 277 default: 278 return false; 279 } 280 281 } 282 283 /* 284 * Perform a IOAT transaction to verify the HW works. 285 */ 286 #define IOAT_TEST_SIZE 2000 287 288 static void ioat_dma_test_callback(void *dma_async_param) 289 { 290 struct completion *cmp = dma_async_param; 291 292 complete(cmp); 293 } 294 295 /** 296 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. 297 * @ioat_dma: dma device to be tested 298 */ 299 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) 300 { 301 int i; 302 u8 *src; 303 u8 *dest; 304 struct dma_device *dma = &ioat_dma->dma_dev; 305 struct device *dev = &ioat_dma->pdev->dev; 306 struct dma_chan *dma_chan; 307 struct dma_async_tx_descriptor *tx; 308 dma_addr_t dma_dest, dma_src; 309 dma_cookie_t cookie; 310 int err = 0; 311 struct completion cmp; 312 unsigned long tmo; 313 unsigned long flags; 314 315 src = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL); 316 if (!src) 317 return -ENOMEM; 318 dest = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL); 319 if (!dest) { 320 kfree(src); 321 return -ENOMEM; 322 } 323 324 /* Fill in src buffer */ 325 for (i = 0; i < IOAT_TEST_SIZE; i++) 326 src[i] = (u8)i; 327 328 /* Start copy, using first DMA channel */ 329 dma_chan = container_of(dma->channels.next, struct dma_chan, 330 device_node); 331 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 332 dev_err(dev, "selftest cannot allocate chan resource\n"); 333 err = -ENODEV; 334 goto out; 335 } 336 337 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 338 if (dma_mapping_error(dev, dma_src)) { 339 dev_err(dev, "mapping src buffer failed\n"); 340 err = -ENOMEM; 341 goto free_resources; 342 } 343 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 344 if (dma_mapping_error(dev, dma_dest)) { 345 dev_err(dev, "mapping dest buffer failed\n"); 346 err = -ENOMEM; 347 goto unmap_src; 348 } 349 flags = DMA_PREP_INTERRUPT; 350 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, 351 dma_src, IOAT_TEST_SIZE, 352 flags); 353 if (!tx) { 354 dev_err(dev, "Self-test prep failed, disabling\n"); 355 err = -ENODEV; 356 goto unmap_dma; 357 } 358 359 async_tx_ack(tx); 360 init_completion(&cmp); 361 tx->callback = ioat_dma_test_callback; 362 tx->callback_param = &cmp; 363 cookie = tx->tx_submit(tx); 364 if (cookie < 0) { 365 dev_err(dev, "Self-test setup failed, disabling\n"); 366 err = -ENODEV; 367 goto unmap_dma; 368 } 369 dma->device_issue_pending(dma_chan); 370 371 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 372 373 if (tmo == 0 || 374 dma->device_tx_status(dma_chan, cookie, NULL) 375 != DMA_COMPLETE) { 376 dev_err(dev, "Self-test copy timed out, disabling\n"); 377 err = -ENODEV; 378 goto unmap_dma; 379 } 380 if (memcmp(src, dest, IOAT_TEST_SIZE)) { 381 dev_err(dev, "Self-test copy failed compare, disabling\n"); 382 err = -ENODEV; 383 goto unmap_dma; 384 } 385 386 unmap_dma: 387 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 388 unmap_src: 389 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 390 free_resources: 391 dma->device_free_chan_resources(dma_chan); 392 out: 393 kfree(src); 394 kfree(dest); 395 return err; 396 } 397 398 /** 399 * ioat_dma_setup_interrupts - setup interrupt handler 400 * @ioat_dma: ioat dma device 401 */ 402 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) 403 { 404 struct ioatdma_chan *ioat_chan; 405 struct pci_dev *pdev = ioat_dma->pdev; 406 struct device *dev = &pdev->dev; 407 struct msix_entry *msix; 408 int i, j, msixcnt; 409 int err = -EINVAL; 410 u8 intrctrl = 0; 411 412 if (!strcmp(ioat_interrupt_style, "msix")) 413 goto msix; 414 if (!strcmp(ioat_interrupt_style, "msi")) 415 goto msi; 416 if (!strcmp(ioat_interrupt_style, "intx")) 417 goto intx; 418 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); 419 goto err_no_irq; 420 421 msix: 422 /* The number of MSI-X vectors should equal the number of channels */ 423 msixcnt = ioat_dma->dma_dev.chancnt; 424 for (i = 0; i < msixcnt; i++) 425 ioat_dma->msix_entries[i].entry = i; 426 427 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); 428 if (err) 429 goto msi; 430 431 for (i = 0; i < msixcnt; i++) { 432 msix = &ioat_dma->msix_entries[i]; 433 ioat_chan = ioat_chan_by_index(ioat_dma, i); 434 err = devm_request_irq(dev, msix->vector, 435 ioat_dma_do_interrupt_msix, 0, 436 "ioat-msix", ioat_chan); 437 if (err) { 438 for (j = 0; j < i; j++) { 439 msix = &ioat_dma->msix_entries[j]; 440 ioat_chan = ioat_chan_by_index(ioat_dma, j); 441 devm_free_irq(dev, msix->vector, ioat_chan); 442 } 443 goto msi; 444 } 445 } 446 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; 447 ioat_dma->irq_mode = IOAT_MSIX; 448 goto done; 449 450 msi: 451 err = pci_enable_msi(pdev); 452 if (err) 453 goto intx; 454 455 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, 456 "ioat-msi", ioat_dma); 457 if (err) { 458 pci_disable_msi(pdev); 459 goto intx; 460 } 461 ioat_dma->irq_mode = IOAT_MSI; 462 goto done; 463 464 intx: 465 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 466 IRQF_SHARED, "ioat-intx", ioat_dma); 467 if (err) 468 goto err_no_irq; 469 470 ioat_dma->irq_mode = IOAT_INTX; 471 done: 472 if (is_bwd_ioat(pdev)) 473 ioat_intr_quirk(ioat_dma); 474 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; 475 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 476 return 0; 477 478 err_no_irq: 479 /* Disable all interrupt generation */ 480 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 481 ioat_dma->irq_mode = IOAT_NOIRQ; 482 dev_err(dev, "no usable interrupts\n"); 483 return err; 484 } 485 486 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) 487 { 488 /* Disable all interrupt generation */ 489 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 490 } 491 492 static int ioat_probe(struct ioatdma_device *ioat_dma) 493 { 494 int err = -ENODEV; 495 struct dma_device *dma = &ioat_dma->dma_dev; 496 struct pci_dev *pdev = ioat_dma->pdev; 497 struct device *dev = &pdev->dev; 498 499 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev, 500 sizeof(u64), 501 SMP_CACHE_BYTES, 502 SMP_CACHE_BYTES); 503 504 if (!ioat_dma->completion_pool) { 505 err = -ENOMEM; 506 goto err_out; 507 } 508 509 ioat_enumerate_channels(ioat_dma); 510 511 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 512 dma->dev = &pdev->dev; 513 514 if (!dma->chancnt) { 515 dev_err(dev, "channel enumeration error\n"); 516 goto err_setup_interrupts; 517 } 518 519 err = ioat_dma_setup_interrupts(ioat_dma); 520 if (err) 521 goto err_setup_interrupts; 522 523 err = ioat3_dma_self_test(ioat_dma); 524 if (err) 525 goto err_self_test; 526 527 return 0; 528 529 err_self_test: 530 ioat_disable_interrupts(ioat_dma); 531 err_setup_interrupts: 532 dma_pool_destroy(ioat_dma->completion_pool); 533 err_out: 534 return err; 535 } 536 537 static int ioat_register(struct ioatdma_device *ioat_dma) 538 { 539 int err = dma_async_device_register(&ioat_dma->dma_dev); 540 541 if (err) { 542 ioat_disable_interrupts(ioat_dma); 543 dma_pool_destroy(ioat_dma->completion_pool); 544 } 545 546 return err; 547 } 548 549 static void ioat_dma_remove(struct ioatdma_device *ioat_dma) 550 { 551 struct dma_device *dma = &ioat_dma->dma_dev; 552 553 ioat_disable_interrupts(ioat_dma); 554 555 ioat_kobject_del(ioat_dma); 556 557 dma_async_device_unregister(dma); 558 } 559 560 /** 561 * ioat_enumerate_channels - find and initialize the device's channels 562 * @ioat_dma: the ioat dma device to be enumerated 563 */ 564 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma) 565 { 566 struct ioatdma_chan *ioat_chan; 567 struct device *dev = &ioat_dma->pdev->dev; 568 struct dma_device *dma = &ioat_dma->dma_dev; 569 u8 xfercap_log; 570 int i; 571 572 INIT_LIST_HEAD(&dma->channels); 573 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); 574 dma->chancnt &= 0x1f; /* bits [4:0] valid */ 575 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) { 576 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", 577 dma->chancnt, ARRAY_SIZE(ioat_dma->idx)); 578 dma->chancnt = ARRAY_SIZE(ioat_dma->idx); 579 } 580 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); 581 xfercap_log &= 0x1f; /* bits [4:0] valid */ 582 if (xfercap_log == 0) 583 return; 584 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); 585 586 for (i = 0; i < dma->chancnt; i++) { 587 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL); 588 if (!ioat_chan) 589 break; 590 591 ioat_init_channel(ioat_dma, ioat_chan, i); 592 ioat_chan->xfercap_log = xfercap_log; 593 spin_lock_init(&ioat_chan->prep_lock); 594 if (ioat_reset_hw(ioat_chan)) { 595 i = 0; 596 break; 597 } 598 } 599 dma->chancnt = i; 600 } 601 602 /** 603 * ioat_free_chan_resources - release all the descriptors 604 * @c: the channel to be cleaned 605 */ 606 static void ioat_free_chan_resources(struct dma_chan *c) 607 { 608 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 609 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; 610 struct ioat_ring_ent *desc; 611 const int total_descs = 1 << ioat_chan->alloc_order; 612 int descs; 613 int i; 614 615 /* Before freeing channel resources first check 616 * if they have been previously allocated for this channel. 617 */ 618 if (!ioat_chan->ring) 619 return; 620 621 ioat_stop(ioat_chan); 622 623 if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) { 624 ioat_reset_hw(ioat_chan); 625 626 /* Put LTR to idle */ 627 if (ioat_dma->version >= IOAT_VER_3_4) 628 writeb(IOAT_CHAN_LTR_SWSEL_IDLE, 629 ioat_chan->reg_base + 630 IOAT_CHAN_LTR_SWSEL_OFFSET); 631 } 632 633 spin_lock_bh(&ioat_chan->cleanup_lock); 634 spin_lock_bh(&ioat_chan->prep_lock); 635 descs = ioat_ring_space(ioat_chan); 636 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); 637 for (i = 0; i < descs; i++) { 638 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); 639 ioat_free_ring_ent(desc, c); 640 } 641 642 if (descs < total_descs) 643 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", 644 total_descs - descs); 645 646 for (i = 0; i < total_descs - descs; i++) { 647 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); 648 dump_desc_dbg(ioat_chan, desc); 649 ioat_free_ring_ent(desc, c); 650 } 651 652 for (i = 0; i < ioat_chan->desc_chunks; i++) { 653 dma_free_coherent(to_dev(ioat_chan), IOAT_CHUNK_SIZE, 654 ioat_chan->descs[i].virt, 655 ioat_chan->descs[i].hw); 656 ioat_chan->descs[i].virt = NULL; 657 ioat_chan->descs[i].hw = 0; 658 } 659 ioat_chan->desc_chunks = 0; 660 661 kfree(ioat_chan->ring); 662 ioat_chan->ring = NULL; 663 ioat_chan->alloc_order = 0; 664 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion, 665 ioat_chan->completion_dma); 666 spin_unlock_bh(&ioat_chan->prep_lock); 667 spin_unlock_bh(&ioat_chan->cleanup_lock); 668 669 ioat_chan->last_completion = 0; 670 ioat_chan->completion_dma = 0; 671 ioat_chan->dmacount = 0; 672 } 673 674 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring 675 * @chan: channel to be initialized 676 */ 677 static int ioat_alloc_chan_resources(struct dma_chan *c) 678 { 679 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 680 struct ioat_ring_ent **ring; 681 u64 status; 682 int order; 683 int i = 0; 684 u32 chanerr; 685 686 /* have we already been set up? */ 687 if (ioat_chan->ring) 688 return 1 << ioat_chan->alloc_order; 689 690 /* Setup register to interrupt and write completion status on error */ 691 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); 692 693 /* allocate a completion writeback area */ 694 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 695 ioat_chan->completion = 696 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool, 697 GFP_NOWAIT, &ioat_chan->completion_dma); 698 if (!ioat_chan->completion) 699 return -ENOMEM; 700 701 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, 702 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); 703 writel(((u64)ioat_chan->completion_dma) >> 32, 704 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 705 706 order = IOAT_MAX_ORDER; 707 ring = ioat_alloc_ring(c, order, GFP_NOWAIT); 708 if (!ring) 709 return -ENOMEM; 710 711 spin_lock_bh(&ioat_chan->cleanup_lock); 712 spin_lock_bh(&ioat_chan->prep_lock); 713 ioat_chan->ring = ring; 714 ioat_chan->head = 0; 715 ioat_chan->issued = 0; 716 ioat_chan->tail = 0; 717 ioat_chan->alloc_order = order; 718 set_bit(IOAT_RUN, &ioat_chan->state); 719 spin_unlock_bh(&ioat_chan->prep_lock); 720 spin_unlock_bh(&ioat_chan->cleanup_lock); 721 722 /* Setting up LTR values for 3.4 or later */ 723 if (ioat_chan->ioat_dma->version >= IOAT_VER_3_4) { 724 u32 lat_val; 725 726 lat_val = IOAT_CHAN_LTR_ACTIVE_SNVAL | 727 IOAT_CHAN_LTR_ACTIVE_SNLATSCALE | 728 IOAT_CHAN_LTR_ACTIVE_SNREQMNT; 729 writel(lat_val, ioat_chan->reg_base + 730 IOAT_CHAN_LTR_ACTIVE_OFFSET); 731 732 lat_val = IOAT_CHAN_LTR_IDLE_SNVAL | 733 IOAT_CHAN_LTR_IDLE_SNLATSCALE | 734 IOAT_CHAN_LTR_IDLE_SNREQMNT; 735 writel(lat_val, ioat_chan->reg_base + 736 IOAT_CHAN_LTR_IDLE_OFFSET); 737 738 /* Select to active */ 739 writeb(IOAT_CHAN_LTR_SWSEL_ACTIVE, 740 ioat_chan->reg_base + 741 IOAT_CHAN_LTR_SWSEL_OFFSET); 742 } 743 744 ioat_start_null_desc(ioat_chan); 745 746 /* check that we got off the ground */ 747 do { 748 udelay(1); 749 status = ioat_chansts(ioat_chan); 750 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); 751 752 if (is_ioat_active(status) || is_ioat_idle(status)) 753 return 1 << ioat_chan->alloc_order; 754 755 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 756 757 dev_WARN(to_dev(ioat_chan), 758 "failed to start channel chanerr: %#x\n", chanerr); 759 ioat_free_chan_resources(c); 760 return -EFAULT; 761 } 762 763 /* common channel initialization */ 764 static void 765 ioat_init_channel(struct ioatdma_device *ioat_dma, 766 struct ioatdma_chan *ioat_chan, int idx) 767 { 768 struct dma_device *dma = &ioat_dma->dma_dev; 769 770 ioat_chan->ioat_dma = ioat_dma; 771 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); 772 spin_lock_init(&ioat_chan->cleanup_lock); 773 ioat_chan->dma_chan.device = dma; 774 dma_cookie_init(&ioat_chan->dma_chan); 775 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); 776 ioat_dma->idx[idx] = ioat_chan; 777 timer_setup(&ioat_chan->timer, ioat_timer_event, 0); 778 tasklet_setup(&ioat_chan->cleanup_task, ioat_cleanup_event); 779 } 780 781 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ 782 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) 783 { 784 int i, src_idx; 785 struct page *dest; 786 struct page *xor_srcs[IOAT_NUM_SRC_TEST]; 787 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; 788 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; 789 dma_addr_t dest_dma; 790 struct dma_async_tx_descriptor *tx; 791 struct dma_chan *dma_chan; 792 dma_cookie_t cookie; 793 u8 cmp_byte = 0; 794 u32 cmp_word; 795 u32 xor_val_result; 796 int err = 0; 797 struct completion cmp; 798 unsigned long tmo; 799 struct device *dev = &ioat_dma->pdev->dev; 800 struct dma_device *dma = &ioat_dma->dma_dev; 801 u8 op = 0; 802 803 dev_dbg(dev, "%s\n", __func__); 804 805 if (!dma_has_cap(DMA_XOR, dma->cap_mask)) 806 return 0; 807 808 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 809 xor_srcs[src_idx] = alloc_page(GFP_KERNEL); 810 if (!xor_srcs[src_idx]) { 811 while (src_idx--) 812 __free_page(xor_srcs[src_idx]); 813 return -ENOMEM; 814 } 815 } 816 817 dest = alloc_page(GFP_KERNEL); 818 if (!dest) { 819 while (src_idx--) 820 __free_page(xor_srcs[src_idx]); 821 return -ENOMEM; 822 } 823 824 /* Fill in src buffers */ 825 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 826 u8 *ptr = page_address(xor_srcs[src_idx]); 827 828 for (i = 0; i < PAGE_SIZE; i++) 829 ptr[i] = (1 << src_idx); 830 } 831 832 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) 833 cmp_byte ^= (u8) (1 << src_idx); 834 835 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | 836 (cmp_byte << 8) | cmp_byte; 837 838 memset(page_address(dest), 0, PAGE_SIZE); 839 840 dma_chan = container_of(dma->channels.next, struct dma_chan, 841 device_node); 842 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 843 err = -ENODEV; 844 goto out; 845 } 846 847 /* test xor */ 848 op = IOAT_OP_XOR; 849 850 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); 851 if (dma_mapping_error(dev, dest_dma)) { 852 err = -ENOMEM; 853 goto free_resources; 854 } 855 856 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { 857 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, 858 DMA_TO_DEVICE); 859 if (dma_mapping_error(dev, dma_srcs[i])) { 860 err = -ENOMEM; 861 goto dma_unmap; 862 } 863 } 864 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, 865 IOAT_NUM_SRC_TEST, PAGE_SIZE, 866 DMA_PREP_INTERRUPT); 867 868 if (!tx) { 869 dev_err(dev, "Self-test xor prep failed\n"); 870 err = -ENODEV; 871 goto dma_unmap; 872 } 873 874 async_tx_ack(tx); 875 init_completion(&cmp); 876 tx->callback = ioat_dma_test_callback; 877 tx->callback_param = &cmp; 878 cookie = tx->tx_submit(tx); 879 if (cookie < 0) { 880 dev_err(dev, "Self-test xor setup failed\n"); 881 err = -ENODEV; 882 goto dma_unmap; 883 } 884 dma->device_issue_pending(dma_chan); 885 886 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 887 888 if (tmo == 0 || 889 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 890 dev_err(dev, "Self-test xor timed out\n"); 891 err = -ENODEV; 892 goto dma_unmap; 893 } 894 895 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 896 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 897 898 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 899 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { 900 u32 *ptr = page_address(dest); 901 902 if (ptr[i] != cmp_word) { 903 dev_err(dev, "Self-test xor failed compare\n"); 904 err = -ENODEV; 905 goto free_resources; 906 } 907 } 908 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 909 910 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 911 912 /* skip validate if the capability is not present */ 913 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) 914 goto free_resources; 915 916 op = IOAT_OP_XOR_VAL; 917 918 /* validate the sources with the destintation page */ 919 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 920 xor_val_srcs[i] = xor_srcs[i]; 921 xor_val_srcs[i] = dest; 922 923 xor_val_result = 1; 924 925 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 926 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 927 DMA_TO_DEVICE); 928 if (dma_mapping_error(dev, dma_srcs[i])) { 929 err = -ENOMEM; 930 goto dma_unmap; 931 } 932 } 933 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 934 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 935 &xor_val_result, DMA_PREP_INTERRUPT); 936 if (!tx) { 937 dev_err(dev, "Self-test zero prep failed\n"); 938 err = -ENODEV; 939 goto dma_unmap; 940 } 941 942 async_tx_ack(tx); 943 init_completion(&cmp); 944 tx->callback = ioat_dma_test_callback; 945 tx->callback_param = &cmp; 946 cookie = tx->tx_submit(tx); 947 if (cookie < 0) { 948 dev_err(dev, "Self-test zero setup failed\n"); 949 err = -ENODEV; 950 goto dma_unmap; 951 } 952 dma->device_issue_pending(dma_chan); 953 954 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 955 956 if (tmo == 0 || 957 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 958 dev_err(dev, "Self-test validate timed out\n"); 959 err = -ENODEV; 960 goto dma_unmap; 961 } 962 963 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 964 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 965 966 if (xor_val_result != 0) { 967 dev_err(dev, "Self-test validate failed compare\n"); 968 err = -ENODEV; 969 goto free_resources; 970 } 971 972 memset(page_address(dest), 0, PAGE_SIZE); 973 974 /* test for non-zero parity sum */ 975 op = IOAT_OP_XOR_VAL; 976 977 xor_val_result = 0; 978 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 979 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 980 DMA_TO_DEVICE); 981 if (dma_mapping_error(dev, dma_srcs[i])) { 982 err = -ENOMEM; 983 goto dma_unmap; 984 } 985 } 986 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 987 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 988 &xor_val_result, DMA_PREP_INTERRUPT); 989 if (!tx) { 990 dev_err(dev, "Self-test 2nd zero prep failed\n"); 991 err = -ENODEV; 992 goto dma_unmap; 993 } 994 995 async_tx_ack(tx); 996 init_completion(&cmp); 997 tx->callback = ioat_dma_test_callback; 998 tx->callback_param = &cmp; 999 cookie = tx->tx_submit(tx); 1000 if (cookie < 0) { 1001 dev_err(dev, "Self-test 2nd zero setup failed\n"); 1002 err = -ENODEV; 1003 goto dma_unmap; 1004 } 1005 dma->device_issue_pending(dma_chan); 1006 1007 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 1008 1009 if (tmo == 0 || 1010 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 1011 dev_err(dev, "Self-test 2nd validate timed out\n"); 1012 err = -ENODEV; 1013 goto dma_unmap; 1014 } 1015 1016 if (xor_val_result != SUM_CHECK_P_RESULT) { 1017 dev_err(dev, "Self-test validate failed compare\n"); 1018 err = -ENODEV; 1019 goto dma_unmap; 1020 } 1021 1022 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 1023 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 1024 1025 goto free_resources; 1026 dma_unmap: 1027 if (op == IOAT_OP_XOR) { 1028 while (--i >= 0) 1029 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1030 DMA_TO_DEVICE); 1031 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 1032 } else if (op == IOAT_OP_XOR_VAL) { 1033 while (--i >= 0) 1034 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1035 DMA_TO_DEVICE); 1036 } 1037 free_resources: 1038 dma->device_free_chan_resources(dma_chan); 1039 out: 1040 src_idx = IOAT_NUM_SRC_TEST; 1041 while (src_idx--) 1042 __free_page(xor_srcs[src_idx]); 1043 __free_page(dest); 1044 return err; 1045 } 1046 1047 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) 1048 { 1049 int rc; 1050 1051 rc = ioat_dma_self_test(ioat_dma); 1052 if (rc) 1053 return rc; 1054 1055 rc = ioat_xor_val_self_test(ioat_dma); 1056 1057 return rc; 1058 } 1059 1060 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma) 1061 { 1062 struct dma_device *dma; 1063 struct dma_chan *c; 1064 struct ioatdma_chan *ioat_chan; 1065 u32 errmask; 1066 1067 dma = &ioat_dma->dma_dev; 1068 1069 /* 1070 * if we have descriptor write back error status, we mask the 1071 * error interrupts 1072 */ 1073 if (ioat_dma->cap & IOAT_CAP_DWBES) { 1074 list_for_each_entry(c, &dma->channels, device_node) { 1075 ioat_chan = to_ioat_chan(c); 1076 errmask = readl(ioat_chan->reg_base + 1077 IOAT_CHANERR_MASK_OFFSET); 1078 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | 1079 IOAT_CHANERR_XOR_Q_ERR; 1080 writel(errmask, ioat_chan->reg_base + 1081 IOAT_CHANERR_MASK_OFFSET); 1082 } 1083 } 1084 } 1085 1086 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 1087 { 1088 struct pci_dev *pdev = ioat_dma->pdev; 1089 int dca_en = system_has_dca_enabled(pdev); 1090 struct dma_device *dma; 1091 struct dma_chan *c; 1092 struct ioatdma_chan *ioat_chan; 1093 int err; 1094 u16 val16; 1095 1096 dma = &ioat_dma->dma_dev; 1097 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; 1098 dma->device_issue_pending = ioat_issue_pending; 1099 dma->device_alloc_chan_resources = ioat_alloc_chan_resources; 1100 dma->device_free_chan_resources = ioat_free_chan_resources; 1101 1102 dma_cap_set(DMA_INTERRUPT, dma->cap_mask); 1103 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; 1104 1105 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); 1106 1107 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) 1108 ioat_dma->cap &= 1109 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); 1110 1111 /* dca is incompatible with raid operations */ 1112 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) 1113 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); 1114 1115 if (ioat_dma->cap & IOAT_CAP_XOR) { 1116 dma->max_xor = 8; 1117 1118 dma_cap_set(DMA_XOR, dma->cap_mask); 1119 dma->device_prep_dma_xor = ioat_prep_xor; 1120 1121 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1122 dma->device_prep_dma_xor_val = ioat_prep_xor_val; 1123 } 1124 1125 if (ioat_dma->cap & IOAT_CAP_PQ) { 1126 1127 dma->device_prep_dma_pq = ioat_prep_pq; 1128 dma->device_prep_dma_pq_val = ioat_prep_pq_val; 1129 dma_cap_set(DMA_PQ, dma->cap_mask); 1130 dma_cap_set(DMA_PQ_VAL, dma->cap_mask); 1131 1132 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1133 dma_set_maxpq(dma, 16, 0); 1134 else 1135 dma_set_maxpq(dma, 8, 0); 1136 1137 if (!(ioat_dma->cap & IOAT_CAP_XOR)) { 1138 dma->device_prep_dma_xor = ioat_prep_pqxor; 1139 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; 1140 dma_cap_set(DMA_XOR, dma->cap_mask); 1141 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1142 1143 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1144 dma->max_xor = 16; 1145 else 1146 dma->max_xor = 8; 1147 } 1148 } 1149 1150 dma->device_tx_status = ioat_tx_status; 1151 1152 /* starting with CB3.3 super extended descriptors are supported */ 1153 if (ioat_dma->cap & IOAT_CAP_RAID16SS) { 1154 char pool_name[14]; 1155 int i; 1156 1157 for (i = 0; i < MAX_SED_POOLS; i++) { 1158 snprintf(pool_name, 14, "ioat_hw%d_sed", i); 1159 1160 /* allocate SED DMA pool */ 1161 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, 1162 &pdev->dev, 1163 SED_SIZE * (i + 1), 64, 0); 1164 if (!ioat_dma->sed_hw_pool[i]) 1165 return -ENOMEM; 1166 1167 } 1168 } 1169 1170 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) 1171 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1172 1173 err = ioat_probe(ioat_dma); 1174 if (err) 1175 return err; 1176 1177 list_for_each_entry(c, &dma->channels, device_node) { 1178 ioat_chan = to_ioat_chan(c); 1179 writel(IOAT_DMA_DCA_ANY_CPU, 1180 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 1181 } 1182 1183 err = ioat_register(ioat_dma); 1184 if (err) 1185 return err; 1186 1187 ioat_kobject_add(ioat_dma, &ioat_ktype); 1188 1189 if (dca) 1190 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); 1191 1192 /* disable relaxed ordering */ 1193 err = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &val16); 1194 if (err) 1195 return pcibios_err_to_errno(err); 1196 1197 /* clear relaxed ordering enable */ 1198 val16 &= ~PCI_EXP_DEVCTL_RELAX_EN; 1199 err = pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, val16); 1200 if (err) 1201 return pcibios_err_to_errno(err); 1202 1203 if (ioat_dma->cap & IOAT_CAP_DPS) 1204 writeb(ioat_pending_level + 1, 1205 ioat_dma->reg_base + IOAT_PREFETCH_LIMIT_OFFSET); 1206 1207 return 0; 1208 } 1209 1210 static void ioat_shutdown(struct pci_dev *pdev) 1211 { 1212 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1213 struct ioatdma_chan *ioat_chan; 1214 int i; 1215 1216 if (!ioat_dma) 1217 return; 1218 1219 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1220 ioat_chan = ioat_dma->idx[i]; 1221 if (!ioat_chan) 1222 continue; 1223 1224 spin_lock_bh(&ioat_chan->prep_lock); 1225 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1226 spin_unlock_bh(&ioat_chan->prep_lock); 1227 /* 1228 * Synchronization rule for del_timer_sync(): 1229 * - The caller must not hold locks which would prevent 1230 * completion of the timer's handler. 1231 * So prep_lock cannot be held before calling it. 1232 */ 1233 del_timer_sync(&ioat_chan->timer); 1234 1235 /* this should quiesce then reset */ 1236 ioat_reset_hw(ioat_chan); 1237 } 1238 1239 ioat_disable_interrupts(ioat_dma); 1240 } 1241 1242 static void ioat_resume(struct ioatdma_device *ioat_dma) 1243 { 1244 struct ioatdma_chan *ioat_chan; 1245 u32 chanerr; 1246 int i; 1247 1248 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1249 ioat_chan = ioat_dma->idx[i]; 1250 if (!ioat_chan) 1251 continue; 1252 1253 spin_lock_bh(&ioat_chan->prep_lock); 1254 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1255 spin_unlock_bh(&ioat_chan->prep_lock); 1256 1257 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1258 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1259 1260 /* no need to reset as shutdown already did that */ 1261 } 1262 } 1263 1264 #define DRV_NAME "ioatdma" 1265 1266 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev, 1267 pci_channel_state_t error) 1268 { 1269 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error); 1270 1271 /* quiesce and block I/O */ 1272 ioat_shutdown(pdev); 1273 1274 return PCI_ERS_RESULT_NEED_RESET; 1275 } 1276 1277 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev) 1278 { 1279 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 1280 1281 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME); 1282 1283 if (pci_enable_device_mem(pdev) < 0) { 1284 dev_err(&pdev->dev, 1285 "Failed to enable PCIe device after reset.\n"); 1286 result = PCI_ERS_RESULT_DISCONNECT; 1287 } else { 1288 pci_set_master(pdev); 1289 pci_restore_state(pdev); 1290 pci_save_state(pdev); 1291 pci_wake_from_d3(pdev, false); 1292 } 1293 1294 return result; 1295 } 1296 1297 static void ioat_pcie_error_resume(struct pci_dev *pdev) 1298 { 1299 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1300 1301 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME); 1302 1303 /* initialize and bring everything back */ 1304 ioat_resume(ioat_dma); 1305 } 1306 1307 static const struct pci_error_handlers ioat_err_handler = { 1308 .error_detected = ioat_pcie_error_detected, 1309 .slot_reset = ioat_pcie_error_slot_reset, 1310 .resume = ioat_pcie_error_resume, 1311 }; 1312 1313 static struct pci_driver ioat_pci_driver = { 1314 .name = DRV_NAME, 1315 .id_table = ioat_pci_tbl, 1316 .probe = ioat_pci_probe, 1317 .remove = ioat_remove, 1318 .shutdown = ioat_shutdown, 1319 .err_handler = &ioat_err_handler, 1320 }; 1321 1322 static void release_ioatdma(struct dma_device *device) 1323 { 1324 struct ioatdma_device *d = to_ioatdma_device(device); 1325 int i; 1326 1327 for (i = 0; i < IOAT_MAX_CHANS; i++) 1328 kfree(d->idx[i]); 1329 1330 dma_pool_destroy(d->completion_pool); 1331 kfree(d); 1332 } 1333 1334 static struct ioatdma_device * 1335 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) 1336 { 1337 struct ioatdma_device *d = kzalloc(sizeof(*d), GFP_KERNEL); 1338 1339 if (!d) 1340 return NULL; 1341 d->pdev = pdev; 1342 d->reg_base = iobase; 1343 d->dma_dev.device_release = release_ioatdma; 1344 return d; 1345 } 1346 1347 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1348 { 1349 void __iomem * const *iomap; 1350 struct device *dev = &pdev->dev; 1351 struct ioatdma_device *device; 1352 int err; 1353 1354 err = pcim_enable_device(pdev); 1355 if (err) 1356 return err; 1357 1358 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); 1359 if (err) 1360 return err; 1361 iomap = pcim_iomap_table(pdev); 1362 if (!iomap) 1363 return -ENOMEM; 1364 1365 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1366 if (err) 1367 return err; 1368 1369 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); 1370 if (!device) 1371 return -ENOMEM; 1372 pci_set_master(pdev); 1373 pci_set_drvdata(pdev, device); 1374 1375 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1376 if (device->version >= IOAT_VER_3_4) 1377 ioat_dca_enabled = 0; 1378 if (device->version >= IOAT_VER_3_0) { 1379 if (is_skx_ioat(pdev)) 1380 device->version = IOAT_VER_3_2; 1381 err = ioat3_dma_probe(device, ioat_dca_enabled); 1382 } else 1383 return -ENODEV; 1384 1385 if (err) { 1386 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); 1387 return -ENODEV; 1388 } 1389 1390 return 0; 1391 } 1392 1393 static void ioat_remove(struct pci_dev *pdev) 1394 { 1395 struct ioatdma_device *device = pci_get_drvdata(pdev); 1396 1397 if (!device) 1398 return; 1399 1400 ioat_shutdown(pdev); 1401 1402 dev_err(&pdev->dev, "Removing dma and dca services\n"); 1403 if (device->dca) { 1404 unregister_dca_provider(device->dca, &pdev->dev); 1405 free_dca_provider(device->dca); 1406 device->dca = NULL; 1407 } 1408 1409 ioat_dma_remove(device); 1410 } 1411 1412 static int __init ioat_init_module(void) 1413 { 1414 int err = -ENOMEM; 1415 1416 pr_info("%s: Intel(R) QuickData Technology Driver %s\n", 1417 DRV_NAME, IOAT_DMA_VERSION); 1418 1419 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), 1420 0, SLAB_HWCACHE_ALIGN, NULL); 1421 if (!ioat_cache) 1422 return -ENOMEM; 1423 1424 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); 1425 if (!ioat_sed_cache) 1426 goto err_ioat_cache; 1427 1428 err = pci_register_driver(&ioat_pci_driver); 1429 if (err) 1430 goto err_ioat3_cache; 1431 1432 return 0; 1433 1434 err_ioat3_cache: 1435 kmem_cache_destroy(ioat_sed_cache); 1436 1437 err_ioat_cache: 1438 kmem_cache_destroy(ioat_cache); 1439 1440 return err; 1441 } 1442 module_init(ioat_init_module); 1443 1444 static void __exit ioat_exit_module(void) 1445 { 1446 pci_unregister_driver(&ioat_pci_driver); 1447 kmem_cache_destroy(ioat_cache); 1448 } 1449 module_exit(ioat_exit_module); 1450