1 /* 2 * Intel I/OAT DMA Linux driver 3 * Copyright(c) 2004 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 */ 18 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/slab.h> 22 #include <linux/pci.h> 23 #include <linux/interrupt.h> 24 #include <linux/dmaengine.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/workqueue.h> 28 #include <linux/prefetch.h> 29 #include <linux/dca.h> 30 #include <linux/aer.h> 31 #include <linux/sizes.h> 32 #include "dma.h" 33 #include "registers.h" 34 #include "hw.h" 35 36 #include "../dmaengine.h" 37 38 MODULE_VERSION(IOAT_DMA_VERSION); 39 MODULE_LICENSE("Dual BSD/GPL"); 40 MODULE_AUTHOR("Intel Corporation"); 41 42 static const struct pci_device_id ioat_pci_tbl[] = { 43 /* I/OAT v3 platforms */ 44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, 45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, 46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, 47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, 48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, 49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, 50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, 51 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, 52 53 /* I/OAT v3.2 platforms */ 54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, 55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, 56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, 57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, 58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, 59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, 60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, 61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, 62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, 63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, 64 65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, 66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, 67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, 68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, 69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, 70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, 71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, 72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, 73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, 74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, 75 76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, 77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, 78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, 79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, 80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, 81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, 82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, 83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, 84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, 85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, 86 87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, 88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, 89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, 90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, 91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, 92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, 93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, 94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, 95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, 96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, 97 98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) }, 99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) }, 100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) }, 101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) }, 102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) }, 103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) }, 104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) }, 105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) }, 106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) }, 107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) }, 108 109 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) }, 110 111 /* I/OAT v3.3 platforms */ 112 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, 113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, 114 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, 115 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, 116 117 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, 118 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, 119 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, 120 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, 121 122 { 0, } 123 }; 124 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); 125 126 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 127 static void ioat_remove(struct pci_dev *pdev); 128 static void 129 ioat_init_channel(struct ioatdma_device *ioat_dma, 130 struct ioatdma_chan *ioat_chan, int idx); 131 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma); 132 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma); 133 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); 134 135 static int ioat_dca_enabled = 1; 136 module_param(ioat_dca_enabled, int, 0644); 137 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); 138 int ioat_pending_level = 4; 139 module_param(ioat_pending_level, int, 0644); 140 MODULE_PARM_DESC(ioat_pending_level, 141 "high-water mark for pushing ioat descriptors (default: 4)"); 142 static char ioat_interrupt_style[32] = "msix"; 143 module_param_string(ioat_interrupt_style, ioat_interrupt_style, 144 sizeof(ioat_interrupt_style), 0644); 145 MODULE_PARM_DESC(ioat_interrupt_style, 146 "set ioat interrupt style: msix (default), msi, intx"); 147 148 struct kmem_cache *ioat_cache; 149 struct kmem_cache *ioat_sed_cache; 150 151 static bool is_jf_ioat(struct pci_dev *pdev) 152 { 153 switch (pdev->device) { 154 case PCI_DEVICE_ID_INTEL_IOAT_JSF0: 155 case PCI_DEVICE_ID_INTEL_IOAT_JSF1: 156 case PCI_DEVICE_ID_INTEL_IOAT_JSF2: 157 case PCI_DEVICE_ID_INTEL_IOAT_JSF3: 158 case PCI_DEVICE_ID_INTEL_IOAT_JSF4: 159 case PCI_DEVICE_ID_INTEL_IOAT_JSF5: 160 case PCI_DEVICE_ID_INTEL_IOAT_JSF6: 161 case PCI_DEVICE_ID_INTEL_IOAT_JSF7: 162 case PCI_DEVICE_ID_INTEL_IOAT_JSF8: 163 case PCI_DEVICE_ID_INTEL_IOAT_JSF9: 164 return true; 165 default: 166 return false; 167 } 168 } 169 170 static bool is_snb_ioat(struct pci_dev *pdev) 171 { 172 switch (pdev->device) { 173 case PCI_DEVICE_ID_INTEL_IOAT_SNB0: 174 case PCI_DEVICE_ID_INTEL_IOAT_SNB1: 175 case PCI_DEVICE_ID_INTEL_IOAT_SNB2: 176 case PCI_DEVICE_ID_INTEL_IOAT_SNB3: 177 case PCI_DEVICE_ID_INTEL_IOAT_SNB4: 178 case PCI_DEVICE_ID_INTEL_IOAT_SNB5: 179 case PCI_DEVICE_ID_INTEL_IOAT_SNB6: 180 case PCI_DEVICE_ID_INTEL_IOAT_SNB7: 181 case PCI_DEVICE_ID_INTEL_IOAT_SNB8: 182 case PCI_DEVICE_ID_INTEL_IOAT_SNB9: 183 return true; 184 default: 185 return false; 186 } 187 } 188 189 static bool is_ivb_ioat(struct pci_dev *pdev) 190 { 191 switch (pdev->device) { 192 case PCI_DEVICE_ID_INTEL_IOAT_IVB0: 193 case PCI_DEVICE_ID_INTEL_IOAT_IVB1: 194 case PCI_DEVICE_ID_INTEL_IOAT_IVB2: 195 case PCI_DEVICE_ID_INTEL_IOAT_IVB3: 196 case PCI_DEVICE_ID_INTEL_IOAT_IVB4: 197 case PCI_DEVICE_ID_INTEL_IOAT_IVB5: 198 case PCI_DEVICE_ID_INTEL_IOAT_IVB6: 199 case PCI_DEVICE_ID_INTEL_IOAT_IVB7: 200 case PCI_DEVICE_ID_INTEL_IOAT_IVB8: 201 case PCI_DEVICE_ID_INTEL_IOAT_IVB9: 202 return true; 203 default: 204 return false; 205 } 206 207 } 208 209 static bool is_hsw_ioat(struct pci_dev *pdev) 210 { 211 switch (pdev->device) { 212 case PCI_DEVICE_ID_INTEL_IOAT_HSW0: 213 case PCI_DEVICE_ID_INTEL_IOAT_HSW1: 214 case PCI_DEVICE_ID_INTEL_IOAT_HSW2: 215 case PCI_DEVICE_ID_INTEL_IOAT_HSW3: 216 case PCI_DEVICE_ID_INTEL_IOAT_HSW4: 217 case PCI_DEVICE_ID_INTEL_IOAT_HSW5: 218 case PCI_DEVICE_ID_INTEL_IOAT_HSW6: 219 case PCI_DEVICE_ID_INTEL_IOAT_HSW7: 220 case PCI_DEVICE_ID_INTEL_IOAT_HSW8: 221 case PCI_DEVICE_ID_INTEL_IOAT_HSW9: 222 return true; 223 default: 224 return false; 225 } 226 227 } 228 229 static bool is_bdx_ioat(struct pci_dev *pdev) 230 { 231 switch (pdev->device) { 232 case PCI_DEVICE_ID_INTEL_IOAT_BDX0: 233 case PCI_DEVICE_ID_INTEL_IOAT_BDX1: 234 case PCI_DEVICE_ID_INTEL_IOAT_BDX2: 235 case PCI_DEVICE_ID_INTEL_IOAT_BDX3: 236 case PCI_DEVICE_ID_INTEL_IOAT_BDX4: 237 case PCI_DEVICE_ID_INTEL_IOAT_BDX5: 238 case PCI_DEVICE_ID_INTEL_IOAT_BDX6: 239 case PCI_DEVICE_ID_INTEL_IOAT_BDX7: 240 case PCI_DEVICE_ID_INTEL_IOAT_BDX8: 241 case PCI_DEVICE_ID_INTEL_IOAT_BDX9: 242 return true; 243 default: 244 return false; 245 } 246 } 247 248 static inline bool is_skx_ioat(struct pci_dev *pdev) 249 { 250 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false; 251 } 252 253 static bool is_xeon_cb32(struct pci_dev *pdev) 254 { 255 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || 256 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev); 257 } 258 259 bool is_bwd_ioat(struct pci_dev *pdev) 260 { 261 switch (pdev->device) { 262 case PCI_DEVICE_ID_INTEL_IOAT_BWD0: 263 case PCI_DEVICE_ID_INTEL_IOAT_BWD1: 264 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 265 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 266 /* even though not Atom, BDX-DE has same DMA silicon */ 267 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 268 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 269 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 270 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 271 return true; 272 default: 273 return false; 274 } 275 } 276 277 static bool is_bwd_noraid(struct pci_dev *pdev) 278 { 279 switch (pdev->device) { 280 case PCI_DEVICE_ID_INTEL_IOAT_BWD2: 281 case PCI_DEVICE_ID_INTEL_IOAT_BWD3: 282 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: 283 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: 284 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: 285 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: 286 return true; 287 default: 288 return false; 289 } 290 291 } 292 293 /* 294 * Perform a IOAT transaction to verify the HW works. 295 */ 296 #define IOAT_TEST_SIZE 2000 297 298 static void ioat_dma_test_callback(void *dma_async_param) 299 { 300 struct completion *cmp = dma_async_param; 301 302 complete(cmp); 303 } 304 305 /** 306 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. 307 * @ioat_dma: dma device to be tested 308 */ 309 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) 310 { 311 int i; 312 u8 *src; 313 u8 *dest; 314 struct dma_device *dma = &ioat_dma->dma_dev; 315 struct device *dev = &ioat_dma->pdev->dev; 316 struct dma_chan *dma_chan; 317 struct dma_async_tx_descriptor *tx; 318 dma_addr_t dma_dest, dma_src; 319 dma_cookie_t cookie; 320 int err = 0; 321 struct completion cmp; 322 unsigned long tmo; 323 unsigned long flags; 324 325 src = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL); 326 if (!src) 327 return -ENOMEM; 328 dest = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL); 329 if (!dest) { 330 kfree(src); 331 return -ENOMEM; 332 } 333 334 /* Fill in src buffer */ 335 for (i = 0; i < IOAT_TEST_SIZE; i++) 336 src[i] = (u8)i; 337 338 /* Start copy, using first DMA channel */ 339 dma_chan = container_of(dma->channels.next, struct dma_chan, 340 device_node); 341 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 342 dev_err(dev, "selftest cannot allocate chan resource\n"); 343 err = -ENODEV; 344 goto out; 345 } 346 347 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 348 if (dma_mapping_error(dev, dma_src)) { 349 dev_err(dev, "mapping src buffer failed\n"); 350 err = -ENOMEM; 351 goto free_resources; 352 } 353 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 354 if (dma_mapping_error(dev, dma_dest)) { 355 dev_err(dev, "mapping dest buffer failed\n"); 356 err = -ENOMEM; 357 goto unmap_src; 358 } 359 flags = DMA_PREP_INTERRUPT; 360 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, 361 dma_src, IOAT_TEST_SIZE, 362 flags); 363 if (!tx) { 364 dev_err(dev, "Self-test prep failed, disabling\n"); 365 err = -ENODEV; 366 goto unmap_dma; 367 } 368 369 async_tx_ack(tx); 370 init_completion(&cmp); 371 tx->callback = ioat_dma_test_callback; 372 tx->callback_param = &cmp; 373 cookie = tx->tx_submit(tx); 374 if (cookie < 0) { 375 dev_err(dev, "Self-test setup failed, disabling\n"); 376 err = -ENODEV; 377 goto unmap_dma; 378 } 379 dma->device_issue_pending(dma_chan); 380 381 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 382 383 if (tmo == 0 || 384 dma->device_tx_status(dma_chan, cookie, NULL) 385 != DMA_COMPLETE) { 386 dev_err(dev, "Self-test copy timed out, disabling\n"); 387 err = -ENODEV; 388 goto unmap_dma; 389 } 390 if (memcmp(src, dest, IOAT_TEST_SIZE)) { 391 dev_err(dev, "Self-test copy failed compare, disabling\n"); 392 err = -ENODEV; 393 goto unmap_dma; 394 } 395 396 unmap_dma: 397 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); 398 unmap_src: 399 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); 400 free_resources: 401 dma->device_free_chan_resources(dma_chan); 402 out: 403 kfree(src); 404 kfree(dest); 405 return err; 406 } 407 408 /** 409 * ioat_dma_setup_interrupts - setup interrupt handler 410 * @ioat_dma: ioat dma device 411 */ 412 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) 413 { 414 struct ioatdma_chan *ioat_chan; 415 struct pci_dev *pdev = ioat_dma->pdev; 416 struct device *dev = &pdev->dev; 417 struct msix_entry *msix; 418 int i, j, msixcnt; 419 int err = -EINVAL; 420 u8 intrctrl = 0; 421 422 if (!strcmp(ioat_interrupt_style, "msix")) 423 goto msix; 424 if (!strcmp(ioat_interrupt_style, "msi")) 425 goto msi; 426 if (!strcmp(ioat_interrupt_style, "intx")) 427 goto intx; 428 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); 429 goto err_no_irq; 430 431 msix: 432 /* The number of MSI-X vectors should equal the number of channels */ 433 msixcnt = ioat_dma->dma_dev.chancnt; 434 for (i = 0; i < msixcnt; i++) 435 ioat_dma->msix_entries[i].entry = i; 436 437 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); 438 if (err) 439 goto msi; 440 441 for (i = 0; i < msixcnt; i++) { 442 msix = &ioat_dma->msix_entries[i]; 443 ioat_chan = ioat_chan_by_index(ioat_dma, i); 444 err = devm_request_irq(dev, msix->vector, 445 ioat_dma_do_interrupt_msix, 0, 446 "ioat-msix", ioat_chan); 447 if (err) { 448 for (j = 0; j < i; j++) { 449 msix = &ioat_dma->msix_entries[j]; 450 ioat_chan = ioat_chan_by_index(ioat_dma, j); 451 devm_free_irq(dev, msix->vector, ioat_chan); 452 } 453 goto msi; 454 } 455 } 456 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; 457 ioat_dma->irq_mode = IOAT_MSIX; 458 goto done; 459 460 msi: 461 err = pci_enable_msi(pdev); 462 if (err) 463 goto intx; 464 465 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, 466 "ioat-msi", ioat_dma); 467 if (err) { 468 pci_disable_msi(pdev); 469 goto intx; 470 } 471 ioat_dma->irq_mode = IOAT_MSI; 472 goto done; 473 474 intx: 475 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 476 IRQF_SHARED, "ioat-intx", ioat_dma); 477 if (err) 478 goto err_no_irq; 479 480 ioat_dma->irq_mode = IOAT_INTX; 481 done: 482 if (is_bwd_ioat(pdev)) 483 ioat_intr_quirk(ioat_dma); 484 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; 485 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 486 return 0; 487 488 err_no_irq: 489 /* Disable all interrupt generation */ 490 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 491 ioat_dma->irq_mode = IOAT_NOIRQ; 492 dev_err(dev, "no usable interrupts\n"); 493 return err; 494 } 495 496 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) 497 { 498 /* Disable all interrupt generation */ 499 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); 500 } 501 502 static int ioat_probe(struct ioatdma_device *ioat_dma) 503 { 504 int err = -ENODEV; 505 struct dma_device *dma = &ioat_dma->dma_dev; 506 struct pci_dev *pdev = ioat_dma->pdev; 507 struct device *dev = &pdev->dev; 508 509 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev, 510 sizeof(u64), 511 SMP_CACHE_BYTES, 512 SMP_CACHE_BYTES); 513 514 if (!ioat_dma->completion_pool) { 515 err = -ENOMEM; 516 goto err_out; 517 } 518 519 ioat_enumerate_channels(ioat_dma); 520 521 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 522 dma->dev = &pdev->dev; 523 524 if (!dma->chancnt) { 525 dev_err(dev, "channel enumeration error\n"); 526 goto err_setup_interrupts; 527 } 528 529 err = ioat_dma_setup_interrupts(ioat_dma); 530 if (err) 531 goto err_setup_interrupts; 532 533 err = ioat3_dma_self_test(ioat_dma); 534 if (err) 535 goto err_self_test; 536 537 return 0; 538 539 err_self_test: 540 ioat_disable_interrupts(ioat_dma); 541 err_setup_interrupts: 542 dma_pool_destroy(ioat_dma->completion_pool); 543 err_out: 544 return err; 545 } 546 547 static int ioat_register(struct ioatdma_device *ioat_dma) 548 { 549 int err = dma_async_device_register(&ioat_dma->dma_dev); 550 551 if (err) { 552 ioat_disable_interrupts(ioat_dma); 553 dma_pool_destroy(ioat_dma->completion_pool); 554 } 555 556 return err; 557 } 558 559 static void ioat_dma_remove(struct ioatdma_device *ioat_dma) 560 { 561 struct dma_device *dma = &ioat_dma->dma_dev; 562 563 ioat_disable_interrupts(ioat_dma); 564 565 ioat_kobject_del(ioat_dma); 566 567 dma_async_device_unregister(dma); 568 569 dma_pool_destroy(ioat_dma->completion_pool); 570 571 INIT_LIST_HEAD(&dma->channels); 572 } 573 574 /** 575 * ioat_enumerate_channels - find and initialize the device's channels 576 * @ioat_dma: the ioat dma device to be enumerated 577 */ 578 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma) 579 { 580 struct ioatdma_chan *ioat_chan; 581 struct device *dev = &ioat_dma->pdev->dev; 582 struct dma_device *dma = &ioat_dma->dma_dev; 583 u8 xfercap_log; 584 int i; 585 586 INIT_LIST_HEAD(&dma->channels); 587 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); 588 dma->chancnt &= 0x1f; /* bits [4:0] valid */ 589 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) { 590 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", 591 dma->chancnt, ARRAY_SIZE(ioat_dma->idx)); 592 dma->chancnt = ARRAY_SIZE(ioat_dma->idx); 593 } 594 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); 595 xfercap_log &= 0x1f; /* bits [4:0] valid */ 596 if (xfercap_log == 0) 597 return; 598 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); 599 600 for (i = 0; i < dma->chancnt; i++) { 601 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); 602 if (!ioat_chan) 603 break; 604 605 ioat_init_channel(ioat_dma, ioat_chan, i); 606 ioat_chan->xfercap_log = xfercap_log; 607 spin_lock_init(&ioat_chan->prep_lock); 608 if (ioat_reset_hw(ioat_chan)) { 609 i = 0; 610 break; 611 } 612 } 613 dma->chancnt = i; 614 } 615 616 /** 617 * ioat_free_chan_resources - release all the descriptors 618 * @chan: the channel to be cleaned 619 */ 620 static void ioat_free_chan_resources(struct dma_chan *c) 621 { 622 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 623 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; 624 struct ioat_ring_ent *desc; 625 const int total_descs = 1 << ioat_chan->alloc_order; 626 int descs; 627 int i; 628 629 /* Before freeing channel resources first check 630 * if they have been previously allocated for this channel. 631 */ 632 if (!ioat_chan->ring) 633 return; 634 635 ioat_stop(ioat_chan); 636 ioat_reset_hw(ioat_chan); 637 638 spin_lock_bh(&ioat_chan->cleanup_lock); 639 spin_lock_bh(&ioat_chan->prep_lock); 640 descs = ioat_ring_space(ioat_chan); 641 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); 642 for (i = 0; i < descs; i++) { 643 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); 644 ioat_free_ring_ent(desc, c); 645 } 646 647 if (descs < total_descs) 648 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", 649 total_descs - descs); 650 651 for (i = 0; i < total_descs - descs; i++) { 652 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); 653 dump_desc_dbg(ioat_chan, desc); 654 ioat_free_ring_ent(desc, c); 655 } 656 657 for (i = 0; i < ioat_chan->desc_chunks; i++) { 658 dma_free_coherent(to_dev(ioat_chan), SZ_2M, 659 ioat_chan->descs[i].virt, 660 ioat_chan->descs[i].hw); 661 ioat_chan->descs[i].virt = NULL; 662 ioat_chan->descs[i].hw = 0; 663 } 664 ioat_chan->desc_chunks = 0; 665 666 kfree(ioat_chan->ring); 667 ioat_chan->ring = NULL; 668 ioat_chan->alloc_order = 0; 669 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion, 670 ioat_chan->completion_dma); 671 spin_unlock_bh(&ioat_chan->prep_lock); 672 spin_unlock_bh(&ioat_chan->cleanup_lock); 673 674 ioat_chan->last_completion = 0; 675 ioat_chan->completion_dma = 0; 676 ioat_chan->dmacount = 0; 677 } 678 679 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring 680 * @chan: channel to be initialized 681 */ 682 static int ioat_alloc_chan_resources(struct dma_chan *c) 683 { 684 struct ioatdma_chan *ioat_chan = to_ioat_chan(c); 685 struct ioat_ring_ent **ring; 686 u64 status; 687 int order; 688 int i = 0; 689 u32 chanerr; 690 691 /* have we already been set up? */ 692 if (ioat_chan->ring) 693 return 1 << ioat_chan->alloc_order; 694 695 /* Setup register to interrupt and write completion status on error */ 696 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); 697 698 /* allocate a completion writeback area */ 699 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ 700 ioat_chan->completion = 701 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool, 702 GFP_NOWAIT, &ioat_chan->completion_dma); 703 if (!ioat_chan->completion) 704 return -ENOMEM; 705 706 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, 707 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); 708 writel(((u64)ioat_chan->completion_dma) >> 32, 709 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); 710 711 order = IOAT_MAX_ORDER; 712 ring = ioat_alloc_ring(c, order, GFP_NOWAIT); 713 if (!ring) 714 return -ENOMEM; 715 716 spin_lock_bh(&ioat_chan->cleanup_lock); 717 spin_lock_bh(&ioat_chan->prep_lock); 718 ioat_chan->ring = ring; 719 ioat_chan->head = 0; 720 ioat_chan->issued = 0; 721 ioat_chan->tail = 0; 722 ioat_chan->alloc_order = order; 723 set_bit(IOAT_RUN, &ioat_chan->state); 724 spin_unlock_bh(&ioat_chan->prep_lock); 725 spin_unlock_bh(&ioat_chan->cleanup_lock); 726 727 ioat_start_null_desc(ioat_chan); 728 729 /* check that we got off the ground */ 730 do { 731 udelay(1); 732 status = ioat_chansts(ioat_chan); 733 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); 734 735 if (is_ioat_active(status) || is_ioat_idle(status)) 736 return 1 << ioat_chan->alloc_order; 737 738 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 739 740 dev_WARN(to_dev(ioat_chan), 741 "failed to start channel chanerr: %#x\n", chanerr); 742 ioat_free_chan_resources(c); 743 return -EFAULT; 744 } 745 746 /* common channel initialization */ 747 static void 748 ioat_init_channel(struct ioatdma_device *ioat_dma, 749 struct ioatdma_chan *ioat_chan, int idx) 750 { 751 struct dma_device *dma = &ioat_dma->dma_dev; 752 struct dma_chan *c = &ioat_chan->dma_chan; 753 unsigned long data = (unsigned long) c; 754 755 ioat_chan->ioat_dma = ioat_dma; 756 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); 757 spin_lock_init(&ioat_chan->cleanup_lock); 758 ioat_chan->dma_chan.device = dma; 759 dma_cookie_init(&ioat_chan->dma_chan); 760 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); 761 ioat_dma->idx[idx] = ioat_chan; 762 timer_setup(&ioat_chan->timer, ioat_timer_event, 0); 763 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data); 764 } 765 766 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ 767 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) 768 { 769 int i, src_idx; 770 struct page *dest; 771 struct page *xor_srcs[IOAT_NUM_SRC_TEST]; 772 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; 773 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; 774 dma_addr_t dest_dma; 775 struct dma_async_tx_descriptor *tx; 776 struct dma_chan *dma_chan; 777 dma_cookie_t cookie; 778 u8 cmp_byte = 0; 779 u32 cmp_word; 780 u32 xor_val_result; 781 int err = 0; 782 struct completion cmp; 783 unsigned long tmo; 784 struct device *dev = &ioat_dma->pdev->dev; 785 struct dma_device *dma = &ioat_dma->dma_dev; 786 u8 op = 0; 787 788 dev_dbg(dev, "%s\n", __func__); 789 790 if (!dma_has_cap(DMA_XOR, dma->cap_mask)) 791 return 0; 792 793 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 794 xor_srcs[src_idx] = alloc_page(GFP_KERNEL); 795 if (!xor_srcs[src_idx]) { 796 while (src_idx--) 797 __free_page(xor_srcs[src_idx]); 798 return -ENOMEM; 799 } 800 } 801 802 dest = alloc_page(GFP_KERNEL); 803 if (!dest) { 804 while (src_idx--) 805 __free_page(xor_srcs[src_idx]); 806 return -ENOMEM; 807 } 808 809 /* Fill in src buffers */ 810 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { 811 u8 *ptr = page_address(xor_srcs[src_idx]); 812 813 for (i = 0; i < PAGE_SIZE; i++) 814 ptr[i] = (1 << src_idx); 815 } 816 817 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) 818 cmp_byte ^= (u8) (1 << src_idx); 819 820 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | 821 (cmp_byte << 8) | cmp_byte; 822 823 memset(page_address(dest), 0, PAGE_SIZE); 824 825 dma_chan = container_of(dma->channels.next, struct dma_chan, 826 device_node); 827 if (dma->device_alloc_chan_resources(dma_chan) < 1) { 828 err = -ENODEV; 829 goto out; 830 } 831 832 /* test xor */ 833 op = IOAT_OP_XOR; 834 835 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); 836 if (dma_mapping_error(dev, dest_dma)) { 837 err = -ENOMEM; 838 goto free_resources; 839 } 840 841 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { 842 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, 843 DMA_TO_DEVICE); 844 if (dma_mapping_error(dev, dma_srcs[i])) { 845 err = -ENOMEM; 846 goto dma_unmap; 847 } 848 } 849 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, 850 IOAT_NUM_SRC_TEST, PAGE_SIZE, 851 DMA_PREP_INTERRUPT); 852 853 if (!tx) { 854 dev_err(dev, "Self-test xor prep failed\n"); 855 err = -ENODEV; 856 goto dma_unmap; 857 } 858 859 async_tx_ack(tx); 860 init_completion(&cmp); 861 tx->callback = ioat_dma_test_callback; 862 tx->callback_param = &cmp; 863 cookie = tx->tx_submit(tx); 864 if (cookie < 0) { 865 dev_err(dev, "Self-test xor setup failed\n"); 866 err = -ENODEV; 867 goto dma_unmap; 868 } 869 dma->device_issue_pending(dma_chan); 870 871 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 872 873 if (tmo == 0 || 874 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 875 dev_err(dev, "Self-test xor timed out\n"); 876 err = -ENODEV; 877 goto dma_unmap; 878 } 879 880 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 881 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 882 883 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 884 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { 885 u32 *ptr = page_address(dest); 886 887 if (ptr[i] != cmp_word) { 888 dev_err(dev, "Self-test xor failed compare\n"); 889 err = -ENODEV; 890 goto free_resources; 891 } 892 } 893 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 894 895 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 896 897 /* skip validate if the capability is not present */ 898 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) 899 goto free_resources; 900 901 op = IOAT_OP_XOR_VAL; 902 903 /* validate the sources with the destintation page */ 904 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) 905 xor_val_srcs[i] = xor_srcs[i]; 906 xor_val_srcs[i] = dest; 907 908 xor_val_result = 1; 909 910 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 911 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 912 DMA_TO_DEVICE); 913 if (dma_mapping_error(dev, dma_srcs[i])) { 914 err = -ENOMEM; 915 goto dma_unmap; 916 } 917 } 918 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 919 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 920 &xor_val_result, DMA_PREP_INTERRUPT); 921 if (!tx) { 922 dev_err(dev, "Self-test zero prep failed\n"); 923 err = -ENODEV; 924 goto dma_unmap; 925 } 926 927 async_tx_ack(tx); 928 init_completion(&cmp); 929 tx->callback = ioat_dma_test_callback; 930 tx->callback_param = &cmp; 931 cookie = tx->tx_submit(tx); 932 if (cookie < 0) { 933 dev_err(dev, "Self-test zero setup failed\n"); 934 err = -ENODEV; 935 goto dma_unmap; 936 } 937 dma->device_issue_pending(dma_chan); 938 939 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 940 941 if (tmo == 0 || 942 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 943 dev_err(dev, "Self-test validate timed out\n"); 944 err = -ENODEV; 945 goto dma_unmap; 946 } 947 948 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 949 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 950 951 if (xor_val_result != 0) { 952 dev_err(dev, "Self-test validate failed compare\n"); 953 err = -ENODEV; 954 goto free_resources; 955 } 956 957 memset(page_address(dest), 0, PAGE_SIZE); 958 959 /* test for non-zero parity sum */ 960 op = IOAT_OP_XOR_VAL; 961 962 xor_val_result = 0; 963 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { 964 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, 965 DMA_TO_DEVICE); 966 if (dma_mapping_error(dev, dma_srcs[i])) { 967 err = -ENOMEM; 968 goto dma_unmap; 969 } 970 } 971 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, 972 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, 973 &xor_val_result, DMA_PREP_INTERRUPT); 974 if (!tx) { 975 dev_err(dev, "Self-test 2nd zero prep failed\n"); 976 err = -ENODEV; 977 goto dma_unmap; 978 } 979 980 async_tx_ack(tx); 981 init_completion(&cmp); 982 tx->callback = ioat_dma_test_callback; 983 tx->callback_param = &cmp; 984 cookie = tx->tx_submit(tx); 985 if (cookie < 0) { 986 dev_err(dev, "Self-test 2nd zero setup failed\n"); 987 err = -ENODEV; 988 goto dma_unmap; 989 } 990 dma->device_issue_pending(dma_chan); 991 992 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); 993 994 if (tmo == 0 || 995 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { 996 dev_err(dev, "Self-test 2nd validate timed out\n"); 997 err = -ENODEV; 998 goto dma_unmap; 999 } 1000 1001 if (xor_val_result != SUM_CHECK_P_RESULT) { 1002 dev_err(dev, "Self-test validate failed compare\n"); 1003 err = -ENODEV; 1004 goto dma_unmap; 1005 } 1006 1007 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) 1008 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); 1009 1010 goto free_resources; 1011 dma_unmap: 1012 if (op == IOAT_OP_XOR) { 1013 while (--i >= 0) 1014 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1015 DMA_TO_DEVICE); 1016 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); 1017 } else if (op == IOAT_OP_XOR_VAL) { 1018 while (--i >= 0) 1019 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, 1020 DMA_TO_DEVICE); 1021 } 1022 free_resources: 1023 dma->device_free_chan_resources(dma_chan); 1024 out: 1025 src_idx = IOAT_NUM_SRC_TEST; 1026 while (src_idx--) 1027 __free_page(xor_srcs[src_idx]); 1028 __free_page(dest); 1029 return err; 1030 } 1031 1032 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) 1033 { 1034 int rc; 1035 1036 rc = ioat_dma_self_test(ioat_dma); 1037 if (rc) 1038 return rc; 1039 1040 rc = ioat_xor_val_self_test(ioat_dma); 1041 1042 return rc; 1043 } 1044 1045 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma) 1046 { 1047 struct dma_device *dma; 1048 struct dma_chan *c; 1049 struct ioatdma_chan *ioat_chan; 1050 u32 errmask; 1051 1052 dma = &ioat_dma->dma_dev; 1053 1054 /* 1055 * if we have descriptor write back error status, we mask the 1056 * error interrupts 1057 */ 1058 if (ioat_dma->cap & IOAT_CAP_DWBES) { 1059 list_for_each_entry(c, &dma->channels, device_node) { 1060 ioat_chan = to_ioat_chan(c); 1061 errmask = readl(ioat_chan->reg_base + 1062 IOAT_CHANERR_MASK_OFFSET); 1063 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | 1064 IOAT_CHANERR_XOR_Q_ERR; 1065 writel(errmask, ioat_chan->reg_base + 1066 IOAT_CHANERR_MASK_OFFSET); 1067 } 1068 } 1069 } 1070 1071 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 1072 { 1073 struct pci_dev *pdev = ioat_dma->pdev; 1074 int dca_en = system_has_dca_enabled(pdev); 1075 struct dma_device *dma; 1076 struct dma_chan *c; 1077 struct ioatdma_chan *ioat_chan; 1078 int err; 1079 u16 val16; 1080 1081 dma = &ioat_dma->dma_dev; 1082 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; 1083 dma->device_issue_pending = ioat_issue_pending; 1084 dma->device_alloc_chan_resources = ioat_alloc_chan_resources; 1085 dma->device_free_chan_resources = ioat_free_chan_resources; 1086 1087 dma_cap_set(DMA_INTERRUPT, dma->cap_mask); 1088 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; 1089 1090 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); 1091 1092 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) 1093 ioat_dma->cap &= 1094 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); 1095 1096 /* dca is incompatible with raid operations */ 1097 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) 1098 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); 1099 1100 if (ioat_dma->cap & IOAT_CAP_XOR) { 1101 dma->max_xor = 8; 1102 1103 dma_cap_set(DMA_XOR, dma->cap_mask); 1104 dma->device_prep_dma_xor = ioat_prep_xor; 1105 1106 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1107 dma->device_prep_dma_xor_val = ioat_prep_xor_val; 1108 } 1109 1110 if (ioat_dma->cap & IOAT_CAP_PQ) { 1111 1112 dma->device_prep_dma_pq = ioat_prep_pq; 1113 dma->device_prep_dma_pq_val = ioat_prep_pq_val; 1114 dma_cap_set(DMA_PQ, dma->cap_mask); 1115 dma_cap_set(DMA_PQ_VAL, dma->cap_mask); 1116 1117 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1118 dma_set_maxpq(dma, 16, 0); 1119 else 1120 dma_set_maxpq(dma, 8, 0); 1121 1122 if (!(ioat_dma->cap & IOAT_CAP_XOR)) { 1123 dma->device_prep_dma_xor = ioat_prep_pqxor; 1124 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; 1125 dma_cap_set(DMA_XOR, dma->cap_mask); 1126 dma_cap_set(DMA_XOR_VAL, dma->cap_mask); 1127 1128 if (ioat_dma->cap & IOAT_CAP_RAID16SS) 1129 dma->max_xor = 16; 1130 else 1131 dma->max_xor = 8; 1132 } 1133 } 1134 1135 dma->device_tx_status = ioat_tx_status; 1136 1137 /* starting with CB3.3 super extended descriptors are supported */ 1138 if (ioat_dma->cap & IOAT_CAP_RAID16SS) { 1139 char pool_name[14]; 1140 int i; 1141 1142 for (i = 0; i < MAX_SED_POOLS; i++) { 1143 snprintf(pool_name, 14, "ioat_hw%d_sed", i); 1144 1145 /* allocate SED DMA pool */ 1146 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, 1147 &pdev->dev, 1148 SED_SIZE * (i + 1), 64, 0); 1149 if (!ioat_dma->sed_hw_pool[i]) 1150 return -ENOMEM; 1151 1152 } 1153 } 1154 1155 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) 1156 dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1157 1158 err = ioat_probe(ioat_dma); 1159 if (err) 1160 return err; 1161 1162 list_for_each_entry(c, &dma->channels, device_node) { 1163 ioat_chan = to_ioat_chan(c); 1164 writel(IOAT_DMA_DCA_ANY_CPU, 1165 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 1166 } 1167 1168 err = ioat_register(ioat_dma); 1169 if (err) 1170 return err; 1171 1172 ioat_kobject_add(ioat_dma, &ioat_ktype); 1173 1174 if (dca) 1175 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); 1176 1177 /* disable relaxed ordering */ 1178 err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16); 1179 if (err) 1180 return err; 1181 1182 /* clear relaxed ordering enable */ 1183 val16 &= ~IOAT_DEVCTRL_ROE; 1184 err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16); 1185 if (err) 1186 return err; 1187 1188 return 0; 1189 } 1190 1191 static void ioat_shutdown(struct pci_dev *pdev) 1192 { 1193 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1194 struct ioatdma_chan *ioat_chan; 1195 int i; 1196 1197 if (!ioat_dma) 1198 return; 1199 1200 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1201 ioat_chan = ioat_dma->idx[i]; 1202 if (!ioat_chan) 1203 continue; 1204 1205 spin_lock_bh(&ioat_chan->prep_lock); 1206 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1207 spin_unlock_bh(&ioat_chan->prep_lock); 1208 /* 1209 * Synchronization rule for del_timer_sync(): 1210 * - The caller must not hold locks which would prevent 1211 * completion of the timer's handler. 1212 * So prep_lock cannot be held before calling it. 1213 */ 1214 del_timer_sync(&ioat_chan->timer); 1215 1216 /* this should quiesce then reset */ 1217 ioat_reset_hw(ioat_chan); 1218 } 1219 1220 ioat_disable_interrupts(ioat_dma); 1221 } 1222 1223 static void ioat_resume(struct ioatdma_device *ioat_dma) 1224 { 1225 struct ioatdma_chan *ioat_chan; 1226 u32 chanerr; 1227 int i; 1228 1229 for (i = 0; i < IOAT_MAX_CHANS; i++) { 1230 ioat_chan = ioat_dma->idx[i]; 1231 if (!ioat_chan) 1232 continue; 1233 1234 spin_lock_bh(&ioat_chan->prep_lock); 1235 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); 1236 spin_unlock_bh(&ioat_chan->prep_lock); 1237 1238 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1239 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 1240 1241 /* no need to reset as shutdown already did that */ 1242 } 1243 } 1244 1245 #define DRV_NAME "ioatdma" 1246 1247 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev, 1248 enum pci_channel_state error) 1249 { 1250 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error); 1251 1252 /* quiesce and block I/O */ 1253 ioat_shutdown(pdev); 1254 1255 return PCI_ERS_RESULT_NEED_RESET; 1256 } 1257 1258 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev) 1259 { 1260 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 1261 1262 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME); 1263 1264 if (pci_enable_device_mem(pdev) < 0) { 1265 dev_err(&pdev->dev, 1266 "Failed to enable PCIe device after reset.\n"); 1267 result = PCI_ERS_RESULT_DISCONNECT; 1268 } else { 1269 pci_set_master(pdev); 1270 pci_restore_state(pdev); 1271 pci_save_state(pdev); 1272 pci_wake_from_d3(pdev, false); 1273 } 1274 1275 return result; 1276 } 1277 1278 static void ioat_pcie_error_resume(struct pci_dev *pdev) 1279 { 1280 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); 1281 1282 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME); 1283 1284 /* initialize and bring everything back */ 1285 ioat_resume(ioat_dma); 1286 } 1287 1288 static const struct pci_error_handlers ioat_err_handler = { 1289 .error_detected = ioat_pcie_error_detected, 1290 .slot_reset = ioat_pcie_error_slot_reset, 1291 .resume = ioat_pcie_error_resume, 1292 }; 1293 1294 static struct pci_driver ioat_pci_driver = { 1295 .name = DRV_NAME, 1296 .id_table = ioat_pci_tbl, 1297 .probe = ioat_pci_probe, 1298 .remove = ioat_remove, 1299 .shutdown = ioat_shutdown, 1300 .err_handler = &ioat_err_handler, 1301 }; 1302 1303 static struct ioatdma_device * 1304 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) 1305 { 1306 struct device *dev = &pdev->dev; 1307 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 1308 1309 if (!d) 1310 return NULL; 1311 d->pdev = pdev; 1312 d->reg_base = iobase; 1313 return d; 1314 } 1315 1316 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1317 { 1318 void __iomem * const *iomap; 1319 struct device *dev = &pdev->dev; 1320 struct ioatdma_device *device; 1321 int err; 1322 1323 err = pcim_enable_device(pdev); 1324 if (err) 1325 return err; 1326 1327 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); 1328 if (err) 1329 return err; 1330 iomap = pcim_iomap_table(pdev); 1331 if (!iomap) 1332 return -ENOMEM; 1333 1334 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1335 if (err) 1336 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1337 if (err) 1338 return err; 1339 1340 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1341 if (err) 1342 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1343 if (err) 1344 return err; 1345 1346 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); 1347 if (!device) 1348 return -ENOMEM; 1349 pci_set_master(pdev); 1350 pci_set_drvdata(pdev, device); 1351 1352 device->version = readb(device->reg_base + IOAT_VER_OFFSET); 1353 if (device->version >= IOAT_VER_3_0) { 1354 if (is_skx_ioat(pdev)) 1355 device->version = IOAT_VER_3_2; 1356 err = ioat3_dma_probe(device, ioat_dca_enabled); 1357 1358 if (device->version >= IOAT_VER_3_3) 1359 pci_enable_pcie_error_reporting(pdev); 1360 } else 1361 return -ENODEV; 1362 1363 if (err) { 1364 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); 1365 pci_disable_pcie_error_reporting(pdev); 1366 return -ENODEV; 1367 } 1368 1369 return 0; 1370 } 1371 1372 static void ioat_remove(struct pci_dev *pdev) 1373 { 1374 struct ioatdma_device *device = pci_get_drvdata(pdev); 1375 1376 if (!device) 1377 return; 1378 1379 dev_err(&pdev->dev, "Removing dma and dca services\n"); 1380 if (device->dca) { 1381 unregister_dca_provider(device->dca, &pdev->dev); 1382 free_dca_provider(device->dca); 1383 device->dca = NULL; 1384 } 1385 1386 pci_disable_pcie_error_reporting(pdev); 1387 ioat_dma_remove(device); 1388 } 1389 1390 static int __init ioat_init_module(void) 1391 { 1392 int err = -ENOMEM; 1393 1394 pr_info("%s: Intel(R) QuickData Technology Driver %s\n", 1395 DRV_NAME, IOAT_DMA_VERSION); 1396 1397 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), 1398 0, SLAB_HWCACHE_ALIGN, NULL); 1399 if (!ioat_cache) 1400 return -ENOMEM; 1401 1402 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); 1403 if (!ioat_sed_cache) 1404 goto err_ioat_cache; 1405 1406 err = pci_register_driver(&ioat_pci_driver); 1407 if (err) 1408 goto err_ioat3_cache; 1409 1410 return 0; 1411 1412 err_ioat3_cache: 1413 kmem_cache_destroy(ioat_sed_cache); 1414 1415 err_ioat_cache: 1416 kmem_cache_destroy(ioat_cache); 1417 1418 return err; 1419 } 1420 module_init(ioat_init_module); 1421 1422 static void __exit ioat_exit_module(void) 1423 { 1424 pci_unregister_driver(&ioat_pci_driver); 1425 kmem_cache_destroy(ioat_cache); 1426 } 1427 module_exit(ioat_exit_module); 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