1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef _IOAT_HW_H_ 22 #define _IOAT_HW_H_ 23 24 /* PCI Configuration Space Values */ 25 #define IOAT_MMIO_BAR 0 26 27 /* CB device ID's */ 28 #define IOAT_PCI_DID_5000 0x1A38 29 #define IOAT_PCI_DID_CNB 0x360B 30 #define IOAT_PCI_DID_SCNB 0x65FF 31 #define IOAT_PCI_DID_SNB 0x402F 32 33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20 34 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21 35 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22 36 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23 37 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24 38 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25 39 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26 40 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27 41 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e 42 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f 43 44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20 45 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21 46 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22 47 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23 48 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24 49 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25 50 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26 51 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27 52 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e 53 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f 54 55 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50 56 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51 57 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52 58 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53 59 60 #define IOAT_VER_1_2 0x12 /* Version 1.2 */ 61 #define IOAT_VER_2_0 0x20 /* Version 2.0 */ 62 #define IOAT_VER_3_0 0x30 /* Version 3.0 */ 63 #define IOAT_VER_3_2 0x32 /* Version 3.2 */ 64 #define IOAT_VER_3_3 0x33 /* Version 3.3 */ 65 66 67 int system_has_dca_enabled(struct pci_dev *pdev); 68 69 struct ioat_dma_descriptor { 70 uint32_t size; 71 union { 72 uint32_t ctl; 73 struct { 74 unsigned int int_en:1; 75 unsigned int src_snoop_dis:1; 76 unsigned int dest_snoop_dis:1; 77 unsigned int compl_write:1; 78 unsigned int fence:1; 79 unsigned int null:1; 80 unsigned int src_brk:1; 81 unsigned int dest_brk:1; 82 unsigned int bundle:1; 83 unsigned int dest_dca:1; 84 unsigned int hint:1; 85 unsigned int rsvd2:13; 86 #define IOAT_OP_COPY 0x00 87 unsigned int op:8; 88 } ctl_f; 89 }; 90 uint64_t src_addr; 91 uint64_t dst_addr; 92 uint64_t next; 93 uint64_t rsv1; 94 uint64_t rsv2; 95 /* store some driver data in an unused portion of the descriptor */ 96 union { 97 uint64_t user1; 98 uint64_t tx_cnt; 99 }; 100 uint64_t user2; 101 }; 102 103 struct ioat_xor_descriptor { 104 uint32_t size; 105 union { 106 uint32_t ctl; 107 struct { 108 unsigned int int_en:1; 109 unsigned int src_snoop_dis:1; 110 unsigned int dest_snoop_dis:1; 111 unsigned int compl_write:1; 112 unsigned int fence:1; 113 unsigned int src_cnt:3; 114 unsigned int bundle:1; 115 unsigned int dest_dca:1; 116 unsigned int hint:1; 117 unsigned int rsvd:13; 118 #define IOAT_OP_XOR 0x87 119 #define IOAT_OP_XOR_VAL 0x88 120 unsigned int op:8; 121 } ctl_f; 122 }; 123 uint64_t src_addr; 124 uint64_t dst_addr; 125 uint64_t next; 126 uint64_t src_addr2; 127 uint64_t src_addr3; 128 uint64_t src_addr4; 129 uint64_t src_addr5; 130 }; 131 132 struct ioat_xor_ext_descriptor { 133 uint64_t src_addr6; 134 uint64_t src_addr7; 135 uint64_t src_addr8; 136 uint64_t next; 137 uint64_t rsvd[4]; 138 }; 139 140 struct ioat_pq_descriptor { 141 union { 142 uint32_t size; 143 uint32_t dwbes; 144 struct { 145 unsigned int rsvd:25; 146 unsigned int p_val_err:1; 147 unsigned int q_val_err:1; 148 unsigned int rsvd1:4; 149 unsigned int wbes:1; 150 } dwbes_f; 151 }; 152 union { 153 uint32_t ctl; 154 struct { 155 unsigned int int_en:1; 156 unsigned int src_snoop_dis:1; 157 unsigned int dest_snoop_dis:1; 158 unsigned int compl_write:1; 159 unsigned int fence:1; 160 unsigned int src_cnt:3; 161 unsigned int bundle:1; 162 unsigned int dest_dca:1; 163 unsigned int hint:1; 164 unsigned int p_disable:1; 165 unsigned int q_disable:1; 166 unsigned int rsvd2:2; 167 unsigned int wb_en:1; 168 unsigned int prl_en:1; 169 unsigned int rsvd3:7; 170 #define IOAT_OP_PQ 0x89 171 #define IOAT_OP_PQ_VAL 0x8a 172 #define IOAT_OP_PQ_16S 0xa0 173 #define IOAT_OP_PQ_VAL_16S 0xa1 174 unsigned int op:8; 175 } ctl_f; 176 }; 177 uint64_t src_addr; 178 uint64_t p_addr; 179 uint64_t next; 180 uint64_t src_addr2; 181 union { 182 uint64_t src_addr3; 183 uint64_t sed_addr; 184 }; 185 uint8_t coef[8]; 186 uint64_t q_addr; 187 }; 188 189 struct ioat_pq_ext_descriptor { 190 uint64_t src_addr4; 191 uint64_t src_addr5; 192 uint64_t src_addr6; 193 uint64_t next; 194 uint64_t src_addr7; 195 uint64_t src_addr8; 196 uint64_t rsvd[2]; 197 }; 198 199 struct ioat_pq_update_descriptor { 200 uint32_t size; 201 union { 202 uint32_t ctl; 203 struct { 204 unsigned int int_en:1; 205 unsigned int src_snoop_dis:1; 206 unsigned int dest_snoop_dis:1; 207 unsigned int compl_write:1; 208 unsigned int fence:1; 209 unsigned int src_cnt:3; 210 unsigned int bundle:1; 211 unsigned int dest_dca:1; 212 unsigned int hint:1; 213 unsigned int p_disable:1; 214 unsigned int q_disable:1; 215 unsigned int rsvd:3; 216 unsigned int coef:8; 217 #define IOAT_OP_PQ_UP 0x8b 218 unsigned int op:8; 219 } ctl_f; 220 }; 221 uint64_t src_addr; 222 uint64_t p_addr; 223 uint64_t next; 224 uint64_t src_addr2; 225 uint64_t p_src; 226 uint64_t q_src; 227 uint64_t q_addr; 228 }; 229 230 struct ioat_raw_descriptor { 231 uint64_t field[8]; 232 }; 233 234 struct ioat_pq16a_descriptor { 235 uint8_t coef[8]; 236 uint64_t src_addr3; 237 uint64_t src_addr4; 238 uint64_t src_addr5; 239 uint64_t src_addr6; 240 uint64_t src_addr7; 241 uint64_t src_addr8; 242 uint64_t src_addr9; 243 }; 244 245 struct ioat_pq16b_descriptor { 246 uint64_t src_addr10; 247 uint64_t src_addr11; 248 uint64_t src_addr12; 249 uint64_t src_addr13; 250 uint64_t src_addr14; 251 uint64_t src_addr15; 252 uint64_t src_addr16; 253 uint64_t rsvd; 254 }; 255 256 union ioat_sed_pq_descriptor { 257 struct ioat_pq16a_descriptor a; 258 struct ioat_pq16b_descriptor b; 259 }; 260 261 #define SED_SIZE 64 262 263 struct ioat_sed_raw_descriptor { 264 uint64_t a[8]; 265 uint64_t b[8]; 266 uint64_t c[8]; 267 }; 268 269 #endif 270