1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef IOATDMA_H 18 #define IOATDMA_H 19 20 #include <linux/dmaengine.h> 21 #include <linux/init.h> 22 #include <linux/dmapool.h> 23 #include <linux/cache.h> 24 #include <linux/pci_ids.h> 25 #include <linux/circ_buf.h> 26 #include <linux/interrupt.h> 27 #include "registers.h" 28 #include "hw.h" 29 30 #define IOAT_DMA_VERSION "4.00" 31 32 #define IOAT_DMA_DCA_ANY_CPU ~0 33 34 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev) 35 #define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev) 36 #define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev) 37 38 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80) 39 40 /* ioat hardware assumes at least two sources for raid operations */ 41 #define src_cnt_to_sw(x) ((x) + 2) 42 #define src_cnt_to_hw(x) ((x) - 2) 43 #define ndest_to_sw(x) ((x) + 1) 44 #define ndest_to_hw(x) ((x) - 1) 45 #define src16_cnt_to_sw(x) ((x) + 9) 46 #define src16_cnt_to_hw(x) ((x) - 9) 47 48 /* 49 * workaround for IOAT ver.3.0 null descriptor issue 50 * (channel returns error when size is 0) 51 */ 52 #define NULL_DESC_BUFFER_SIZE 1 53 54 enum ioat_irq_mode { 55 IOAT_NOIRQ = 0, 56 IOAT_MSIX, 57 IOAT_MSI, 58 IOAT_INTX 59 }; 60 61 /** 62 * struct ioatdma_device - internal representation of a IOAT device 63 * @pdev: PCI-Express device 64 * @reg_base: MMIO register space base address 65 * @dma_pool: for allocating DMA descriptors 66 * @completion_pool: DMA buffers for completion ops 67 * @sed_hw_pool: DMA super descriptor pools 68 * @dma_dev: embedded struct dma_device 69 * @version: version of ioatdma device 70 * @msix_entries: irq handlers 71 * @idx: per channel data 72 * @dca: direct cache access context 73 * @irq_mode: interrupt mode (INTX, MSI, MSIX) 74 * @cap: read DMA capabilities register 75 */ 76 struct ioatdma_device { 77 struct pci_dev *pdev; 78 void __iomem *reg_base; 79 struct pci_pool *dma_pool; 80 struct pci_pool *completion_pool; 81 #define MAX_SED_POOLS 5 82 struct dma_pool *sed_hw_pool[MAX_SED_POOLS]; 83 struct dma_device dma_dev; 84 u8 version; 85 #define IOAT_MAX_CHANS 4 86 struct msix_entry msix_entries[IOAT_MAX_CHANS]; 87 struct ioatdma_chan *idx[IOAT_MAX_CHANS]; 88 struct dca_provider *dca; 89 enum ioat_irq_mode irq_mode; 90 u32 cap; 91 }; 92 93 struct ioatdma_chan { 94 struct dma_chan dma_chan; 95 void __iomem *reg_base; 96 dma_addr_t last_completion; 97 spinlock_t cleanup_lock; 98 unsigned long state; 99 #define IOAT_CHAN_DOWN 0 100 #define IOAT_COMPLETION_ACK 1 101 #define IOAT_RESET_PENDING 2 102 #define IOAT_KOBJ_INIT_FAIL 3 103 #define IOAT_RESHAPE_PENDING 4 104 #define IOAT_RUN 5 105 #define IOAT_CHAN_ACTIVE 6 106 struct timer_list timer; 107 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 108 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 109 #define RESET_DELAY msecs_to_jiffies(100) 110 struct ioatdma_device *ioat_dma; 111 dma_addr_t completion_dma; 112 u64 *completion; 113 struct tasklet_struct cleanup_task; 114 struct kobject kobj; 115 116 /* ioat v2 / v3 channel attributes 117 * @xfercap_log; log2 of channel max transfer length (for fast division) 118 * @head: allocated index 119 * @issued: hardware notification point 120 * @tail: cleanup index 121 * @dmacount: identical to 'head' except for occasionally resetting to zero 122 * @alloc_order: log2 of the number of allocated descriptors 123 * @produce: number of descriptors to produce at submit time 124 * @ring: software ring buffer implementation of hardware ring 125 * @prep_lock: serializes descriptor preparation (producers) 126 */ 127 size_t xfercap_log; 128 u16 head; 129 u16 issued; 130 u16 tail; 131 u16 dmacount; 132 u16 alloc_order; 133 u16 produce; 134 struct ioat_ring_ent **ring; 135 spinlock_t prep_lock; 136 }; 137 138 struct ioat_sysfs_entry { 139 struct attribute attr; 140 ssize_t (*show)(struct dma_chan *, char *); 141 }; 142 143 /** 144 * struct ioat_sed_ent - wrapper around super extended hardware descriptor 145 * @hw: hardware SED 146 * @dma: dma address for the SED 147 * @parent: point to the dma descriptor that's the parent 148 * @hw_pool: descriptor pool index 149 */ 150 struct ioat_sed_ent { 151 struct ioat_sed_raw_descriptor *hw; 152 dma_addr_t dma; 153 struct ioat_ring_ent *parent; 154 unsigned int hw_pool; 155 }; 156 157 /** 158 * struct ioat_ring_ent - wrapper around hardware descriptor 159 * @hw: hardware DMA descriptor (for memcpy) 160 * @xor: hardware xor descriptor 161 * @xor_ex: hardware xor extension descriptor 162 * @pq: hardware pq descriptor 163 * @pq_ex: hardware pq extension descriptor 164 * @pqu: hardware pq update descriptor 165 * @raw: hardware raw (un-typed) descriptor 166 * @txd: the generic software descriptor for all engines 167 * @len: total transaction length for unmap 168 * @result: asynchronous result of validate operations 169 * @id: identifier for debug 170 * @sed: pointer to super extended descriptor sw desc 171 */ 172 173 struct ioat_ring_ent { 174 union { 175 struct ioat_dma_descriptor *hw; 176 struct ioat_xor_descriptor *xor; 177 struct ioat_xor_ext_descriptor *xor_ex; 178 struct ioat_pq_descriptor *pq; 179 struct ioat_pq_ext_descriptor *pq_ex; 180 struct ioat_pq_update_descriptor *pqu; 181 struct ioat_raw_descriptor *raw; 182 }; 183 size_t len; 184 struct dma_async_tx_descriptor txd; 185 enum sum_check_flags *result; 186 #ifdef DEBUG 187 int id; 188 #endif 189 struct ioat_sed_ent *sed; 190 }; 191 192 extern const struct sysfs_ops ioat_sysfs_ops; 193 extern struct ioat_sysfs_entry ioat_version_attr; 194 extern struct ioat_sysfs_entry ioat_cap_attr; 195 extern int ioat_pending_level; 196 extern int ioat_ring_alloc_order; 197 extern struct kobj_type ioat_ktype; 198 extern struct kmem_cache *ioat_cache; 199 extern int ioat_ring_max_alloc_order; 200 extern struct kmem_cache *ioat_sed_cache; 201 202 static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c) 203 { 204 return container_of(c, struct ioatdma_chan, dma_chan); 205 } 206 207 /* wrapper around hardware descriptor format + additional software fields */ 208 #ifdef DEBUG 209 #define set_desc_id(desc, i) ((desc)->id = (i)) 210 #define desc_id(desc) ((desc)->id) 211 #else 212 #define set_desc_id(desc, i) 213 #define desc_id(desc) (0) 214 #endif 215 216 static inline void 217 __dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw, 218 struct dma_async_tx_descriptor *tx, int id) 219 { 220 struct device *dev = to_dev(ioat_chan); 221 222 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 223 " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id, 224 (unsigned long long) tx->phys, 225 (unsigned long long) hw->next, tx->cookie, tx->flags, 226 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 227 } 228 229 #define dump_desc_dbg(c, d) \ 230 ({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; }) 231 232 static inline struct ioatdma_chan * 233 ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index) 234 { 235 return ioat_dma->idx[index]; 236 } 237 238 static inline u64 ioat_chansts_32(struct ioatdma_chan *ioat_chan) 239 { 240 u8 ver = ioat_chan->ioat_dma->version; 241 u64 status; 242 u32 status_lo; 243 244 /* We need to read the low address first as this causes the 245 * chipset to latch the upper bits for the subsequent read 246 */ 247 status_lo = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); 248 status = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); 249 status <<= 32; 250 status |= status_lo; 251 252 return status; 253 } 254 255 #if BITS_PER_LONG == 64 256 257 static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan) 258 { 259 u8 ver = ioat_chan->ioat_dma->version; 260 u64 status; 261 262 /* With IOAT v3.3 the status register is 64bit. */ 263 if (ver >= IOAT_VER_3_3) 264 status = readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); 265 else 266 status = ioat_chansts_32(ioat_chan); 267 268 return status; 269 } 270 271 #else 272 #define ioat_chansts ioat_chansts_32 273 #endif 274 275 static inline u64 ioat_chansts_to_addr(u64 status) 276 { 277 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 278 } 279 280 static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan) 281 { 282 return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 283 } 284 285 static inline void ioat_suspend(struct ioatdma_chan *ioat_chan) 286 { 287 u8 ver = ioat_chan->ioat_dma->version; 288 289 writeb(IOAT_CHANCMD_SUSPEND, 290 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 291 } 292 293 static inline void ioat_reset(struct ioatdma_chan *ioat_chan) 294 { 295 u8 ver = ioat_chan->ioat_dma->version; 296 297 writeb(IOAT_CHANCMD_RESET, 298 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 299 } 300 301 static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan) 302 { 303 u8 ver = ioat_chan->ioat_dma->version; 304 u8 cmd; 305 306 cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 307 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; 308 } 309 310 static inline bool is_ioat_active(unsigned long status) 311 { 312 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 313 } 314 315 static inline bool is_ioat_idle(unsigned long status) 316 { 317 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 318 } 319 320 static inline bool is_ioat_halted(unsigned long status) 321 { 322 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 323 } 324 325 static inline bool is_ioat_suspended(unsigned long status) 326 { 327 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 328 } 329 330 /* channel was fatally programmed */ 331 static inline bool is_ioat_bug(unsigned long err) 332 { 333 return !!err; 334 } 335 336 #define IOAT_MAX_ORDER 16 337 #define ioat_get_alloc_order() \ 338 (min(ioat_ring_alloc_order, IOAT_MAX_ORDER)) 339 #define ioat_get_max_alloc_order() \ 340 (min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER)) 341 342 static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan) 343 { 344 return 1 << ioat_chan->alloc_order; 345 } 346 347 /* count of descriptors in flight with the engine */ 348 static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan) 349 { 350 return CIRC_CNT(ioat_chan->head, ioat_chan->tail, 351 ioat_ring_size(ioat_chan)); 352 } 353 354 /* count of descriptors pending submission to hardware */ 355 static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan) 356 { 357 return CIRC_CNT(ioat_chan->head, ioat_chan->issued, 358 ioat_ring_size(ioat_chan)); 359 } 360 361 static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan) 362 { 363 return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan); 364 } 365 366 static inline u16 367 ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len) 368 { 369 u16 num_descs = len >> ioat_chan->xfercap_log; 370 371 num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1)); 372 return num_descs; 373 } 374 375 static inline struct ioat_ring_ent * 376 ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx) 377 { 378 return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)]; 379 } 380 381 static inline void 382 ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr) 383 { 384 writel(addr & 0x00000000FFFFFFFF, 385 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); 386 writel(addr >> 32, 387 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); 388 } 389 390 /* IOAT Prep functions */ 391 struct dma_async_tx_descriptor * 392 ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, 393 dma_addr_t dma_src, size_t len, unsigned long flags); 394 struct dma_async_tx_descriptor * 395 ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags); 396 struct dma_async_tx_descriptor * 397 ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, 398 unsigned int src_cnt, size_t len, unsigned long flags); 399 struct dma_async_tx_descriptor * 400 ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, 401 unsigned int src_cnt, size_t len, 402 enum sum_check_flags *result, unsigned long flags); 403 struct dma_async_tx_descriptor * 404 ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 405 unsigned int src_cnt, const unsigned char *scf, size_t len, 406 unsigned long flags); 407 struct dma_async_tx_descriptor * 408 ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 409 unsigned int src_cnt, const unsigned char *scf, size_t len, 410 enum sum_check_flags *pqres, unsigned long flags); 411 struct dma_async_tx_descriptor * 412 ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, 413 unsigned int src_cnt, size_t len, unsigned long flags); 414 struct dma_async_tx_descriptor * 415 ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, 416 unsigned int src_cnt, size_t len, 417 enum sum_check_flags *result, unsigned long flags); 418 419 /* IOAT Operation functions */ 420 irqreturn_t ioat_dma_do_interrupt(int irq, void *data); 421 irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data); 422 struct ioat_ring_ent ** 423 ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags); 424 void ioat_start_null_desc(struct ioatdma_chan *ioat_chan); 425 void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan); 426 int ioat_reset_hw(struct ioatdma_chan *ioat_chan); 427 enum dma_status 428 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, 429 struct dma_tx_state *txstate); 430 void ioat_cleanup_event(unsigned long data); 431 void ioat_timer_event(unsigned long data); 432 int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs); 433 void ioat_issue_pending(struct dma_chan *chan); 434 void ioat_timer_event(unsigned long data); 435 436 /* IOAT Init functions */ 437 bool is_bwd_ioat(struct pci_dev *pdev); 438 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); 439 void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type); 440 void ioat_kobject_del(struct ioatdma_device *ioat_dma); 441 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma); 442 void ioat_stop(struct ioatdma_chan *ioat_chan); 443 #endif /* IOATDMA_H */ 444