1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef IOATDMA_H 22 #define IOATDMA_H 23 24 #include <linux/dmaengine.h> 25 #include "hw.h" 26 #include "registers.h" 27 #include <linux/init.h> 28 #include <linux/dmapool.h> 29 #include <linux/cache.h> 30 #include <linux/pci_ids.h> 31 #include <net/tcp.h> 32 33 #define IOAT_DMA_VERSION "4.00" 34 35 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 36 #define IOAT_DMA_DCA_ANY_CPU ~0 37 38 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) 39 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) 40 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd) 41 #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev) 42 43 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) 44 45 /* 46 * workaround for IOAT ver.3.0 null descriptor issue 47 * (channel returns error when size is 0) 48 */ 49 #define NULL_DESC_BUFFER_SIZE 1 50 51 /** 52 * struct ioatdma_device - internal representation of a IOAT device 53 * @pdev: PCI-Express device 54 * @reg_base: MMIO register space base address 55 * @dma_pool: for allocating DMA descriptors 56 * @common: embedded struct dma_device 57 * @version: version of ioatdma device 58 * @msix_entries: irq handlers 59 * @idx: per channel data 60 * @dca: direct cache access context 61 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) 62 * @enumerate_channels: hw version specific channel enumeration 63 * @reset_hw: hw version specific channel (re)initialization 64 * @cleanup_fn: select between the v2 and v3 cleanup routines 65 * @timer_fn: select between the v2 and v3 timer watchdog routines 66 * @self_test: hardware version specific self test for each supported op type 67 * 68 * Note: the v3 cleanup routine supports raid operations 69 */ 70 struct ioatdma_device { 71 struct pci_dev *pdev; 72 void __iomem *reg_base; 73 struct pci_pool *dma_pool; 74 struct pci_pool *completion_pool; 75 struct dma_device common; 76 u8 version; 77 struct msix_entry msix_entries[4]; 78 struct ioat_chan_common *idx[4]; 79 struct dca_provider *dca; 80 void (*intr_quirk)(struct ioatdma_device *device); 81 int (*enumerate_channels)(struct ioatdma_device *device); 82 int (*reset_hw)(struct ioat_chan_common *chan); 83 void (*cleanup_fn)(unsigned long data); 84 void (*timer_fn)(unsigned long data); 85 int (*self_test)(struct ioatdma_device *device); 86 }; 87 88 struct ioat_chan_common { 89 struct dma_chan common; 90 void __iomem *reg_base; 91 unsigned long last_completion; 92 spinlock_t cleanup_lock; 93 dma_cookie_t completed_cookie; 94 unsigned long state; 95 #define IOAT_COMPLETION_PENDING 0 96 #define IOAT_COMPLETION_ACK 1 97 #define IOAT_RESET_PENDING 2 98 #define IOAT_KOBJ_INIT_FAIL 3 99 #define IOAT_RESHAPE_PENDING 4 100 struct timer_list timer; 101 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 102 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 103 #define RESET_DELAY msecs_to_jiffies(100) 104 struct ioatdma_device *device; 105 dma_addr_t completion_dma; 106 u64 *completion; 107 struct tasklet_struct cleanup_task; 108 struct kobject kobj; 109 }; 110 111 struct ioat_sysfs_entry { 112 struct attribute attr; 113 ssize_t (*show)(struct dma_chan *, char *); 114 }; 115 116 /** 117 * struct ioat_dma_chan - internal representation of a DMA channel 118 */ 119 struct ioat_dma_chan { 120 struct ioat_chan_common base; 121 122 size_t xfercap; /* XFERCAP register value expanded out */ 123 124 spinlock_t desc_lock; 125 struct list_head free_desc; 126 struct list_head used_desc; 127 128 int pending; 129 u16 desccount; 130 u16 active; 131 }; 132 133 static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) 134 { 135 return container_of(c, struct ioat_chan_common, common); 136 } 137 138 static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c) 139 { 140 struct ioat_chan_common *chan = to_chan_common(c); 141 142 return container_of(chan, struct ioat_dma_chan, base); 143 } 144 145 /** 146 * ioat_tx_status - poll the status of an ioat transaction 147 * @c: channel handle 148 * @cookie: transaction identifier 149 * @txstate: if set, updated with the transaction state 150 */ 151 static inline enum dma_status 152 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, 153 struct dma_tx_state *txstate) 154 { 155 struct ioat_chan_common *chan = to_chan_common(c); 156 dma_cookie_t last_used; 157 dma_cookie_t last_complete; 158 159 last_used = c->cookie; 160 last_complete = chan->completed_cookie; 161 162 dma_set_tx_state(txstate, last_complete, last_used, 0); 163 164 return dma_async_is_complete(cookie, last_complete, last_used); 165 } 166 167 /* wrapper around hardware descriptor format + additional software fields */ 168 169 /** 170 * struct ioat_desc_sw - wrapper around hardware descriptor 171 * @hw: hardware DMA descriptor (for memcpy) 172 * @node: this descriptor will either be on the free list, 173 * or attached to a transaction list (tx_list) 174 * @txd: the generic software descriptor for all engines 175 * @id: identifier for debug 176 */ 177 struct ioat_desc_sw { 178 struct ioat_dma_descriptor *hw; 179 struct list_head node; 180 size_t len; 181 struct list_head tx_list; 182 struct dma_async_tx_descriptor txd; 183 #ifdef DEBUG 184 int id; 185 #endif 186 }; 187 188 #ifdef DEBUG 189 #define set_desc_id(desc, i) ((desc)->id = (i)) 190 #define desc_id(desc) ((desc)->id) 191 #else 192 #define set_desc_id(desc, i) 193 #define desc_id(desc) (0) 194 #endif 195 196 static inline void 197 __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw, 198 struct dma_async_tx_descriptor *tx, int id) 199 { 200 struct device *dev = to_dev(chan); 201 202 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 203 " ctl: %#x (op: %d int_en: %d compl: %d)\n", id, 204 (unsigned long long) tx->phys, 205 (unsigned long long) hw->next, tx->cookie, tx->flags, 206 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 207 } 208 209 #define dump_desc_dbg(c, d) \ 210 ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; }) 211 212 static inline void ioat_set_tcp_copy_break(unsigned long copybreak) 213 { 214 #ifdef CONFIG_NET_DMA 215 sysctl_tcp_dma_copybreak = copybreak; 216 #endif 217 } 218 219 static inline struct ioat_chan_common * 220 ioat_chan_by_index(struct ioatdma_device *device, int index) 221 { 222 return device->idx[index]; 223 } 224 225 static inline u64 ioat_chansts(struct ioat_chan_common *chan) 226 { 227 u8 ver = chan->device->version; 228 u64 status; 229 u32 status_lo; 230 231 /* We need to read the low address first as this causes the 232 * chipset to latch the upper bits for the subsequent read 233 */ 234 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); 235 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); 236 status <<= 32; 237 status |= status_lo; 238 239 return status; 240 } 241 242 static inline void ioat_start(struct ioat_chan_common *chan) 243 { 244 u8 ver = chan->device->version; 245 246 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 247 } 248 249 static inline u64 ioat_chansts_to_addr(u64 status) 250 { 251 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 252 } 253 254 static inline u32 ioat_chanerr(struct ioat_chan_common *chan) 255 { 256 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); 257 } 258 259 static inline void ioat_suspend(struct ioat_chan_common *chan) 260 { 261 u8 ver = chan->device->version; 262 263 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 264 } 265 266 static inline void ioat_reset(struct ioat_chan_common *chan) 267 { 268 u8 ver = chan->device->version; 269 270 writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 271 } 272 273 static inline bool ioat_reset_pending(struct ioat_chan_common *chan) 274 { 275 u8 ver = chan->device->version; 276 u8 cmd; 277 278 cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 279 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; 280 } 281 282 static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr) 283 { 284 struct ioat_chan_common *chan = &ioat->base; 285 286 writel(addr & 0x00000000FFFFFFFF, 287 chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); 288 writel(addr >> 32, 289 chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); 290 } 291 292 static inline bool is_ioat_active(unsigned long status) 293 { 294 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 295 } 296 297 static inline bool is_ioat_idle(unsigned long status) 298 { 299 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 300 } 301 302 static inline bool is_ioat_halted(unsigned long status) 303 { 304 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 305 } 306 307 static inline bool is_ioat_suspended(unsigned long status) 308 { 309 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 310 } 311 312 /* channel was fatally programmed */ 313 static inline bool is_ioat_bug(unsigned long err) 314 { 315 return !!err; 316 } 317 318 static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, 319 int direction, enum dma_ctrl_flags flags, bool dst) 320 { 321 if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || 322 (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) 323 pci_unmap_single(pdev, addr, len, direction); 324 else 325 pci_unmap_page(pdev, addr, len, direction); 326 } 327 328 int __devinit ioat_probe(struct ioatdma_device *device); 329 int __devinit ioat_register(struct ioatdma_device *device); 330 int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca); 331 int __devinit ioat_dma_self_test(struct ioatdma_device *device); 332 void __devexit ioat_dma_remove(struct ioatdma_device *device); 333 struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev, 334 void __iomem *iobase); 335 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan); 336 void ioat_init_channel(struct ioatdma_device *device, 337 struct ioat_chan_common *chan, int idx); 338 enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, 339 struct dma_tx_state *txstate); 340 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, 341 size_t len, struct ioat_dma_descriptor *hw); 342 bool ioat_cleanup_preamble(struct ioat_chan_common *chan, 343 unsigned long *phys_complete); 344 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type); 345 void ioat_kobject_del(struct ioatdma_device *device); 346 extern const struct sysfs_ops ioat_sysfs_ops; 347 extern struct ioat_sysfs_entry ioat_version_attr; 348 extern struct ioat_sysfs_entry ioat_cap_attr; 349 #endif /* IOATDMA_H */ 350