1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef IOATDMA_H 22 #define IOATDMA_H 23 24 #include <linux/dmaengine.h> 25 #include "hw.h" 26 #include "registers.h" 27 #include <linux/init.h> 28 #include <linux/dmapool.h> 29 #include <linux/cache.h> 30 #include <linux/pci_ids.h> 31 #include <net/tcp.h> 32 33 #define IOAT_DMA_VERSION "4.00" 34 35 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 36 #define IOAT_DMA_DCA_ANY_CPU ~0 37 38 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) 39 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) 40 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd) 41 #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev) 42 43 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) 44 45 /* 46 * workaround for IOAT ver.3.0 null descriptor issue 47 * (channel returns error when size is 0) 48 */ 49 #define NULL_DESC_BUFFER_SIZE 1 50 51 /** 52 * struct ioatdma_device - internal representation of a IOAT device 53 * @pdev: PCI-Express device 54 * @reg_base: MMIO register space base address 55 * @dma_pool: for allocating DMA descriptors 56 * @common: embedded struct dma_device 57 * @version: version of ioatdma device 58 * @msix_entries: irq handlers 59 * @idx: per channel data 60 * @dca: direct cache access context 61 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) 62 * @enumerate_channels: hw version specific channel enumeration 63 * @reset_hw: hw version specific channel (re)initialization 64 * @cleanup_fn: select between the v2 and v3 cleanup routines 65 * @timer_fn: select between the v2 and v3 timer watchdog routines 66 * @self_test: hardware version specific self test for each supported op type 67 * 68 * Note: the v3 cleanup routine supports raid operations 69 */ 70 struct ioatdma_device { 71 struct pci_dev *pdev; 72 void __iomem *reg_base; 73 struct pci_pool *dma_pool; 74 struct pci_pool *completion_pool; 75 struct dma_device common; 76 u8 version; 77 struct msix_entry msix_entries[4]; 78 struct ioat_chan_common *idx[4]; 79 struct dca_provider *dca; 80 void (*intr_quirk)(struct ioatdma_device *device); 81 int (*enumerate_channels)(struct ioatdma_device *device); 82 int (*reset_hw)(struct ioat_chan_common *chan); 83 void (*cleanup_fn)(unsigned long data); 84 void (*timer_fn)(unsigned long data); 85 int (*self_test)(struct ioatdma_device *device); 86 }; 87 88 struct ioat_chan_common { 89 struct dma_chan common; 90 void __iomem *reg_base; 91 unsigned long last_completion; 92 spinlock_t cleanup_lock; 93 dma_cookie_t completed_cookie; 94 unsigned long state; 95 #define IOAT_COMPLETION_PENDING 0 96 #define IOAT_COMPLETION_ACK 1 97 #define IOAT_RESET_PENDING 2 98 #define IOAT_KOBJ_INIT_FAIL 3 99 struct timer_list timer; 100 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 101 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 102 #define RESET_DELAY msecs_to_jiffies(100) 103 struct ioatdma_device *device; 104 dma_addr_t completion_dma; 105 u64 *completion; 106 struct tasklet_struct cleanup_task; 107 struct kobject kobj; 108 }; 109 110 struct ioat_sysfs_entry { 111 struct attribute attr; 112 ssize_t (*show)(struct dma_chan *, char *); 113 }; 114 115 /** 116 * struct ioat_dma_chan - internal representation of a DMA channel 117 */ 118 struct ioat_dma_chan { 119 struct ioat_chan_common base; 120 121 size_t xfercap; /* XFERCAP register value expanded out */ 122 123 spinlock_t desc_lock; 124 struct list_head free_desc; 125 struct list_head used_desc; 126 127 int pending; 128 u16 desccount; 129 u16 active; 130 }; 131 132 static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) 133 { 134 return container_of(c, struct ioat_chan_common, common); 135 } 136 137 static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c) 138 { 139 struct ioat_chan_common *chan = to_chan_common(c); 140 141 return container_of(chan, struct ioat_dma_chan, base); 142 } 143 144 /** 145 * ioat_is_complete - poll the status of an ioat transaction 146 * @c: channel handle 147 * @cookie: transaction identifier 148 * @done: if set, updated with last completed transaction 149 * @used: if set, updated with last used transaction 150 */ 151 static inline enum dma_status 152 ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie, 153 dma_cookie_t *done, dma_cookie_t *used) 154 { 155 struct ioat_chan_common *chan = to_chan_common(c); 156 dma_cookie_t last_used; 157 dma_cookie_t last_complete; 158 159 last_used = c->cookie; 160 last_complete = chan->completed_cookie; 161 162 if (done) 163 *done = last_complete; 164 if (used) 165 *used = last_used; 166 167 return dma_async_is_complete(cookie, last_complete, last_used); 168 } 169 170 /* wrapper around hardware descriptor format + additional software fields */ 171 172 /** 173 * struct ioat_desc_sw - wrapper around hardware descriptor 174 * @hw: hardware DMA descriptor (for memcpy) 175 * @node: this descriptor will either be on the free list, 176 * or attached to a transaction list (tx_list) 177 * @txd: the generic software descriptor for all engines 178 * @id: identifier for debug 179 */ 180 struct ioat_desc_sw { 181 struct ioat_dma_descriptor *hw; 182 struct list_head node; 183 size_t len; 184 struct list_head tx_list; 185 struct dma_async_tx_descriptor txd; 186 #ifdef DEBUG 187 int id; 188 #endif 189 }; 190 191 #ifdef DEBUG 192 #define set_desc_id(desc, i) ((desc)->id = (i)) 193 #define desc_id(desc) ((desc)->id) 194 #else 195 #define set_desc_id(desc, i) 196 #define desc_id(desc) (0) 197 #endif 198 199 static inline void 200 __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw, 201 struct dma_async_tx_descriptor *tx, int id) 202 { 203 struct device *dev = to_dev(chan); 204 205 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 206 " ctl: %#x (op: %d int_en: %d compl: %d)\n", id, 207 (unsigned long long) tx->phys, 208 (unsigned long long) hw->next, tx->cookie, tx->flags, 209 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 210 } 211 212 #define dump_desc_dbg(c, d) \ 213 ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; }) 214 215 static inline void ioat_set_tcp_copy_break(unsigned long copybreak) 216 { 217 #ifdef CONFIG_NET_DMA 218 sysctl_tcp_dma_copybreak = copybreak; 219 #endif 220 } 221 222 static inline struct ioat_chan_common * 223 ioat_chan_by_index(struct ioatdma_device *device, int index) 224 { 225 return device->idx[index]; 226 } 227 228 static inline u64 ioat_chansts(struct ioat_chan_common *chan) 229 { 230 u8 ver = chan->device->version; 231 u64 status; 232 u32 status_lo; 233 234 /* We need to read the low address first as this causes the 235 * chipset to latch the upper bits for the subsequent read 236 */ 237 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); 238 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); 239 status <<= 32; 240 status |= status_lo; 241 242 return status; 243 } 244 245 static inline void ioat_start(struct ioat_chan_common *chan) 246 { 247 u8 ver = chan->device->version; 248 249 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 250 } 251 252 static inline u64 ioat_chansts_to_addr(u64 status) 253 { 254 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 255 } 256 257 static inline u32 ioat_chanerr(struct ioat_chan_common *chan) 258 { 259 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); 260 } 261 262 static inline void ioat_suspend(struct ioat_chan_common *chan) 263 { 264 u8 ver = chan->device->version; 265 266 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 267 } 268 269 static inline void ioat_reset(struct ioat_chan_common *chan) 270 { 271 u8 ver = chan->device->version; 272 273 writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 274 } 275 276 static inline bool ioat_reset_pending(struct ioat_chan_common *chan) 277 { 278 u8 ver = chan->device->version; 279 u8 cmd; 280 281 cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 282 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; 283 } 284 285 static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr) 286 { 287 struct ioat_chan_common *chan = &ioat->base; 288 289 writel(addr & 0x00000000FFFFFFFF, 290 chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); 291 writel(addr >> 32, 292 chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); 293 } 294 295 static inline bool is_ioat_active(unsigned long status) 296 { 297 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 298 } 299 300 static inline bool is_ioat_idle(unsigned long status) 301 { 302 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 303 } 304 305 static inline bool is_ioat_halted(unsigned long status) 306 { 307 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 308 } 309 310 static inline bool is_ioat_suspended(unsigned long status) 311 { 312 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 313 } 314 315 /* channel was fatally programmed */ 316 static inline bool is_ioat_bug(unsigned long err) 317 { 318 return !!err; 319 } 320 321 static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, 322 int direction, enum dma_ctrl_flags flags, bool dst) 323 { 324 if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || 325 (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) 326 pci_unmap_single(pdev, addr, len, direction); 327 else 328 pci_unmap_page(pdev, addr, len, direction); 329 } 330 331 int __devinit ioat_probe(struct ioatdma_device *device); 332 int __devinit ioat_register(struct ioatdma_device *device); 333 int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca); 334 int __devinit ioat_dma_self_test(struct ioatdma_device *device); 335 void __devexit ioat_dma_remove(struct ioatdma_device *device); 336 struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev, 337 void __iomem *iobase); 338 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan); 339 void ioat_init_channel(struct ioatdma_device *device, 340 struct ioat_chan_common *chan, int idx); 341 enum dma_status ioat_is_dma_complete(struct dma_chan *c, dma_cookie_t cookie, 342 dma_cookie_t *done, dma_cookie_t *used); 343 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, 344 size_t len, struct ioat_dma_descriptor *hw); 345 bool ioat_cleanup_preamble(struct ioat_chan_common *chan, 346 unsigned long *phys_complete); 347 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type); 348 void ioat_kobject_del(struct ioatdma_device *device); 349 extern const struct sysfs_ops ioat_sysfs_ops; 350 extern struct ioat_sysfs_entry ioat_version_attr; 351 extern struct ioat_sysfs_entry ioat_cap_attr; 352 #endif /* IOATDMA_H */ 353