1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/slab.h> 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/workqueue.h> 12 #include <linux/fs.h> 13 #include <linux/io-64-nonatomic-lo-hi.h> 14 #include <linux/device.h> 15 #include <linux/idr.h> 16 #include <linux/iommu.h> 17 #include <uapi/linux/idxd.h> 18 #include <linux/dmaengine.h> 19 #include "../dmaengine.h" 20 #include "registers.h" 21 #include "idxd.h" 22 #include "perfmon.h" 23 24 MODULE_VERSION(IDXD_DRIVER_VERSION); 25 MODULE_LICENSE("GPL v2"); 26 MODULE_AUTHOR("Intel Corporation"); 27 MODULE_IMPORT_NS(IDXD); 28 29 static bool sva = true; 30 module_param(sva, bool, 0644); 31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off"); 32 33 bool tc_override; 34 module_param(tc_override, bool, 0644); 35 MODULE_PARM_DESC(tc_override, "Override traffic class defaults"); 36 37 #define DRV_NAME "idxd" 38 39 bool support_enqcmd; 40 DEFINE_IDA(idxd_ida); 41 42 static struct idxd_driver_data idxd_driver_data[] = { 43 [IDXD_TYPE_DSA] = { 44 .name_prefix = "dsa", 45 .type = IDXD_TYPE_DSA, 46 .compl_size = sizeof(struct dsa_completion_record), 47 .align = 32, 48 .dev_type = &dsa_device_type, 49 .evl_cr_off = offsetof(struct dsa_evl_entry, cr), 50 .cr_status_off = offsetof(struct dsa_completion_record, status), 51 .cr_result_off = offsetof(struct dsa_completion_record, result), 52 }, 53 [IDXD_TYPE_IAX] = { 54 .name_prefix = "iax", 55 .type = IDXD_TYPE_IAX, 56 .compl_size = sizeof(struct iax_completion_record), 57 .align = 64, 58 .dev_type = &iax_device_type, 59 .evl_cr_off = offsetof(struct iax_evl_entry, cr), 60 .cr_status_off = offsetof(struct iax_completion_record, status), 61 .cr_result_off = offsetof(struct iax_completion_record, error_code), 62 .load_device_defaults = idxd_load_iaa_device_defaults, 63 }, 64 }; 65 66 static struct pci_device_id idxd_pci_tbl[] = { 67 /* DSA ver 1.0 platforms */ 68 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) }, 69 70 /* IAX ver 1.0 platforms */ 71 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) }, 72 { 0, } 73 }; 74 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl); 75 76 static int idxd_setup_interrupts(struct idxd_device *idxd) 77 { 78 struct pci_dev *pdev = idxd->pdev; 79 struct device *dev = &pdev->dev; 80 struct idxd_irq_entry *ie; 81 int i, msixcnt; 82 int rc = 0; 83 84 msixcnt = pci_msix_vec_count(pdev); 85 if (msixcnt < 0) { 86 dev_err(dev, "Not MSI-X interrupt capable.\n"); 87 return -ENOSPC; 88 } 89 idxd->irq_cnt = msixcnt; 90 91 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX); 92 if (rc != msixcnt) { 93 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc); 94 return -ENOSPC; 95 } 96 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt); 97 98 99 ie = idxd_get_ie(idxd, 0); 100 ie->vector = pci_irq_vector(pdev, 0); 101 rc = request_threaded_irq(ie->vector, NULL, idxd_misc_thread, 0, "idxd-misc", ie); 102 if (rc < 0) { 103 dev_err(dev, "Failed to allocate misc interrupt.\n"); 104 goto err_misc_irq; 105 } 106 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector); 107 108 for (i = 0; i < idxd->max_wqs; i++) { 109 int msix_idx = i + 1; 110 111 ie = idxd_get_ie(idxd, msix_idx); 112 ie->id = msix_idx; 113 ie->int_handle = INVALID_INT_HANDLE; 114 ie->pasid = IOMMU_PASID_INVALID; 115 116 spin_lock_init(&ie->list_lock); 117 init_llist_head(&ie->pending_llist); 118 INIT_LIST_HEAD(&ie->work_list); 119 } 120 121 idxd_unmask_error_interrupts(idxd); 122 return 0; 123 124 err_misc_irq: 125 idxd_mask_error_interrupts(idxd); 126 pci_free_irq_vectors(pdev); 127 dev_err(dev, "No usable interrupts\n"); 128 return rc; 129 } 130 131 static void idxd_cleanup_interrupts(struct idxd_device *idxd) 132 { 133 struct pci_dev *pdev = idxd->pdev; 134 struct idxd_irq_entry *ie; 135 int msixcnt; 136 137 msixcnt = pci_msix_vec_count(pdev); 138 if (msixcnt <= 0) 139 return; 140 141 ie = idxd_get_ie(idxd, 0); 142 idxd_mask_error_interrupts(idxd); 143 free_irq(ie->vector, ie); 144 pci_free_irq_vectors(pdev); 145 } 146 147 static int idxd_setup_wqs(struct idxd_device *idxd) 148 { 149 struct device *dev = &idxd->pdev->dev; 150 struct idxd_wq *wq; 151 struct device *conf_dev; 152 int i, rc; 153 154 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *), 155 GFP_KERNEL, dev_to_node(dev)); 156 if (!idxd->wqs) 157 return -ENOMEM; 158 159 idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev)); 160 if (!idxd->wq_enable_map) { 161 kfree(idxd->wqs); 162 return -ENOMEM; 163 } 164 165 for (i = 0; i < idxd->max_wqs; i++) { 166 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev)); 167 if (!wq) { 168 rc = -ENOMEM; 169 goto err; 170 } 171 172 idxd_dev_set_type(&wq->idxd_dev, IDXD_DEV_WQ); 173 conf_dev = wq_confdev(wq); 174 wq->id = i; 175 wq->idxd = idxd; 176 device_initialize(wq_confdev(wq)); 177 conf_dev->parent = idxd_confdev(idxd); 178 conf_dev->bus = &dsa_bus_type; 179 conf_dev->type = &idxd_wq_device_type; 180 rc = dev_set_name(conf_dev, "wq%d.%d", idxd->id, wq->id); 181 if (rc < 0) { 182 put_device(conf_dev); 183 goto err; 184 } 185 186 mutex_init(&wq->wq_lock); 187 init_waitqueue_head(&wq->err_queue); 188 init_completion(&wq->wq_dead); 189 init_completion(&wq->wq_resurrect); 190 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 191 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 192 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 193 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev)); 194 if (!wq->wqcfg) { 195 put_device(conf_dev); 196 rc = -ENOMEM; 197 goto err; 198 } 199 200 if (idxd->hw.wq_cap.op_config) { 201 wq->opcap_bmap = bitmap_zalloc(IDXD_MAX_OPCAP_BITS, GFP_KERNEL); 202 if (!wq->opcap_bmap) { 203 put_device(conf_dev); 204 rc = -ENOMEM; 205 goto err; 206 } 207 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 208 } 209 mutex_init(&wq->uc_lock); 210 xa_init(&wq->upasid_xa); 211 idxd->wqs[i] = wq; 212 } 213 214 return 0; 215 216 err: 217 while (--i >= 0) { 218 wq = idxd->wqs[i]; 219 conf_dev = wq_confdev(wq); 220 put_device(conf_dev); 221 } 222 return rc; 223 } 224 225 static int idxd_setup_engines(struct idxd_device *idxd) 226 { 227 struct idxd_engine *engine; 228 struct device *dev = &idxd->pdev->dev; 229 struct device *conf_dev; 230 int i, rc; 231 232 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *), 233 GFP_KERNEL, dev_to_node(dev)); 234 if (!idxd->engines) 235 return -ENOMEM; 236 237 for (i = 0; i < idxd->max_engines; i++) { 238 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev)); 239 if (!engine) { 240 rc = -ENOMEM; 241 goto err; 242 } 243 244 idxd_dev_set_type(&engine->idxd_dev, IDXD_DEV_ENGINE); 245 conf_dev = engine_confdev(engine); 246 engine->id = i; 247 engine->idxd = idxd; 248 device_initialize(conf_dev); 249 conf_dev->parent = idxd_confdev(idxd); 250 conf_dev->bus = &dsa_bus_type; 251 conf_dev->type = &idxd_engine_device_type; 252 rc = dev_set_name(conf_dev, "engine%d.%d", idxd->id, engine->id); 253 if (rc < 0) { 254 put_device(conf_dev); 255 goto err; 256 } 257 258 idxd->engines[i] = engine; 259 } 260 261 return 0; 262 263 err: 264 while (--i >= 0) { 265 engine = idxd->engines[i]; 266 conf_dev = engine_confdev(engine); 267 put_device(conf_dev); 268 } 269 return rc; 270 } 271 272 static int idxd_setup_groups(struct idxd_device *idxd) 273 { 274 struct device *dev = &idxd->pdev->dev; 275 struct device *conf_dev; 276 struct idxd_group *group; 277 int i, rc; 278 279 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *), 280 GFP_KERNEL, dev_to_node(dev)); 281 if (!idxd->groups) 282 return -ENOMEM; 283 284 for (i = 0; i < idxd->max_groups; i++) { 285 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev)); 286 if (!group) { 287 rc = -ENOMEM; 288 goto err; 289 } 290 291 idxd_dev_set_type(&group->idxd_dev, IDXD_DEV_GROUP); 292 conf_dev = group_confdev(group); 293 group->id = i; 294 group->idxd = idxd; 295 device_initialize(conf_dev); 296 conf_dev->parent = idxd_confdev(idxd); 297 conf_dev->bus = &dsa_bus_type; 298 conf_dev->type = &idxd_group_device_type; 299 rc = dev_set_name(conf_dev, "group%d.%d", idxd->id, group->id); 300 if (rc < 0) { 301 put_device(conf_dev); 302 goto err; 303 } 304 305 idxd->groups[i] = group; 306 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) { 307 group->tc_a = 1; 308 group->tc_b = 1; 309 } else { 310 group->tc_a = -1; 311 group->tc_b = -1; 312 } 313 /* 314 * The default value is the same as the value of 315 * total read buffers in GRPCAP. 316 */ 317 group->rdbufs_allowed = idxd->max_rdbufs; 318 } 319 320 return 0; 321 322 err: 323 while (--i >= 0) { 324 group = idxd->groups[i]; 325 put_device(group_confdev(group)); 326 } 327 return rc; 328 } 329 330 static void idxd_cleanup_internals(struct idxd_device *idxd) 331 { 332 int i; 333 334 for (i = 0; i < idxd->max_groups; i++) 335 put_device(group_confdev(idxd->groups[i])); 336 for (i = 0; i < idxd->max_engines; i++) 337 put_device(engine_confdev(idxd->engines[i])); 338 for (i = 0; i < idxd->max_wqs; i++) 339 put_device(wq_confdev(idxd->wqs[i])); 340 destroy_workqueue(idxd->wq); 341 } 342 343 static int idxd_init_evl(struct idxd_device *idxd) 344 { 345 struct device *dev = &idxd->pdev->dev; 346 struct idxd_evl *evl; 347 348 if (idxd->hw.gen_cap.evl_support == 0) 349 return 0; 350 351 evl = kzalloc_node(sizeof(*evl), GFP_KERNEL, dev_to_node(dev)); 352 if (!evl) 353 return -ENOMEM; 354 355 spin_lock_init(&evl->lock); 356 evl->size = IDXD_EVL_SIZE_MIN; 357 358 idxd->evl_cache = kmem_cache_create(dev_name(idxd_confdev(idxd)), 359 sizeof(struct idxd_evl_fault) + evl_ent_size(idxd), 360 0, 0, NULL); 361 if (!idxd->evl_cache) { 362 kfree(evl); 363 return -ENOMEM; 364 } 365 366 idxd->evl = evl; 367 return 0; 368 } 369 370 static int idxd_setup_internals(struct idxd_device *idxd) 371 { 372 struct device *dev = &idxd->pdev->dev; 373 int rc, i; 374 375 init_waitqueue_head(&idxd->cmd_waitq); 376 377 rc = idxd_setup_wqs(idxd); 378 if (rc < 0) 379 goto err_wqs; 380 381 rc = idxd_setup_engines(idxd); 382 if (rc < 0) 383 goto err_engine; 384 385 rc = idxd_setup_groups(idxd); 386 if (rc < 0) 387 goto err_group; 388 389 idxd->wq = create_workqueue(dev_name(dev)); 390 if (!idxd->wq) { 391 rc = -ENOMEM; 392 goto err_wkq_create; 393 } 394 395 rc = idxd_init_evl(idxd); 396 if (rc < 0) 397 goto err_evl; 398 399 return 0; 400 401 err_evl: 402 destroy_workqueue(idxd->wq); 403 err_wkq_create: 404 for (i = 0; i < idxd->max_groups; i++) 405 put_device(group_confdev(idxd->groups[i])); 406 err_group: 407 for (i = 0; i < idxd->max_engines; i++) 408 put_device(engine_confdev(idxd->engines[i])); 409 err_engine: 410 for (i = 0; i < idxd->max_wqs; i++) 411 put_device(wq_confdev(idxd->wqs[i])); 412 err_wqs: 413 return rc; 414 } 415 416 static void idxd_read_table_offsets(struct idxd_device *idxd) 417 { 418 union offsets_reg offsets; 419 struct device *dev = &idxd->pdev->dev; 420 421 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET); 422 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64)); 423 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT; 424 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset); 425 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT; 426 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset); 427 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT; 428 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset); 429 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT; 430 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset); 431 } 432 433 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count) 434 { 435 int i, j, nr; 436 437 for (i = 0, nr = 0; i < count; i++) { 438 for (j = 0; j < BITS_PER_LONG_LONG; j++) { 439 if (val[i] & BIT(j)) 440 set_bit(nr, bmap); 441 nr++; 442 } 443 } 444 } 445 446 static void idxd_read_caps(struct idxd_device *idxd) 447 { 448 struct device *dev = &idxd->pdev->dev; 449 int i; 450 451 /* reading generic capabilities */ 452 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET); 453 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits); 454 455 if (idxd->hw.gen_cap.cmd_cap) { 456 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET); 457 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap); 458 } 459 460 /* reading command capabilities */ 461 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) 462 idxd->request_int_handles = true; 463 464 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift; 465 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes); 466 idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift); 467 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size); 468 if (idxd->hw.gen_cap.config_en) 469 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags); 470 471 /* reading group capabilities */ 472 idxd->hw.group_cap.bits = 473 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET); 474 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits); 475 idxd->max_groups = idxd->hw.group_cap.num_groups; 476 dev_dbg(dev, "max groups: %u\n", idxd->max_groups); 477 idxd->max_rdbufs = idxd->hw.group_cap.total_rdbufs; 478 dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs); 479 idxd->nr_rdbufs = idxd->max_rdbufs; 480 481 /* read engine capabilities */ 482 idxd->hw.engine_cap.bits = 483 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET); 484 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits); 485 idxd->max_engines = idxd->hw.engine_cap.num_engines; 486 dev_dbg(dev, "max engines: %u\n", idxd->max_engines); 487 488 /* read workqueue capabilities */ 489 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET); 490 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits); 491 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size; 492 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size); 493 idxd->max_wqs = idxd->hw.wq_cap.num_wqs; 494 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs); 495 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN); 496 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size); 497 498 /* reading operation capabilities */ 499 for (i = 0; i < 4; i++) { 500 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base + 501 IDXD_OPCAP_OFFSET + i * sizeof(u64)); 502 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]); 503 } 504 multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4); 505 506 /* read iaa cap */ 507 if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2) 508 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET); 509 } 510 511 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data) 512 { 513 struct device *dev = &pdev->dev; 514 struct device *conf_dev; 515 struct idxd_device *idxd; 516 int rc; 517 518 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev)); 519 if (!idxd) 520 return NULL; 521 522 conf_dev = idxd_confdev(idxd); 523 idxd->pdev = pdev; 524 idxd->data = data; 525 idxd_dev_set_type(&idxd->idxd_dev, idxd->data->type); 526 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL); 527 if (idxd->id < 0) 528 return NULL; 529 530 idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev)); 531 if (!idxd->opcap_bmap) { 532 ida_free(&idxd_ida, idxd->id); 533 return NULL; 534 } 535 536 device_initialize(conf_dev); 537 conf_dev->parent = dev; 538 conf_dev->bus = &dsa_bus_type; 539 conf_dev->type = idxd->data->dev_type; 540 rc = dev_set_name(conf_dev, "%s%d", idxd->data->name_prefix, idxd->id); 541 if (rc < 0) { 542 put_device(conf_dev); 543 return NULL; 544 } 545 546 spin_lock_init(&idxd->dev_lock); 547 spin_lock_init(&idxd->cmd_lock); 548 549 return idxd; 550 } 551 552 static int idxd_enable_system_pasid(struct idxd_device *idxd) 553 { 554 struct pci_dev *pdev = idxd->pdev; 555 struct device *dev = &pdev->dev; 556 struct iommu_domain *domain; 557 ioasid_t pasid; 558 int ret; 559 560 /* 561 * Attach a global PASID to the DMA domain so that we can use ENQCMDS 562 * to submit work on buffers mapped by DMA API. 563 */ 564 domain = iommu_get_domain_for_dev(dev); 565 if (!domain) 566 return -EPERM; 567 568 pasid = iommu_alloc_global_pasid(dev); 569 if (pasid == IOMMU_PASID_INVALID) 570 return -ENOSPC; 571 572 /* 573 * DMA domain is owned by the driver, it should support all valid 574 * types such as DMA-FQ, identity, etc. 575 */ 576 ret = iommu_attach_device_pasid(domain, dev, pasid); 577 if (ret) { 578 dev_err(dev, "failed to attach device pasid %d, domain type %d", 579 pasid, domain->type); 580 iommu_free_global_pasid(pasid); 581 return ret; 582 } 583 584 /* Since we set user privilege for kernel DMA, enable completion IRQ */ 585 idxd_set_user_intr(idxd, 1); 586 idxd->pasid = pasid; 587 588 return ret; 589 } 590 591 static void idxd_disable_system_pasid(struct idxd_device *idxd) 592 { 593 struct pci_dev *pdev = idxd->pdev; 594 struct device *dev = &pdev->dev; 595 struct iommu_domain *domain; 596 597 domain = iommu_get_domain_for_dev(dev); 598 if (!domain) 599 return; 600 601 iommu_detach_device_pasid(domain, dev, idxd->pasid); 602 iommu_free_global_pasid(idxd->pasid); 603 604 idxd_set_user_intr(idxd, 0); 605 idxd->sva = NULL; 606 idxd->pasid = IOMMU_PASID_INVALID; 607 } 608 609 static int idxd_enable_sva(struct pci_dev *pdev) 610 { 611 int ret; 612 613 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF); 614 if (ret) 615 return ret; 616 617 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA); 618 if (ret) 619 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF); 620 621 return ret; 622 } 623 624 static void idxd_disable_sva(struct pci_dev *pdev) 625 { 626 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA); 627 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF); 628 } 629 630 static int idxd_probe(struct idxd_device *idxd) 631 { 632 struct pci_dev *pdev = idxd->pdev; 633 struct device *dev = &pdev->dev; 634 int rc; 635 636 dev_dbg(dev, "%s entered and resetting device\n", __func__); 637 rc = idxd_device_init_reset(idxd); 638 if (rc < 0) 639 return rc; 640 641 dev_dbg(dev, "IDXD reset complete\n"); 642 643 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) { 644 if (idxd_enable_sva(pdev)) { 645 dev_warn(dev, "Unable to turn on user SVA feature.\n"); 646 } else { 647 set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags); 648 649 rc = idxd_enable_system_pasid(idxd); 650 if (rc) 651 dev_warn(dev, "No in-kernel DMA with PASID. %d\n", rc); 652 else 653 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 654 } 655 } else if (!sva) { 656 dev_warn(dev, "User forced SVA off via module param.\n"); 657 } 658 659 idxd_read_caps(idxd); 660 idxd_read_table_offsets(idxd); 661 662 rc = idxd_setup_internals(idxd); 663 if (rc) 664 goto err; 665 666 /* If the configs are readonly, then load them from device */ 667 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 668 dev_dbg(dev, "Loading RO device config\n"); 669 rc = idxd_device_load_config(idxd); 670 if (rc < 0) 671 goto err_config; 672 } 673 674 rc = idxd_setup_interrupts(idxd); 675 if (rc) 676 goto err_config; 677 678 idxd->major = idxd_cdev_get_major(idxd); 679 680 rc = perfmon_pmu_init(idxd); 681 if (rc < 0) 682 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc); 683 684 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id); 685 return 0; 686 687 err_config: 688 idxd_cleanup_internals(idxd); 689 err: 690 if (device_pasid_enabled(idxd)) 691 idxd_disable_system_pasid(idxd); 692 if (device_user_pasid_enabled(idxd)) 693 idxd_disable_sva(pdev); 694 return rc; 695 } 696 697 static void idxd_cleanup(struct idxd_device *idxd) 698 { 699 perfmon_pmu_remove(idxd); 700 idxd_cleanup_interrupts(idxd); 701 idxd_cleanup_internals(idxd); 702 if (device_pasid_enabled(idxd)) 703 idxd_disable_system_pasid(idxd); 704 if (device_user_pasid_enabled(idxd)) 705 idxd_disable_sva(idxd->pdev); 706 } 707 708 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 709 { 710 struct device *dev = &pdev->dev; 711 struct idxd_device *idxd; 712 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data; 713 int rc; 714 715 rc = pci_enable_device(pdev); 716 if (rc) 717 return rc; 718 719 dev_dbg(dev, "Alloc IDXD context\n"); 720 idxd = idxd_alloc(pdev, data); 721 if (!idxd) { 722 rc = -ENOMEM; 723 goto err_idxd_alloc; 724 } 725 726 dev_dbg(dev, "Mapping BARs\n"); 727 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0); 728 if (!idxd->reg_base) { 729 rc = -ENOMEM; 730 goto err_iomap; 731 } 732 733 dev_dbg(dev, "Set DMA masks\n"); 734 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 735 if (rc) 736 goto err; 737 738 dev_dbg(dev, "Set PCI master\n"); 739 pci_set_master(pdev); 740 pci_set_drvdata(pdev, idxd); 741 742 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET); 743 rc = idxd_probe(idxd); 744 if (rc) { 745 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n"); 746 goto err; 747 } 748 749 if (data->load_device_defaults) { 750 rc = data->load_device_defaults(idxd); 751 if (rc) 752 dev_warn(dev, "IDXD loading device defaults failed\n"); 753 } 754 755 rc = idxd_register_devices(idxd); 756 if (rc) { 757 dev_err(dev, "IDXD sysfs setup failed\n"); 758 goto err_dev_register; 759 } 760 761 rc = idxd_device_init_debugfs(idxd); 762 if (rc) 763 dev_warn(dev, "IDXD debugfs failed to setup\n"); 764 765 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n", 766 idxd->hw.version); 767 768 return 0; 769 770 err_dev_register: 771 idxd_cleanup(idxd); 772 err: 773 pci_iounmap(pdev, idxd->reg_base); 774 err_iomap: 775 put_device(idxd_confdev(idxd)); 776 err_idxd_alloc: 777 pci_disable_device(pdev); 778 return rc; 779 } 780 781 void idxd_wqs_quiesce(struct idxd_device *idxd) 782 { 783 struct idxd_wq *wq; 784 int i; 785 786 for (i = 0; i < idxd->max_wqs; i++) { 787 wq = idxd->wqs[i]; 788 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL) 789 idxd_wq_quiesce(wq); 790 } 791 } 792 793 static void idxd_shutdown(struct pci_dev *pdev) 794 { 795 struct idxd_device *idxd = pci_get_drvdata(pdev); 796 struct idxd_irq_entry *irq_entry; 797 int rc; 798 799 rc = idxd_device_disable(idxd); 800 if (rc) 801 dev_err(&pdev->dev, "Disabling device failed\n"); 802 803 irq_entry = &idxd->ie; 804 synchronize_irq(irq_entry->vector); 805 idxd_mask_error_interrupts(idxd); 806 flush_workqueue(idxd->wq); 807 } 808 809 static void idxd_remove(struct pci_dev *pdev) 810 { 811 struct idxd_device *idxd = pci_get_drvdata(pdev); 812 struct idxd_irq_entry *irq_entry; 813 814 idxd_unregister_devices(idxd); 815 /* 816 * When ->release() is called for the idxd->conf_dev, it frees all the memory related 817 * to the idxd context. The driver still needs those bits in order to do the rest of 818 * the cleanup. However, we do need to unbound the idxd sub-driver. So take a ref 819 * on the device here to hold off the freeing while allowing the idxd sub-driver 820 * to unbind. 821 */ 822 get_device(idxd_confdev(idxd)); 823 device_unregister(idxd_confdev(idxd)); 824 idxd_shutdown(pdev); 825 if (device_pasid_enabled(idxd)) 826 idxd_disable_system_pasid(idxd); 827 idxd_device_remove_debugfs(idxd); 828 829 irq_entry = idxd_get_ie(idxd, 0); 830 free_irq(irq_entry->vector, irq_entry); 831 pci_free_irq_vectors(pdev); 832 pci_iounmap(pdev, idxd->reg_base); 833 if (device_user_pasid_enabled(idxd)) 834 idxd_disable_sva(pdev); 835 pci_disable_device(pdev); 836 destroy_workqueue(idxd->wq); 837 perfmon_pmu_remove(idxd); 838 put_device(idxd_confdev(idxd)); 839 } 840 841 static struct pci_driver idxd_pci_driver = { 842 .name = DRV_NAME, 843 .id_table = idxd_pci_tbl, 844 .probe = idxd_pci_probe, 845 .remove = idxd_remove, 846 .shutdown = idxd_shutdown, 847 }; 848 849 static int __init idxd_init_module(void) 850 { 851 int err; 852 853 /* 854 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in 855 * enumerating the device. We can not utilize it. 856 */ 857 if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) { 858 pr_warn("idxd driver failed to load without MOVDIR64B.\n"); 859 return -ENODEV; 860 } 861 862 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) 863 pr_warn("Platform does not have ENQCMD(S) support.\n"); 864 else 865 support_enqcmd = true; 866 867 perfmon_init(); 868 869 err = idxd_driver_register(&idxd_drv); 870 if (err < 0) 871 goto err_idxd_driver_register; 872 873 err = idxd_driver_register(&idxd_dmaengine_drv); 874 if (err < 0) 875 goto err_idxd_dmaengine_driver_register; 876 877 err = idxd_driver_register(&idxd_user_drv); 878 if (err < 0) 879 goto err_idxd_user_driver_register; 880 881 err = idxd_cdev_register(); 882 if (err) 883 goto err_cdev_register; 884 885 err = idxd_init_debugfs(); 886 if (err) 887 goto err_debugfs; 888 889 err = pci_register_driver(&idxd_pci_driver); 890 if (err) 891 goto err_pci_register; 892 893 return 0; 894 895 err_pci_register: 896 idxd_remove_debugfs(); 897 err_debugfs: 898 idxd_cdev_remove(); 899 err_cdev_register: 900 idxd_driver_unregister(&idxd_user_drv); 901 err_idxd_user_driver_register: 902 idxd_driver_unregister(&idxd_dmaengine_drv); 903 err_idxd_dmaengine_driver_register: 904 idxd_driver_unregister(&idxd_drv); 905 err_idxd_driver_register: 906 return err; 907 } 908 module_init(idxd_init_module); 909 910 static void __exit idxd_exit_module(void) 911 { 912 idxd_driver_unregister(&idxd_user_drv); 913 idxd_driver_unregister(&idxd_dmaengine_drv); 914 idxd_driver_unregister(&idxd_drv); 915 pci_unregister_driver(&idxd_pci_driver); 916 idxd_cdev_remove(); 917 perfmon_exit(); 918 idxd_remove_debugfs(); 919 } 920 module_exit(idxd_exit_module); 921