1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/slab.h> 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/workqueue.h> 12 #include <linux/aer.h> 13 #include <linux/fs.h> 14 #include <linux/io-64-nonatomic-lo-hi.h> 15 #include <linux/device.h> 16 #include <linux/idr.h> 17 #include <linux/intel-svm.h> 18 #include <linux/iommu.h> 19 #include <uapi/linux/idxd.h> 20 #include <linux/dmaengine.h> 21 #include "../dmaengine.h" 22 #include "registers.h" 23 #include "idxd.h" 24 #include "perfmon.h" 25 26 MODULE_VERSION(IDXD_DRIVER_VERSION); 27 MODULE_LICENSE("GPL v2"); 28 MODULE_AUTHOR("Intel Corporation"); 29 30 static bool sva = true; 31 module_param(sva, bool, 0644); 32 MODULE_PARM_DESC(sva, "Toggle SVA support on/off"); 33 34 #define DRV_NAME "idxd" 35 36 bool support_enqcmd; 37 DEFINE_IDA(idxd_ida); 38 39 static struct idxd_driver_data idxd_driver_data[] = { 40 [IDXD_TYPE_DSA] = { 41 .name_prefix = "dsa", 42 .type = IDXD_TYPE_DSA, 43 .compl_size = sizeof(struct dsa_completion_record), 44 .align = 32, 45 .dev_type = &dsa_device_type, 46 }, 47 [IDXD_TYPE_IAX] = { 48 .name_prefix = "iax", 49 .type = IDXD_TYPE_IAX, 50 .compl_size = sizeof(struct iax_completion_record), 51 .align = 64, 52 .dev_type = &iax_device_type, 53 }, 54 }; 55 56 static struct pci_device_id idxd_pci_tbl[] = { 57 /* DSA ver 1.0 platforms */ 58 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) }, 59 60 /* IAX ver 1.0 platforms */ 61 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) }, 62 { 0, } 63 }; 64 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl); 65 66 static int idxd_setup_interrupts(struct idxd_device *idxd) 67 { 68 struct pci_dev *pdev = idxd->pdev; 69 struct device *dev = &pdev->dev; 70 struct idxd_irq_entry *irq_entry; 71 int i, msixcnt; 72 int rc = 0; 73 74 msixcnt = pci_msix_vec_count(pdev); 75 if (msixcnt < 0) { 76 dev_err(dev, "Not MSI-X interrupt capable.\n"); 77 return -ENOSPC; 78 } 79 80 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX); 81 if (rc != msixcnt) { 82 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc); 83 return -ENOSPC; 84 } 85 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt); 86 87 /* 88 * We implement 1 completion list per MSI-X entry except for 89 * entry 0, which is for errors and others. 90 */ 91 idxd->irq_entries = kcalloc_node(msixcnt, sizeof(struct idxd_irq_entry), 92 GFP_KERNEL, dev_to_node(dev)); 93 if (!idxd->irq_entries) { 94 rc = -ENOMEM; 95 goto err_irq_entries; 96 } 97 98 for (i = 0; i < msixcnt; i++) { 99 idxd->irq_entries[i].id = i; 100 idxd->irq_entries[i].idxd = idxd; 101 idxd->irq_entries[i].vector = pci_irq_vector(pdev, i); 102 spin_lock_init(&idxd->irq_entries[i].list_lock); 103 } 104 105 irq_entry = &idxd->irq_entries[0]; 106 rc = request_threaded_irq(irq_entry->vector, NULL, idxd_misc_thread, 107 0, "idxd-misc", irq_entry); 108 if (rc < 0) { 109 dev_err(dev, "Failed to allocate misc interrupt.\n"); 110 goto err_misc_irq; 111 } 112 113 dev_dbg(dev, "Allocated idxd-misc handler on msix vector %d\n", irq_entry->vector); 114 115 /* first MSI-X entry is not for wq interrupts */ 116 idxd->num_wq_irqs = msixcnt - 1; 117 118 for (i = 1; i < msixcnt; i++) { 119 irq_entry = &idxd->irq_entries[i]; 120 121 init_llist_head(&idxd->irq_entries[i].pending_llist); 122 INIT_LIST_HEAD(&idxd->irq_entries[i].work_list); 123 rc = request_threaded_irq(irq_entry->vector, NULL, 124 idxd_wq_thread, 0, "idxd-portal", irq_entry); 125 if (rc < 0) { 126 dev_err(dev, "Failed to allocate irq %d.\n", irq_entry->vector); 127 goto err_wq_irqs; 128 } 129 130 dev_dbg(dev, "Allocated idxd-msix %d for vector %d\n", i, irq_entry->vector); 131 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) { 132 /* 133 * The MSIX vector enumeration starts at 1 with vector 0 being the 134 * misc interrupt that handles non I/O completion events. The 135 * interrupt handles are for IMS enumeration on guest. The misc 136 * interrupt vector does not require a handle and therefore we start 137 * the int_handles at index 0. Since 'i' starts at 1, the first 138 * int_handles index will be 0. 139 */ 140 rc = idxd_device_request_int_handle(idxd, i, &idxd->int_handles[i - 1], 141 IDXD_IRQ_MSIX); 142 if (rc < 0) { 143 free_irq(irq_entry->vector, irq_entry); 144 goto err_wq_irqs; 145 } 146 dev_dbg(dev, "int handle requested: %u\n", idxd->int_handles[i - 1]); 147 } 148 } 149 150 idxd_unmask_error_interrupts(idxd); 151 idxd_msix_perm_setup(idxd); 152 return 0; 153 154 err_wq_irqs: 155 while (--i >= 0) { 156 irq_entry = &idxd->irq_entries[i]; 157 free_irq(irq_entry->vector, irq_entry); 158 if (i != 0) 159 idxd_device_release_int_handle(idxd, 160 idxd->int_handles[i], IDXD_IRQ_MSIX); 161 } 162 err_misc_irq: 163 /* Disable error interrupt generation */ 164 idxd_mask_error_interrupts(idxd); 165 err_irq_entries: 166 pci_free_irq_vectors(pdev); 167 dev_err(dev, "No usable interrupts\n"); 168 return rc; 169 } 170 171 static int idxd_setup_wqs(struct idxd_device *idxd) 172 { 173 struct device *dev = &idxd->pdev->dev; 174 struct idxd_wq *wq; 175 int i, rc; 176 177 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *), 178 GFP_KERNEL, dev_to_node(dev)); 179 if (!idxd->wqs) 180 return -ENOMEM; 181 182 for (i = 0; i < idxd->max_wqs; i++) { 183 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev)); 184 if (!wq) { 185 rc = -ENOMEM; 186 goto err; 187 } 188 189 wq->id = i; 190 wq->idxd = idxd; 191 device_initialize(&wq->conf_dev); 192 wq->conf_dev.parent = &idxd->conf_dev; 193 wq->conf_dev.bus = &dsa_bus_type; 194 wq->conf_dev.type = &idxd_wq_device_type; 195 rc = dev_set_name(&wq->conf_dev, "wq%d.%d", idxd->id, wq->id); 196 if (rc < 0) { 197 put_device(&wq->conf_dev); 198 goto err; 199 } 200 201 mutex_init(&wq->wq_lock); 202 init_waitqueue_head(&wq->err_queue); 203 init_completion(&wq->wq_dead); 204 wq->max_xfer_bytes = idxd->max_xfer_bytes; 205 wq->max_batch_size = idxd->max_batch_size; 206 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev)); 207 if (!wq->wqcfg) { 208 put_device(&wq->conf_dev); 209 rc = -ENOMEM; 210 goto err; 211 } 212 idxd->wqs[i] = wq; 213 } 214 215 return 0; 216 217 err: 218 while (--i >= 0) 219 put_device(&idxd->wqs[i]->conf_dev); 220 return rc; 221 } 222 223 static int idxd_setup_engines(struct idxd_device *idxd) 224 { 225 struct idxd_engine *engine; 226 struct device *dev = &idxd->pdev->dev; 227 int i, rc; 228 229 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *), 230 GFP_KERNEL, dev_to_node(dev)); 231 if (!idxd->engines) 232 return -ENOMEM; 233 234 for (i = 0; i < idxd->max_engines; i++) { 235 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev)); 236 if (!engine) { 237 rc = -ENOMEM; 238 goto err; 239 } 240 241 engine->id = i; 242 engine->idxd = idxd; 243 device_initialize(&engine->conf_dev); 244 engine->conf_dev.parent = &idxd->conf_dev; 245 engine->conf_dev.bus = &dsa_bus_type; 246 engine->conf_dev.type = &idxd_engine_device_type; 247 rc = dev_set_name(&engine->conf_dev, "engine%d.%d", idxd->id, engine->id); 248 if (rc < 0) { 249 put_device(&engine->conf_dev); 250 goto err; 251 } 252 253 idxd->engines[i] = engine; 254 } 255 256 return 0; 257 258 err: 259 while (--i >= 0) 260 put_device(&idxd->engines[i]->conf_dev); 261 return rc; 262 } 263 264 static int idxd_setup_groups(struct idxd_device *idxd) 265 { 266 struct device *dev = &idxd->pdev->dev; 267 struct idxd_group *group; 268 int i, rc; 269 270 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *), 271 GFP_KERNEL, dev_to_node(dev)); 272 if (!idxd->groups) 273 return -ENOMEM; 274 275 for (i = 0; i < idxd->max_groups; i++) { 276 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev)); 277 if (!group) { 278 rc = -ENOMEM; 279 goto err; 280 } 281 282 group->id = i; 283 group->idxd = idxd; 284 device_initialize(&group->conf_dev); 285 group->conf_dev.parent = &idxd->conf_dev; 286 group->conf_dev.bus = &dsa_bus_type; 287 group->conf_dev.type = &idxd_group_device_type; 288 rc = dev_set_name(&group->conf_dev, "group%d.%d", idxd->id, group->id); 289 if (rc < 0) { 290 put_device(&group->conf_dev); 291 goto err; 292 } 293 294 idxd->groups[i] = group; 295 group->tc_a = -1; 296 group->tc_b = -1; 297 } 298 299 return 0; 300 301 err: 302 while (--i >= 0) 303 put_device(&idxd->groups[i]->conf_dev); 304 return rc; 305 } 306 307 static int idxd_setup_internals(struct idxd_device *idxd) 308 { 309 struct device *dev = &idxd->pdev->dev; 310 int rc, i; 311 312 init_waitqueue_head(&idxd->cmd_waitq); 313 314 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) { 315 idxd->int_handles = devm_kcalloc(dev, idxd->max_wqs, sizeof(int), GFP_KERNEL); 316 if (!idxd->int_handles) 317 return -ENOMEM; 318 } 319 320 rc = idxd_setup_wqs(idxd); 321 if (rc < 0) 322 goto err_wqs; 323 324 rc = idxd_setup_engines(idxd); 325 if (rc < 0) 326 goto err_engine; 327 328 rc = idxd_setup_groups(idxd); 329 if (rc < 0) 330 goto err_group; 331 332 idxd->wq = create_workqueue(dev_name(dev)); 333 if (!idxd->wq) { 334 rc = -ENOMEM; 335 goto err_wkq_create; 336 } 337 338 return 0; 339 340 err_wkq_create: 341 for (i = 0; i < idxd->max_groups; i++) 342 put_device(&idxd->groups[i]->conf_dev); 343 err_group: 344 for (i = 0; i < idxd->max_engines; i++) 345 put_device(&idxd->engines[i]->conf_dev); 346 err_engine: 347 for (i = 0; i < idxd->max_wqs; i++) 348 put_device(&idxd->wqs[i]->conf_dev); 349 err_wqs: 350 kfree(idxd->int_handles); 351 return rc; 352 } 353 354 static void idxd_read_table_offsets(struct idxd_device *idxd) 355 { 356 union offsets_reg offsets; 357 struct device *dev = &idxd->pdev->dev; 358 359 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET); 360 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64)); 361 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT; 362 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset); 363 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT; 364 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset); 365 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT; 366 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset); 367 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT; 368 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset); 369 } 370 371 static void idxd_read_caps(struct idxd_device *idxd) 372 { 373 struct device *dev = &idxd->pdev->dev; 374 int i; 375 376 /* reading generic capabilities */ 377 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET); 378 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits); 379 380 if (idxd->hw.gen_cap.cmd_cap) { 381 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET); 382 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap); 383 } 384 385 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift; 386 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes); 387 idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift; 388 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size); 389 if (idxd->hw.gen_cap.config_en) 390 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags); 391 392 /* reading group capabilities */ 393 idxd->hw.group_cap.bits = 394 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET); 395 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits); 396 idxd->max_groups = idxd->hw.group_cap.num_groups; 397 dev_dbg(dev, "max groups: %u\n", idxd->max_groups); 398 idxd->max_tokens = idxd->hw.group_cap.total_tokens; 399 dev_dbg(dev, "max tokens: %u\n", idxd->max_tokens); 400 idxd->nr_tokens = idxd->max_tokens; 401 402 /* read engine capabilities */ 403 idxd->hw.engine_cap.bits = 404 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET); 405 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits); 406 idxd->max_engines = idxd->hw.engine_cap.num_engines; 407 dev_dbg(dev, "max engines: %u\n", idxd->max_engines); 408 409 /* read workqueue capabilities */ 410 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET); 411 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits); 412 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size; 413 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size); 414 idxd->max_wqs = idxd->hw.wq_cap.num_wqs; 415 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs); 416 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN); 417 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size); 418 419 /* reading operation capabilities */ 420 for (i = 0; i < 4; i++) { 421 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base + 422 IDXD_OPCAP_OFFSET + i * sizeof(u64)); 423 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]); 424 } 425 } 426 427 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data) 428 { 429 struct device *dev = &pdev->dev; 430 struct idxd_device *idxd; 431 int rc; 432 433 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev)); 434 if (!idxd) 435 return NULL; 436 437 idxd->pdev = pdev; 438 idxd->data = data; 439 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL); 440 if (idxd->id < 0) 441 return NULL; 442 443 device_initialize(&idxd->conf_dev); 444 idxd->conf_dev.parent = dev; 445 idxd->conf_dev.bus = &dsa_bus_type; 446 idxd->conf_dev.type = idxd->data->dev_type; 447 rc = dev_set_name(&idxd->conf_dev, "%s%d", idxd->data->name_prefix, idxd->id); 448 if (rc < 0) { 449 put_device(&idxd->conf_dev); 450 return NULL; 451 } 452 453 spin_lock_init(&idxd->dev_lock); 454 spin_lock_init(&idxd->cmd_lock); 455 456 return idxd; 457 } 458 459 static int idxd_enable_system_pasid(struct idxd_device *idxd) 460 { 461 int flags; 462 unsigned int pasid; 463 struct iommu_sva *sva; 464 465 flags = SVM_FLAG_SUPERVISOR_MODE; 466 467 sva = iommu_sva_bind_device(&idxd->pdev->dev, NULL, &flags); 468 if (IS_ERR(sva)) { 469 dev_warn(&idxd->pdev->dev, 470 "iommu sva bind failed: %ld\n", PTR_ERR(sva)); 471 return PTR_ERR(sva); 472 } 473 474 pasid = iommu_sva_get_pasid(sva); 475 if (pasid == IOMMU_PASID_INVALID) { 476 iommu_sva_unbind_device(sva); 477 return -ENODEV; 478 } 479 480 idxd->sva = sva; 481 idxd->pasid = pasid; 482 dev_dbg(&idxd->pdev->dev, "system pasid: %u\n", pasid); 483 return 0; 484 } 485 486 static void idxd_disable_system_pasid(struct idxd_device *idxd) 487 { 488 489 iommu_sva_unbind_device(idxd->sva); 490 idxd->sva = NULL; 491 } 492 493 static int idxd_probe(struct idxd_device *idxd) 494 { 495 struct pci_dev *pdev = idxd->pdev; 496 struct device *dev = &pdev->dev; 497 int rc; 498 499 dev_dbg(dev, "%s entered and resetting device\n", __func__); 500 rc = idxd_device_init_reset(idxd); 501 if (rc < 0) 502 return rc; 503 504 dev_dbg(dev, "IDXD reset complete\n"); 505 506 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) { 507 rc = iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA); 508 if (rc == 0) { 509 rc = idxd_enable_system_pasid(idxd); 510 if (rc < 0) { 511 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA); 512 dev_warn(dev, "Failed to enable PASID. No SVA support: %d\n", rc); 513 } else { 514 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 515 } 516 } else { 517 dev_warn(dev, "Unable to turn on SVA feature.\n"); 518 } 519 } else if (!sva) { 520 dev_warn(dev, "User forced SVA off via module param.\n"); 521 } 522 523 idxd_read_caps(idxd); 524 idxd_read_table_offsets(idxd); 525 526 rc = idxd_setup_internals(idxd); 527 if (rc) 528 goto err; 529 530 /* If the configs are readonly, then load them from device */ 531 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 532 dev_dbg(dev, "Loading RO device config\n"); 533 rc = idxd_device_load_config(idxd); 534 if (rc < 0) 535 goto err; 536 } 537 538 rc = idxd_setup_interrupts(idxd); 539 if (rc) 540 goto err; 541 542 dev_dbg(dev, "IDXD interrupt setup complete.\n"); 543 544 idxd->major = idxd_cdev_get_major(idxd); 545 546 rc = perfmon_pmu_init(idxd); 547 if (rc < 0) 548 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc); 549 550 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id); 551 return 0; 552 553 err: 554 if (device_pasid_enabled(idxd)) 555 idxd_disable_system_pasid(idxd); 556 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA); 557 return rc; 558 } 559 560 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 561 { 562 struct device *dev = &pdev->dev; 563 struct idxd_device *idxd; 564 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data; 565 int rc; 566 567 rc = pci_enable_device(pdev); 568 if (rc) 569 return rc; 570 571 dev_dbg(dev, "Alloc IDXD context\n"); 572 idxd = idxd_alloc(pdev, data); 573 if (!idxd) { 574 rc = -ENOMEM; 575 goto err_idxd_alloc; 576 } 577 578 dev_dbg(dev, "Mapping BARs\n"); 579 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0); 580 if (!idxd->reg_base) { 581 rc = -ENOMEM; 582 goto err_iomap; 583 } 584 585 dev_dbg(dev, "Set DMA masks\n"); 586 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 587 if (rc) 588 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 589 if (rc) 590 goto err; 591 592 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 593 if (rc) 594 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 595 if (rc) 596 goto err; 597 598 dev_dbg(dev, "Set PCI master\n"); 599 pci_set_master(pdev); 600 pci_set_drvdata(pdev, idxd); 601 602 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET); 603 rc = idxd_probe(idxd); 604 if (rc) { 605 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n"); 606 goto err; 607 } 608 609 rc = idxd_register_devices(idxd); 610 if (rc) { 611 dev_err(dev, "IDXD sysfs setup failed\n"); 612 goto err; 613 } 614 615 idxd->state = IDXD_DEV_CONF_READY; 616 617 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n", 618 idxd->hw.version); 619 620 return 0; 621 622 err: 623 pci_iounmap(pdev, idxd->reg_base); 624 err_iomap: 625 put_device(&idxd->conf_dev); 626 err_idxd_alloc: 627 pci_disable_device(pdev); 628 return rc; 629 } 630 631 static void idxd_flush_pending_llist(struct idxd_irq_entry *ie) 632 { 633 struct idxd_desc *desc, *itr; 634 struct llist_node *head; 635 636 head = llist_del_all(&ie->pending_llist); 637 if (!head) 638 return; 639 640 llist_for_each_entry_safe(desc, itr, head, llnode) { 641 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT); 642 idxd_free_desc(desc->wq, desc); 643 } 644 } 645 646 static void idxd_flush_work_list(struct idxd_irq_entry *ie) 647 { 648 struct idxd_desc *desc, *iter; 649 650 list_for_each_entry_safe(desc, iter, &ie->work_list, list) { 651 list_del(&desc->list); 652 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT); 653 idxd_free_desc(desc->wq, desc); 654 } 655 } 656 657 void idxd_wqs_quiesce(struct idxd_device *idxd) 658 { 659 struct idxd_wq *wq; 660 int i; 661 662 for (i = 0; i < idxd->max_wqs; i++) { 663 wq = idxd->wqs[i]; 664 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL) 665 idxd_wq_quiesce(wq); 666 } 667 } 668 669 static void idxd_release_int_handles(struct idxd_device *idxd) 670 { 671 struct device *dev = &idxd->pdev->dev; 672 int i, rc; 673 674 for (i = 0; i < idxd->num_wq_irqs; i++) { 675 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)) { 676 rc = idxd_device_release_int_handle(idxd, idxd->int_handles[i], 677 IDXD_IRQ_MSIX); 678 if (rc < 0) 679 dev_warn(dev, "irq handle %d release failed\n", 680 idxd->int_handles[i]); 681 else 682 dev_dbg(dev, "int handle requested: %u\n", idxd->int_handles[i]); 683 } 684 } 685 } 686 687 static void idxd_shutdown(struct pci_dev *pdev) 688 { 689 struct idxd_device *idxd = pci_get_drvdata(pdev); 690 int rc, i; 691 struct idxd_irq_entry *irq_entry; 692 int msixcnt = pci_msix_vec_count(pdev); 693 694 rc = idxd_device_disable(idxd); 695 if (rc) 696 dev_err(&pdev->dev, "Disabling device failed\n"); 697 698 dev_dbg(&pdev->dev, "%s called\n", __func__); 699 idxd_mask_msix_vectors(idxd); 700 idxd_mask_error_interrupts(idxd); 701 702 for (i = 0; i < msixcnt; i++) { 703 irq_entry = &idxd->irq_entries[i]; 704 synchronize_irq(irq_entry->vector); 705 free_irq(irq_entry->vector, irq_entry); 706 if (i == 0) 707 continue; 708 idxd_flush_pending_llist(irq_entry); 709 idxd_flush_work_list(irq_entry); 710 } 711 712 idxd_msix_perm_clear(idxd); 713 idxd_release_int_handles(idxd); 714 pci_free_irq_vectors(pdev); 715 pci_iounmap(pdev, idxd->reg_base); 716 pci_disable_device(pdev); 717 destroy_workqueue(idxd->wq); 718 } 719 720 static void idxd_remove(struct pci_dev *pdev) 721 { 722 struct idxd_device *idxd = pci_get_drvdata(pdev); 723 724 dev_dbg(&pdev->dev, "%s called\n", __func__); 725 idxd_shutdown(pdev); 726 if (device_pasid_enabled(idxd)) 727 idxd_disable_system_pasid(idxd); 728 idxd_unregister_devices(idxd); 729 perfmon_pmu_remove(idxd); 730 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA); 731 } 732 733 static struct pci_driver idxd_pci_driver = { 734 .name = DRV_NAME, 735 .id_table = idxd_pci_tbl, 736 .probe = idxd_pci_probe, 737 .remove = idxd_remove, 738 .shutdown = idxd_shutdown, 739 }; 740 741 static int __init idxd_init_module(void) 742 { 743 int err; 744 745 /* 746 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in 747 * enumerating the device. We can not utilize it. 748 */ 749 if (!boot_cpu_has(X86_FEATURE_MOVDIR64B)) { 750 pr_warn("idxd driver failed to load without MOVDIR64B.\n"); 751 return -ENODEV; 752 } 753 754 if (!boot_cpu_has(X86_FEATURE_ENQCMD)) 755 pr_warn("Platform does not have ENQCMD(S) support.\n"); 756 else 757 support_enqcmd = true; 758 759 perfmon_init(); 760 761 err = idxd_register_bus_type(); 762 if (err < 0) 763 return err; 764 765 err = idxd_register_driver(); 766 if (err < 0) 767 goto err_idxd_driver_register; 768 769 err = idxd_cdev_register(); 770 if (err) 771 goto err_cdev_register; 772 773 err = pci_register_driver(&idxd_pci_driver); 774 if (err) 775 goto err_pci_register; 776 777 return 0; 778 779 err_pci_register: 780 idxd_cdev_remove(); 781 err_cdev_register: 782 idxd_unregister_driver(); 783 err_idxd_driver_register: 784 idxd_unregister_bus_type(); 785 return err; 786 } 787 module_init(idxd_init_module); 788 789 static void __exit idxd_exit_module(void) 790 { 791 pci_unregister_driver(&idxd_pci_driver); 792 idxd_cdev_remove(); 793 idxd_unregister_bus_type(); 794 perfmon_exit(); 795 } 796 module_exit(idxd_exit_module); 797