1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <linux/irq.h> 10 #include <uapi/linux/idxd.h> 11 #include "../dmaengine.h" 12 #include "idxd.h" 13 #include "registers.h" 14 15 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 16 u32 *status); 17 static void idxd_device_wqs_clear_state(struct idxd_device *idxd); 18 static void idxd_wq_disable_cleanup(struct idxd_wq *wq); 19 20 /* Interrupt control bits */ 21 void idxd_unmask_error_interrupts(struct idxd_device *idxd) 22 { 23 union genctrl_reg genctrl; 24 25 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 26 genctrl.softerr_int_en = 1; 27 genctrl.halt_int_en = 1; 28 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 29 } 30 31 void idxd_mask_error_interrupts(struct idxd_device *idxd) 32 { 33 union genctrl_reg genctrl; 34 35 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 36 genctrl.softerr_int_en = 0; 37 genctrl.halt_int_en = 0; 38 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 39 } 40 41 static void free_hw_descs(struct idxd_wq *wq) 42 { 43 int i; 44 45 for (i = 0; i < wq->num_descs; i++) 46 kfree(wq->hw_descs[i]); 47 48 kfree(wq->hw_descs); 49 } 50 51 static int alloc_hw_descs(struct idxd_wq *wq, int num) 52 { 53 struct device *dev = &wq->idxd->pdev->dev; 54 int i; 55 int node = dev_to_node(dev); 56 57 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), 58 GFP_KERNEL, node); 59 if (!wq->hw_descs) 60 return -ENOMEM; 61 62 for (i = 0; i < num; i++) { 63 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), 64 GFP_KERNEL, node); 65 if (!wq->hw_descs[i]) { 66 free_hw_descs(wq); 67 return -ENOMEM; 68 } 69 } 70 71 return 0; 72 } 73 74 static void free_descs(struct idxd_wq *wq) 75 { 76 int i; 77 78 for (i = 0; i < wq->num_descs; i++) 79 kfree(wq->descs[i]); 80 81 kfree(wq->descs); 82 } 83 84 static int alloc_descs(struct idxd_wq *wq, int num) 85 { 86 struct device *dev = &wq->idxd->pdev->dev; 87 int i; 88 int node = dev_to_node(dev); 89 90 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), 91 GFP_KERNEL, node); 92 if (!wq->descs) 93 return -ENOMEM; 94 95 for (i = 0; i < num; i++) { 96 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), 97 GFP_KERNEL, node); 98 if (!wq->descs[i]) { 99 free_descs(wq); 100 return -ENOMEM; 101 } 102 } 103 104 return 0; 105 } 106 107 /* WQ control bits */ 108 int idxd_wq_alloc_resources(struct idxd_wq *wq) 109 { 110 struct idxd_device *idxd = wq->idxd; 111 struct device *dev = &idxd->pdev->dev; 112 int rc, num_descs, i; 113 114 if (wq->type != IDXD_WQT_KERNEL) 115 return 0; 116 117 num_descs = wq_dedicated(wq) ? wq->size : wq->threshold; 118 wq->num_descs = num_descs; 119 120 rc = alloc_hw_descs(wq, num_descs); 121 if (rc < 0) 122 return rc; 123 124 wq->compls_size = num_descs * idxd->data->compl_size; 125 wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL); 126 if (!wq->compls) { 127 rc = -ENOMEM; 128 goto fail_alloc_compls; 129 } 130 131 rc = alloc_descs(wq, num_descs); 132 if (rc < 0) 133 goto fail_alloc_descs; 134 135 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL, 136 dev_to_node(dev)); 137 if (rc < 0) 138 goto fail_sbitmap_init; 139 140 for (i = 0; i < num_descs; i++) { 141 struct idxd_desc *desc = wq->descs[i]; 142 143 desc->hw = wq->hw_descs[i]; 144 if (idxd->data->type == IDXD_TYPE_DSA) 145 desc->completion = &wq->compls[i]; 146 else if (idxd->data->type == IDXD_TYPE_IAX) 147 desc->iax_completion = &wq->iax_compls[i]; 148 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i; 149 desc->id = i; 150 desc->wq = wq; 151 desc->cpu = -1; 152 } 153 154 return 0; 155 156 fail_sbitmap_init: 157 free_descs(wq); 158 fail_alloc_descs: 159 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 160 fail_alloc_compls: 161 free_hw_descs(wq); 162 return rc; 163 } 164 EXPORT_SYMBOL_NS_GPL(idxd_wq_alloc_resources, IDXD); 165 166 void idxd_wq_free_resources(struct idxd_wq *wq) 167 { 168 struct device *dev = &wq->idxd->pdev->dev; 169 170 if (wq->type != IDXD_WQT_KERNEL) 171 return; 172 173 free_hw_descs(wq); 174 free_descs(wq); 175 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 176 sbitmap_queue_free(&wq->sbq); 177 } 178 EXPORT_SYMBOL_NS_GPL(idxd_wq_free_resources, IDXD); 179 180 int idxd_wq_enable(struct idxd_wq *wq) 181 { 182 struct idxd_device *idxd = wq->idxd; 183 struct device *dev = &idxd->pdev->dev; 184 u32 status; 185 186 if (wq->state == IDXD_WQ_ENABLED) { 187 dev_dbg(dev, "WQ %d already enabled\n", wq->id); 188 return 0; 189 } 190 191 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status); 192 193 if (status != IDXD_CMDSTS_SUCCESS && 194 status != IDXD_CMDSTS_ERR_WQ_ENABLED) { 195 dev_dbg(dev, "WQ enable failed: %#x\n", status); 196 return -ENXIO; 197 } 198 199 wq->state = IDXD_WQ_ENABLED; 200 set_bit(wq->id, idxd->wq_enable_map); 201 dev_dbg(dev, "WQ %d enabled\n", wq->id); 202 return 0; 203 } 204 205 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config) 206 { 207 struct idxd_device *idxd = wq->idxd; 208 struct device *dev = &idxd->pdev->dev; 209 u32 status, operand; 210 211 dev_dbg(dev, "Disabling WQ %d\n", wq->id); 212 213 if (wq->state != IDXD_WQ_ENABLED) { 214 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 215 return 0; 216 } 217 218 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 219 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status); 220 221 if (status != IDXD_CMDSTS_SUCCESS) { 222 dev_dbg(dev, "WQ disable failed: %#x\n", status); 223 return -ENXIO; 224 } 225 226 if (reset_config) 227 idxd_wq_disable_cleanup(wq); 228 clear_bit(wq->id, idxd->wq_enable_map); 229 wq->state = IDXD_WQ_DISABLED; 230 dev_dbg(dev, "WQ %d disabled\n", wq->id); 231 return 0; 232 } 233 234 void idxd_wq_drain(struct idxd_wq *wq) 235 { 236 struct idxd_device *idxd = wq->idxd; 237 struct device *dev = &idxd->pdev->dev; 238 u32 operand; 239 240 if (wq->state != IDXD_WQ_ENABLED) { 241 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 242 return; 243 } 244 245 dev_dbg(dev, "Draining WQ %d\n", wq->id); 246 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 247 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL); 248 } 249 250 void idxd_wq_reset(struct idxd_wq *wq) 251 { 252 struct idxd_device *idxd = wq->idxd; 253 struct device *dev = &idxd->pdev->dev; 254 u32 operand; 255 256 if (wq->state != IDXD_WQ_ENABLED) { 257 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 258 return; 259 } 260 261 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 262 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL); 263 idxd_wq_disable_cleanup(wq); 264 } 265 266 int idxd_wq_map_portal(struct idxd_wq *wq) 267 { 268 struct idxd_device *idxd = wq->idxd; 269 struct pci_dev *pdev = idxd->pdev; 270 struct device *dev = &pdev->dev; 271 resource_size_t start; 272 273 start = pci_resource_start(pdev, IDXD_WQ_BAR); 274 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED); 275 276 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 277 if (!wq->portal) 278 return -ENOMEM; 279 280 return 0; 281 } 282 283 void idxd_wq_unmap_portal(struct idxd_wq *wq) 284 { 285 struct device *dev = &wq->idxd->pdev->dev; 286 287 devm_iounmap(dev, wq->portal); 288 wq->portal = NULL; 289 wq->portal_offset = 0; 290 } 291 292 void idxd_wqs_unmap_portal(struct idxd_device *idxd) 293 { 294 int i; 295 296 for (i = 0; i < idxd->max_wqs; i++) { 297 struct idxd_wq *wq = idxd->wqs[i]; 298 299 if (wq->portal) 300 idxd_wq_unmap_portal(wq); 301 } 302 } 303 304 static void __idxd_wq_set_pasid_locked(struct idxd_wq *wq, int pasid) 305 { 306 struct idxd_device *idxd = wq->idxd; 307 union wqcfg wqcfg; 308 unsigned int offset; 309 310 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 311 spin_lock(&idxd->dev_lock); 312 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 313 wqcfg.pasid_en = 1; 314 wqcfg.pasid = pasid; 315 wq->wqcfg->bits[WQCFG_PASID_IDX] = wqcfg.bits[WQCFG_PASID_IDX]; 316 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 317 spin_unlock(&idxd->dev_lock); 318 } 319 320 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid) 321 { 322 int rc; 323 324 rc = idxd_wq_disable(wq, false); 325 if (rc < 0) 326 return rc; 327 328 __idxd_wq_set_pasid_locked(wq, pasid); 329 330 rc = idxd_wq_enable(wq); 331 if (rc < 0) 332 return rc; 333 334 return 0; 335 } 336 337 int idxd_wq_disable_pasid(struct idxd_wq *wq) 338 { 339 struct idxd_device *idxd = wq->idxd; 340 int rc; 341 union wqcfg wqcfg; 342 unsigned int offset; 343 344 rc = idxd_wq_disable(wq, false); 345 if (rc < 0) 346 return rc; 347 348 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 349 spin_lock(&idxd->dev_lock); 350 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 351 wqcfg.pasid_en = 0; 352 wqcfg.pasid = 0; 353 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 354 spin_unlock(&idxd->dev_lock); 355 356 rc = idxd_wq_enable(wq); 357 if (rc < 0) 358 return rc; 359 360 return 0; 361 } 362 363 static void idxd_wq_disable_cleanup(struct idxd_wq *wq) 364 { 365 struct idxd_device *idxd = wq->idxd; 366 367 lockdep_assert_held(&wq->wq_lock); 368 wq->state = IDXD_WQ_DISABLED; 369 memset(wq->wqcfg, 0, idxd->wqcfg_size); 370 wq->type = IDXD_WQT_NONE; 371 wq->threshold = 0; 372 wq->priority = 0; 373 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 374 wq->flags = 0; 375 memset(wq->name, 0, WQ_NAME_SIZE); 376 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 377 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 378 if (wq->opcap_bmap) 379 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 380 } 381 382 static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq) 383 { 384 lockdep_assert_held(&wq->wq_lock); 385 386 wq->size = 0; 387 wq->group = NULL; 388 } 389 390 static void idxd_wq_ref_release(struct percpu_ref *ref) 391 { 392 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active); 393 394 complete(&wq->wq_dead); 395 } 396 397 int idxd_wq_init_percpu_ref(struct idxd_wq *wq) 398 { 399 int rc; 400 401 memset(&wq->wq_active, 0, sizeof(wq->wq_active)); 402 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 403 PERCPU_REF_ALLOW_REINIT, GFP_KERNEL); 404 if (rc < 0) 405 return rc; 406 reinit_completion(&wq->wq_dead); 407 reinit_completion(&wq->wq_resurrect); 408 return 0; 409 } 410 EXPORT_SYMBOL_NS_GPL(idxd_wq_init_percpu_ref, IDXD); 411 412 void __idxd_wq_quiesce(struct idxd_wq *wq) 413 { 414 lockdep_assert_held(&wq->wq_lock); 415 reinit_completion(&wq->wq_resurrect); 416 percpu_ref_kill(&wq->wq_active); 417 complete_all(&wq->wq_resurrect); 418 wait_for_completion(&wq->wq_dead); 419 } 420 EXPORT_SYMBOL_NS_GPL(__idxd_wq_quiesce, IDXD); 421 422 void idxd_wq_quiesce(struct idxd_wq *wq) 423 { 424 mutex_lock(&wq->wq_lock); 425 __idxd_wq_quiesce(wq); 426 mutex_unlock(&wq->wq_lock); 427 } 428 EXPORT_SYMBOL_NS_GPL(idxd_wq_quiesce, IDXD); 429 430 /* Device control bits */ 431 static inline bool idxd_is_enabled(struct idxd_device *idxd) 432 { 433 union gensts_reg gensts; 434 435 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 436 437 if (gensts.state == IDXD_DEVICE_STATE_ENABLED) 438 return true; 439 return false; 440 } 441 442 static inline bool idxd_device_is_halted(struct idxd_device *idxd) 443 { 444 union gensts_reg gensts; 445 446 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 447 448 return (gensts.state == IDXD_DEVICE_STATE_HALT); 449 } 450 451 /* 452 * This is function is only used for reset during probe and will 453 * poll for completion. Once the device is setup with interrupts, 454 * all commands will be done via interrupt completion. 455 */ 456 int idxd_device_init_reset(struct idxd_device *idxd) 457 { 458 struct device *dev = &idxd->pdev->dev; 459 union idxd_command_reg cmd; 460 461 if (idxd_device_is_halted(idxd)) { 462 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 463 return -ENXIO; 464 } 465 466 memset(&cmd, 0, sizeof(cmd)); 467 cmd.cmd = IDXD_CMD_RESET_DEVICE; 468 dev_dbg(dev, "%s: sending reset for init.\n", __func__); 469 spin_lock(&idxd->cmd_lock); 470 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 471 472 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & 473 IDXD_CMDSTS_ACTIVE) 474 cpu_relax(); 475 spin_unlock(&idxd->cmd_lock); 476 return 0; 477 } 478 479 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 480 u32 *status) 481 { 482 union idxd_command_reg cmd; 483 DECLARE_COMPLETION_ONSTACK(done); 484 u32 stat; 485 unsigned long flags; 486 487 if (idxd_device_is_halted(idxd)) { 488 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 489 if (status) 490 *status = IDXD_CMDSTS_HW_ERR; 491 return; 492 } 493 494 memset(&cmd, 0, sizeof(cmd)); 495 cmd.cmd = cmd_code; 496 cmd.operand = operand; 497 cmd.int_req = 1; 498 499 spin_lock_irqsave(&idxd->cmd_lock, flags); 500 wait_event_lock_irq(idxd->cmd_waitq, 501 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags), 502 idxd->cmd_lock); 503 504 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n", 505 __func__, cmd_code, operand); 506 507 idxd->cmd_status = 0; 508 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 509 idxd->cmd_done = &done; 510 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 511 512 /* 513 * After command submitted, release lock and go to sleep until 514 * the command completes via interrupt. 515 */ 516 spin_unlock_irqrestore(&idxd->cmd_lock, flags); 517 wait_for_completion(&done); 518 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 519 spin_lock(&idxd->cmd_lock); 520 if (status) 521 *status = stat; 522 idxd->cmd_status = stat & GENMASK(7, 0); 523 524 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 525 /* Wake up other pending commands */ 526 wake_up(&idxd->cmd_waitq); 527 spin_unlock(&idxd->cmd_lock); 528 } 529 530 int idxd_device_enable(struct idxd_device *idxd) 531 { 532 struct device *dev = &idxd->pdev->dev; 533 u32 status; 534 535 if (idxd_is_enabled(idxd)) { 536 dev_dbg(dev, "Device already enabled\n"); 537 return -ENXIO; 538 } 539 540 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status); 541 542 /* If the command is successful or if the device was enabled */ 543 if (status != IDXD_CMDSTS_SUCCESS && 544 status != IDXD_CMDSTS_ERR_DEV_ENABLED) { 545 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 546 return -ENXIO; 547 } 548 549 idxd->state = IDXD_DEV_ENABLED; 550 return 0; 551 } 552 553 int idxd_device_disable(struct idxd_device *idxd) 554 { 555 struct device *dev = &idxd->pdev->dev; 556 u32 status; 557 558 if (!idxd_is_enabled(idxd)) { 559 dev_dbg(dev, "Device is not enabled\n"); 560 return 0; 561 } 562 563 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status); 564 565 /* If the command is successful or if the device was disabled */ 566 if (status != IDXD_CMDSTS_SUCCESS && 567 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) { 568 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 569 return -ENXIO; 570 } 571 572 idxd_device_clear_state(idxd); 573 return 0; 574 } 575 576 void idxd_device_reset(struct idxd_device *idxd) 577 { 578 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 579 idxd_device_clear_state(idxd); 580 spin_lock(&idxd->dev_lock); 581 idxd_unmask_error_interrupts(idxd); 582 spin_unlock(&idxd->dev_lock); 583 } 584 585 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid) 586 { 587 struct device *dev = &idxd->pdev->dev; 588 u32 operand; 589 590 operand = pasid; 591 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand); 592 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL); 593 dev_dbg(dev, "pasid %d drained\n", pasid); 594 } 595 596 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 597 enum idxd_interrupt_type irq_type) 598 { 599 struct device *dev = &idxd->pdev->dev; 600 u32 operand, status; 601 602 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))) 603 return -EOPNOTSUPP; 604 605 dev_dbg(dev, "get int handle, idx %d\n", idx); 606 607 operand = idx & GENMASK(15, 0); 608 if (irq_type == IDXD_IRQ_IMS) 609 operand |= CMD_INT_HANDLE_IMS; 610 611 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand); 612 613 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status); 614 615 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 616 dev_dbg(dev, "request int handle failed: %#x\n", status); 617 return -ENXIO; 618 } 619 620 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0); 621 622 dev_dbg(dev, "int handle acquired: %u\n", *handle); 623 return 0; 624 } 625 626 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 627 enum idxd_interrupt_type irq_type) 628 { 629 struct device *dev = &idxd->pdev->dev; 630 u32 operand, status; 631 union idxd_command_reg cmd; 632 633 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))) 634 return -EOPNOTSUPP; 635 636 dev_dbg(dev, "release int handle, handle %d\n", handle); 637 638 memset(&cmd, 0, sizeof(cmd)); 639 operand = handle & GENMASK(15, 0); 640 641 if (irq_type == IDXD_IRQ_IMS) 642 operand |= CMD_INT_HANDLE_IMS; 643 644 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE; 645 cmd.operand = operand; 646 647 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand); 648 649 spin_lock(&idxd->cmd_lock); 650 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 651 652 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE) 653 cpu_relax(); 654 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 655 spin_unlock(&idxd->cmd_lock); 656 657 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 658 dev_dbg(dev, "release int handle failed: %#x\n", status); 659 return -ENXIO; 660 } 661 662 dev_dbg(dev, "int handle released.\n"); 663 return 0; 664 } 665 666 /* Device configuration bits */ 667 static void idxd_engines_clear_state(struct idxd_device *idxd) 668 { 669 struct idxd_engine *engine; 670 int i; 671 672 lockdep_assert_held(&idxd->dev_lock); 673 for (i = 0; i < idxd->max_engines; i++) { 674 engine = idxd->engines[i]; 675 engine->group = NULL; 676 } 677 } 678 679 static void idxd_groups_clear_state(struct idxd_device *idxd) 680 { 681 struct idxd_group *group; 682 int i; 683 684 lockdep_assert_held(&idxd->dev_lock); 685 for (i = 0; i < idxd->max_groups; i++) { 686 group = idxd->groups[i]; 687 memset(&group->grpcfg, 0, sizeof(group->grpcfg)); 688 group->num_engines = 0; 689 group->num_wqs = 0; 690 group->use_rdbuf_limit = false; 691 /* 692 * The default value is the same as the value of 693 * total read buffers in GRPCAP. 694 */ 695 group->rdbufs_allowed = idxd->max_rdbufs; 696 group->rdbufs_reserved = 0; 697 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) { 698 group->tc_a = 1; 699 group->tc_b = 1; 700 } else { 701 group->tc_a = -1; 702 group->tc_b = -1; 703 } 704 group->desc_progress_limit = 0; 705 group->batch_progress_limit = 0; 706 } 707 } 708 709 static void idxd_device_wqs_clear_state(struct idxd_device *idxd) 710 { 711 int i; 712 713 for (i = 0; i < idxd->max_wqs; i++) { 714 struct idxd_wq *wq = idxd->wqs[i]; 715 716 mutex_lock(&wq->wq_lock); 717 idxd_wq_disable_cleanup(wq); 718 idxd_wq_device_reset_cleanup(wq); 719 mutex_unlock(&wq->wq_lock); 720 } 721 } 722 723 void idxd_device_clear_state(struct idxd_device *idxd) 724 { 725 /* IDXD is always disabled. Other states are cleared only when IDXD is configurable. */ 726 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 727 /* 728 * Clearing wq state is protected by wq lock. 729 * So no need to be protected by device lock. 730 */ 731 idxd_device_wqs_clear_state(idxd); 732 733 spin_lock(&idxd->dev_lock); 734 idxd_groups_clear_state(idxd); 735 idxd_engines_clear_state(idxd); 736 } else { 737 spin_lock(&idxd->dev_lock); 738 } 739 740 idxd->state = IDXD_DEV_DISABLED; 741 spin_unlock(&idxd->dev_lock); 742 } 743 744 static int idxd_device_evl_setup(struct idxd_device *idxd) 745 { 746 union gencfg_reg gencfg; 747 union evlcfg_reg evlcfg; 748 union genctrl_reg genctrl; 749 struct device *dev = &idxd->pdev->dev; 750 void *addr; 751 dma_addr_t dma_addr; 752 int size; 753 struct idxd_evl *evl = idxd->evl; 754 unsigned long *bmap; 755 int rc; 756 757 if (!evl) 758 return 0; 759 760 size = evl_size(idxd); 761 762 bmap = bitmap_zalloc(size, GFP_KERNEL); 763 if (!bmap) { 764 rc = -ENOMEM; 765 goto err_bmap; 766 } 767 768 /* 769 * Address needs to be page aligned. However, dma_alloc_coherent() provides 770 * at minimal page size aligned address. No manual alignment required. 771 */ 772 addr = dma_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 773 if (!addr) { 774 rc = -ENOMEM; 775 goto err_alloc; 776 } 777 778 spin_lock(&evl->lock); 779 evl->log = addr; 780 evl->dma = dma_addr; 781 evl->log_size = size; 782 evl->bmap = bmap; 783 784 memset(&evlcfg, 0, sizeof(evlcfg)); 785 evlcfg.bits[0] = dma_addr & GENMASK(63, 12); 786 evlcfg.size = evl->size; 787 788 iowrite64(evlcfg.bits[0], idxd->reg_base + IDXD_EVLCFG_OFFSET); 789 iowrite64(evlcfg.bits[1], idxd->reg_base + IDXD_EVLCFG_OFFSET + 8); 790 791 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 792 genctrl.evl_int_en = 1; 793 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 794 795 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 796 gencfg.evl_en = 1; 797 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 798 799 spin_unlock(&evl->lock); 800 return 0; 801 802 err_alloc: 803 bitmap_free(bmap); 804 err_bmap: 805 return rc; 806 } 807 808 static void idxd_device_evl_free(struct idxd_device *idxd) 809 { 810 union gencfg_reg gencfg; 811 union genctrl_reg genctrl; 812 struct device *dev = &idxd->pdev->dev; 813 struct idxd_evl *evl = idxd->evl; 814 815 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 816 if (!gencfg.evl_en) 817 return; 818 819 spin_lock(&evl->lock); 820 gencfg.evl_en = 0; 821 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 822 823 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 824 genctrl.evl_int_en = 0; 825 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 826 827 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET); 828 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET + 8); 829 830 dma_free_coherent(dev, evl->log_size, evl->log, evl->dma); 831 bitmap_free(evl->bmap); 832 evl->log = NULL; 833 evl->size = IDXD_EVL_SIZE_MIN; 834 spin_unlock(&evl->lock); 835 } 836 837 static void idxd_group_config_write(struct idxd_group *group) 838 { 839 struct idxd_device *idxd = group->idxd; 840 struct device *dev = &idxd->pdev->dev; 841 int i; 842 u32 grpcfg_offset; 843 844 dev_dbg(dev, "Writing group %d cfg registers\n", group->id); 845 846 /* setup GRPWQCFG */ 847 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 848 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 849 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset); 850 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 851 group->id, i, grpcfg_offset, 852 ioread64(idxd->reg_base + grpcfg_offset)); 853 } 854 855 /* setup GRPENGCFG */ 856 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 857 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 858 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 859 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); 860 861 /* setup GRPFLAGS */ 862 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 863 iowrite64(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); 864 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n", 865 group->id, grpcfg_offset, 866 ioread64(idxd->reg_base + grpcfg_offset)); 867 } 868 869 static int idxd_groups_config_write(struct idxd_device *idxd) 870 871 { 872 union gencfg_reg reg; 873 int i; 874 struct device *dev = &idxd->pdev->dev; 875 876 /* Setup bandwidth rdbuf limit */ 877 if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) { 878 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 879 reg.rdbuf_limit = idxd->rdbuf_limit; 880 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 881 } 882 883 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET, 884 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET)); 885 886 for (i = 0; i < idxd->max_groups; i++) { 887 struct idxd_group *group = idxd->groups[i]; 888 889 idxd_group_config_write(group); 890 } 891 892 return 0; 893 } 894 895 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd) 896 { 897 struct pci_dev *pdev = idxd->pdev; 898 899 if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV)) 900 return true; 901 return false; 902 } 903 904 static int idxd_wq_config_write(struct idxd_wq *wq) 905 { 906 struct idxd_device *idxd = wq->idxd; 907 struct device *dev = &idxd->pdev->dev; 908 u32 wq_offset; 909 int i, n; 910 911 if (!wq->group) 912 return 0; 913 914 /* 915 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after 916 * wq reset. This will copy back the sticky values that are present on some devices. 917 */ 918 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 919 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 920 wq->wqcfg->bits[i] |= ioread32(idxd->reg_base + wq_offset); 921 } 922 923 if (wq->size == 0 && wq->type != IDXD_WQT_NONE) 924 wq->size = WQ_DEFAULT_QUEUE_DEPTH; 925 926 /* byte 0-3 */ 927 wq->wqcfg->wq_size = wq->size; 928 929 /* bytes 4-7 */ 930 wq->wqcfg->wq_thresh = wq->threshold; 931 932 /* byte 8-11 */ 933 if (wq_dedicated(wq)) 934 wq->wqcfg->mode = 1; 935 936 /* 937 * The WQ priv bit is set depending on the WQ type. priv = 1 if the 938 * WQ type is kernel to indicate privileged access. This setting only 939 * matters for dedicated WQ. According to the DSA spec: 940 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the 941 * Privileged Mode Enable field of the PCI Express PASID capability 942 * is 0, this field must be 0. 943 * 944 * In the case of a dedicated kernel WQ that is not able to support 945 * the PASID cap, then the configuration will be rejected. 946 */ 947 if (wq_dedicated(wq) && wq->wqcfg->pasid_en && 948 !idxd_device_pasid_priv_enabled(idxd) && 949 wq->type == IDXD_WQT_KERNEL) { 950 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV; 951 return -EOPNOTSUPP; 952 } 953 954 wq->wqcfg->priority = wq->priority; 955 956 if (idxd->hw.gen_cap.block_on_fault && 957 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags) && 958 !test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags)) 959 wq->wqcfg->bof = 1; 960 961 if (idxd->hw.wq_cap.wq_ats_support) 962 wq->wqcfg->wq_ats_disable = test_bit(WQ_FLAG_ATS_DISABLE, &wq->flags); 963 964 if (idxd->hw.wq_cap.wq_prs_support) 965 wq->wqcfg->wq_prs_disable = test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags); 966 967 /* bytes 12-15 */ 968 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 969 idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size)); 970 971 /* bytes 32-63 */ 972 if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) { 973 memset(wq->wqcfg->op_config, 0, IDXD_MAX_OPCAP_BITS / 8); 974 for_each_set_bit(n, wq->opcap_bmap, IDXD_MAX_OPCAP_BITS) { 975 int pos = n % BITS_PER_LONG_LONG; 976 int idx = n / BITS_PER_LONG_LONG; 977 978 wq->wqcfg->op_config[idx] |= BIT(pos); 979 } 980 } 981 982 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 983 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 984 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 985 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); 986 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 987 wq->id, i, wq_offset, 988 ioread32(idxd->reg_base + wq_offset)); 989 } 990 991 return 0; 992 } 993 994 static int idxd_wqs_config_write(struct idxd_device *idxd) 995 { 996 int i, rc; 997 998 for (i = 0; i < idxd->max_wqs; i++) { 999 struct idxd_wq *wq = idxd->wqs[i]; 1000 1001 rc = idxd_wq_config_write(wq); 1002 if (rc < 0) 1003 return rc; 1004 } 1005 1006 return 0; 1007 } 1008 1009 static void idxd_group_flags_setup(struct idxd_device *idxd) 1010 { 1011 int i; 1012 1013 /* TC-A 0 and TC-B 1 should be defaults */ 1014 for (i = 0; i < idxd->max_groups; i++) { 1015 struct idxd_group *group = idxd->groups[i]; 1016 1017 if (group->tc_a == -1) 1018 group->tc_a = group->grpcfg.flags.tc_a = 0; 1019 else 1020 group->grpcfg.flags.tc_a = group->tc_a; 1021 if (group->tc_b == -1) 1022 group->tc_b = group->grpcfg.flags.tc_b = 1; 1023 else 1024 group->grpcfg.flags.tc_b = group->tc_b; 1025 group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit; 1026 group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved; 1027 group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed; 1028 group->grpcfg.flags.desc_progress_limit = group->desc_progress_limit; 1029 group->grpcfg.flags.batch_progress_limit = group->batch_progress_limit; 1030 } 1031 } 1032 1033 static int idxd_engines_setup(struct idxd_device *idxd) 1034 { 1035 int i, engines = 0; 1036 struct idxd_engine *eng; 1037 struct idxd_group *group; 1038 1039 for (i = 0; i < idxd->max_groups; i++) { 1040 group = idxd->groups[i]; 1041 group->grpcfg.engines = 0; 1042 } 1043 1044 for (i = 0; i < idxd->max_engines; i++) { 1045 eng = idxd->engines[i]; 1046 group = eng->group; 1047 1048 if (!group) 1049 continue; 1050 1051 group->grpcfg.engines |= BIT(eng->id); 1052 engines++; 1053 } 1054 1055 if (!engines) 1056 return -EINVAL; 1057 1058 return 0; 1059 } 1060 1061 static int idxd_wqs_setup(struct idxd_device *idxd) 1062 { 1063 struct idxd_wq *wq; 1064 struct idxd_group *group; 1065 int i, j, configured = 0; 1066 struct device *dev = &idxd->pdev->dev; 1067 1068 for (i = 0; i < idxd->max_groups; i++) { 1069 group = idxd->groups[i]; 1070 for (j = 0; j < 4; j++) 1071 group->grpcfg.wqs[j] = 0; 1072 } 1073 1074 for (i = 0; i < idxd->max_wqs; i++) { 1075 wq = idxd->wqs[i]; 1076 group = wq->group; 1077 1078 if (!wq->group) 1079 continue; 1080 1081 if (wq_shared(wq) && !wq_shared_supported(wq)) { 1082 idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT; 1083 dev_warn(dev, "No shared wq support but configured.\n"); 1084 return -EINVAL; 1085 } 1086 1087 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 1088 configured++; 1089 } 1090 1091 if (configured == 0) { 1092 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED; 1093 return -EINVAL; 1094 } 1095 1096 return 0; 1097 } 1098 1099 int idxd_device_config(struct idxd_device *idxd) 1100 { 1101 int rc; 1102 1103 lockdep_assert_held(&idxd->dev_lock); 1104 rc = idxd_wqs_setup(idxd); 1105 if (rc < 0) 1106 return rc; 1107 1108 rc = idxd_engines_setup(idxd); 1109 if (rc < 0) 1110 return rc; 1111 1112 idxd_group_flags_setup(idxd); 1113 1114 rc = idxd_wqs_config_write(idxd); 1115 if (rc < 0) 1116 return rc; 1117 1118 rc = idxd_groups_config_write(idxd); 1119 if (rc < 0) 1120 return rc; 1121 1122 return 0; 1123 } 1124 1125 static int idxd_wq_load_config(struct idxd_wq *wq) 1126 { 1127 struct idxd_device *idxd = wq->idxd; 1128 struct device *dev = &idxd->pdev->dev; 1129 int wqcfg_offset; 1130 int i; 1131 1132 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0); 1133 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size); 1134 1135 wq->size = wq->wqcfg->wq_size; 1136 wq->threshold = wq->wqcfg->wq_thresh; 1137 1138 /* The driver does not support shared WQ mode in read-only config yet */ 1139 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en) 1140 return -EOPNOTSUPP; 1141 1142 set_bit(WQ_FLAG_DEDICATED, &wq->flags); 1143 1144 wq->priority = wq->wqcfg->priority; 1145 1146 wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift; 1147 idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift); 1148 1149 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1150 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i); 1151 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]); 1152 } 1153 1154 return 0; 1155 } 1156 1157 static void idxd_group_load_config(struct idxd_group *group) 1158 { 1159 struct idxd_device *idxd = group->idxd; 1160 struct device *dev = &idxd->pdev->dev; 1161 int i, j, grpcfg_offset; 1162 1163 /* 1164 * Load WQS bit fields 1165 * Iterate through all 256 bits 64 bits at a time 1166 */ 1167 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 1168 struct idxd_wq *wq; 1169 1170 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 1171 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset); 1172 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 1173 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]); 1174 1175 if (i * 64 >= idxd->max_wqs) 1176 break; 1177 1178 /* Iterate through all 64 bits and check for wq set */ 1179 for (j = 0; j < 64; j++) { 1180 int id = i * 64 + j; 1181 1182 /* No need to check beyond max wqs */ 1183 if (id >= idxd->max_wqs) 1184 break; 1185 1186 /* Set group assignment for wq if wq bit is set */ 1187 if (group->grpcfg.wqs[i] & BIT(j)) { 1188 wq = idxd->wqs[id]; 1189 wq->group = group; 1190 } 1191 } 1192 } 1193 1194 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 1195 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset); 1196 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 1197 grpcfg_offset, group->grpcfg.engines); 1198 1199 /* Iterate through all 64 bits to check engines set */ 1200 for (i = 0; i < 64; i++) { 1201 if (i >= idxd->max_engines) 1202 break; 1203 1204 if (group->grpcfg.engines & BIT(i)) { 1205 struct idxd_engine *engine = idxd->engines[i]; 1206 1207 engine->group = group; 1208 } 1209 } 1210 1211 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 1212 group->grpcfg.flags.bits = ioread64(idxd->reg_base + grpcfg_offset); 1213 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n", 1214 group->id, grpcfg_offset, group->grpcfg.flags.bits); 1215 } 1216 1217 int idxd_device_load_config(struct idxd_device *idxd) 1218 { 1219 union gencfg_reg reg; 1220 int i, rc; 1221 1222 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 1223 idxd->rdbuf_limit = reg.rdbuf_limit; 1224 1225 for (i = 0; i < idxd->max_groups; i++) { 1226 struct idxd_group *group = idxd->groups[i]; 1227 1228 idxd_group_load_config(group); 1229 } 1230 1231 for (i = 0; i < idxd->max_wqs; i++) { 1232 struct idxd_wq *wq = idxd->wqs[i]; 1233 1234 rc = idxd_wq_load_config(wq); 1235 if (rc < 0) 1236 return rc; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static void idxd_flush_pending_descs(struct idxd_irq_entry *ie) 1243 { 1244 struct idxd_desc *desc, *itr; 1245 struct llist_node *head; 1246 LIST_HEAD(flist); 1247 enum idxd_complete_type ctype; 1248 1249 spin_lock(&ie->list_lock); 1250 head = llist_del_all(&ie->pending_llist); 1251 if (head) { 1252 llist_for_each_entry_safe(desc, itr, head, llnode) 1253 list_add_tail(&desc->list, &ie->work_list); 1254 } 1255 1256 list_for_each_entry_safe(desc, itr, &ie->work_list, list) 1257 list_move_tail(&desc->list, &flist); 1258 spin_unlock(&ie->list_lock); 1259 1260 list_for_each_entry_safe(desc, itr, &flist, list) { 1261 struct dma_async_tx_descriptor *tx; 1262 1263 list_del(&desc->list); 1264 ctype = desc->completion->status ? IDXD_COMPLETE_NORMAL : IDXD_COMPLETE_ABORT; 1265 /* 1266 * wq is being disabled. Any remaining descriptors are 1267 * likely to be stuck and can be dropped. callback could 1268 * point to code that is no longer accessible, for example 1269 * if dmatest module has been unloaded. 1270 */ 1271 tx = &desc->txd; 1272 tx->callback = NULL; 1273 tx->callback_result = NULL; 1274 idxd_dma_complete_txd(desc, ctype, true, NULL, NULL); 1275 } 1276 } 1277 1278 static void idxd_device_set_perm_entry(struct idxd_device *idxd, 1279 struct idxd_irq_entry *ie) 1280 { 1281 union msix_perm mperm; 1282 1283 if (ie->pasid == IOMMU_PASID_INVALID) 1284 return; 1285 1286 mperm.bits = 0; 1287 mperm.pasid = ie->pasid; 1288 mperm.pasid_en = 1; 1289 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8); 1290 } 1291 1292 static void idxd_device_clear_perm_entry(struct idxd_device *idxd, 1293 struct idxd_irq_entry *ie) 1294 { 1295 iowrite32(0, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8); 1296 } 1297 1298 void idxd_wq_free_irq(struct idxd_wq *wq) 1299 { 1300 struct idxd_device *idxd = wq->idxd; 1301 struct idxd_irq_entry *ie = &wq->ie; 1302 1303 if (wq->type != IDXD_WQT_KERNEL) 1304 return; 1305 1306 free_irq(ie->vector, ie); 1307 idxd_flush_pending_descs(ie); 1308 if (idxd->request_int_handles) 1309 idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX); 1310 idxd_device_clear_perm_entry(idxd, ie); 1311 ie->vector = -1; 1312 ie->int_handle = INVALID_INT_HANDLE; 1313 ie->pasid = IOMMU_PASID_INVALID; 1314 } 1315 1316 int idxd_wq_request_irq(struct idxd_wq *wq) 1317 { 1318 struct idxd_device *idxd = wq->idxd; 1319 struct pci_dev *pdev = idxd->pdev; 1320 struct device *dev = &pdev->dev; 1321 struct idxd_irq_entry *ie; 1322 int rc; 1323 1324 if (wq->type != IDXD_WQT_KERNEL) 1325 return 0; 1326 1327 ie = &wq->ie; 1328 ie->vector = pci_irq_vector(pdev, ie->id); 1329 ie->pasid = device_pasid_enabled(idxd) ? idxd->pasid : IOMMU_PASID_INVALID; 1330 idxd_device_set_perm_entry(idxd, ie); 1331 1332 rc = request_threaded_irq(ie->vector, NULL, idxd_wq_thread, 0, "idxd-portal", ie); 1333 if (rc < 0) { 1334 dev_err(dev, "Failed to request irq %d.\n", ie->vector); 1335 goto err_irq; 1336 } 1337 1338 if (idxd->request_int_handles) { 1339 rc = idxd_device_request_int_handle(idxd, ie->id, &ie->int_handle, 1340 IDXD_IRQ_MSIX); 1341 if (rc < 0) 1342 goto err_int_handle; 1343 } else { 1344 ie->int_handle = ie->id; 1345 } 1346 1347 return 0; 1348 1349 err_int_handle: 1350 ie->int_handle = INVALID_INT_HANDLE; 1351 free_irq(ie->vector, ie); 1352 err_irq: 1353 idxd_device_clear_perm_entry(idxd, ie); 1354 ie->pasid = IOMMU_PASID_INVALID; 1355 return rc; 1356 } 1357 1358 int idxd_drv_enable_wq(struct idxd_wq *wq) 1359 { 1360 struct idxd_device *idxd = wq->idxd; 1361 struct device *dev = &idxd->pdev->dev; 1362 int rc = -ENXIO; 1363 1364 lockdep_assert_held(&wq->wq_lock); 1365 1366 if (idxd->state != IDXD_DEV_ENABLED) { 1367 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED; 1368 goto err; 1369 } 1370 1371 if (wq->state != IDXD_WQ_DISABLED) { 1372 dev_dbg(dev, "wq %d already enabled.\n", wq->id); 1373 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED; 1374 rc = -EBUSY; 1375 goto err; 1376 } 1377 1378 if (!wq->group) { 1379 dev_dbg(dev, "wq %d not attached to group.\n", wq->id); 1380 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP; 1381 goto err; 1382 } 1383 1384 if (strlen(wq->name) == 0) { 1385 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME; 1386 dev_dbg(dev, "wq %d name not set.\n", wq->id); 1387 goto err; 1388 } 1389 1390 /* Shared WQ checks */ 1391 if (wq_shared(wq)) { 1392 if (!wq_shared_supported(wq)) { 1393 idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM; 1394 dev_dbg(dev, "PASID not enabled and shared wq.\n"); 1395 goto err; 1396 } 1397 /* 1398 * Shared wq with the threshold set to 0 means the user 1399 * did not set the threshold or transitioned from a 1400 * dedicated wq but did not set threshold. A value 1401 * of 0 would effectively disable the shared wq. The 1402 * driver does not allow a value of 0 to be set for 1403 * threshold via sysfs. 1404 */ 1405 if (wq->threshold == 0) { 1406 idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH; 1407 dev_dbg(dev, "Shared wq and threshold 0.\n"); 1408 goto err; 1409 } 1410 } 1411 1412 /* 1413 * In the event that the WQ is configurable for pasid, the driver 1414 * should setup the pasid, pasid_en bit. This is true for both kernel 1415 * and user shared workqueues. There is no need to setup priv bit in 1416 * that in-kernel DMA will also do user privileged requests. 1417 * A dedicated wq that is not 'kernel' type will configure pasid and 1418 * pasid_en later on so there is no need to setup. 1419 */ 1420 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 1421 if (wq_pasid_enabled(wq)) { 1422 if (is_idxd_wq_kernel(wq) || wq_shared(wq)) { 1423 u32 pasid = wq_dedicated(wq) ? idxd->pasid : 0; 1424 1425 __idxd_wq_set_pasid_locked(wq, pasid); 1426 } 1427 } 1428 } 1429 1430 rc = 0; 1431 spin_lock(&idxd->dev_lock); 1432 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1433 rc = idxd_device_config(idxd); 1434 spin_unlock(&idxd->dev_lock); 1435 if (rc < 0) { 1436 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc); 1437 goto err; 1438 } 1439 1440 rc = idxd_wq_enable(wq); 1441 if (rc < 0) { 1442 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc); 1443 goto err; 1444 } 1445 1446 rc = idxd_wq_map_portal(wq); 1447 if (rc < 0) { 1448 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR; 1449 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc); 1450 goto err_map_portal; 1451 } 1452 1453 wq->client_count = 0; 1454 1455 rc = idxd_wq_request_irq(wq); 1456 if (rc < 0) { 1457 idxd->cmd_status = IDXD_SCMD_WQ_IRQ_ERR; 1458 dev_dbg(dev, "WQ %d irq setup failed: %d\n", wq->id, rc); 1459 goto err_irq; 1460 } 1461 1462 rc = idxd_wq_alloc_resources(wq); 1463 if (rc < 0) { 1464 idxd->cmd_status = IDXD_SCMD_WQ_RES_ALLOC_ERR; 1465 dev_dbg(dev, "WQ resource alloc failed\n"); 1466 goto err_res_alloc; 1467 } 1468 1469 rc = idxd_wq_init_percpu_ref(wq); 1470 if (rc < 0) { 1471 idxd->cmd_status = IDXD_SCMD_PERCPU_ERR; 1472 dev_dbg(dev, "percpu_ref setup failed\n"); 1473 goto err_ref; 1474 } 1475 1476 return 0; 1477 1478 err_ref: 1479 idxd_wq_free_resources(wq); 1480 err_res_alloc: 1481 idxd_wq_free_irq(wq); 1482 err_irq: 1483 idxd_wq_unmap_portal(wq); 1484 err_map_portal: 1485 if (idxd_wq_disable(wq, false)) 1486 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq))); 1487 err: 1488 return rc; 1489 } 1490 EXPORT_SYMBOL_NS_GPL(idxd_drv_enable_wq, IDXD); 1491 1492 void idxd_drv_disable_wq(struct idxd_wq *wq) 1493 { 1494 struct idxd_device *idxd = wq->idxd; 1495 struct device *dev = &idxd->pdev->dev; 1496 1497 lockdep_assert_held(&wq->wq_lock); 1498 1499 if (idxd_wq_refcount(wq)) 1500 dev_warn(dev, "Clients has claim on wq %d: %d\n", 1501 wq->id, idxd_wq_refcount(wq)); 1502 1503 idxd_wq_unmap_portal(wq); 1504 idxd_wq_drain(wq); 1505 idxd_wq_free_irq(wq); 1506 idxd_wq_reset(wq); 1507 idxd_wq_free_resources(wq); 1508 percpu_ref_exit(&wq->wq_active); 1509 wq->type = IDXD_WQT_NONE; 1510 wq->client_count = 0; 1511 } 1512 EXPORT_SYMBOL_NS_GPL(idxd_drv_disable_wq, IDXD); 1513 1514 int idxd_device_drv_probe(struct idxd_dev *idxd_dev) 1515 { 1516 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1517 int rc = 0; 1518 1519 /* 1520 * Device should be in disabled state for the idxd_drv to load. If it's in 1521 * enabled state, then the device was altered outside of driver's control. 1522 * If the state is in halted state, then we don't want to proceed. 1523 */ 1524 if (idxd->state != IDXD_DEV_DISABLED) { 1525 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED; 1526 return -ENXIO; 1527 } 1528 1529 /* Device configuration */ 1530 spin_lock(&idxd->dev_lock); 1531 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1532 rc = idxd_device_config(idxd); 1533 spin_unlock(&idxd->dev_lock); 1534 if (rc < 0) 1535 return -ENXIO; 1536 1537 /* 1538 * System PASID is preserved across device disable/enable cycle, but 1539 * genconfig register content gets cleared during device reset. We 1540 * need to re-enable user interrupts for kernel work queue completion 1541 * IRQ to function. 1542 */ 1543 if (idxd->pasid != IOMMU_PASID_INVALID) 1544 idxd_set_user_intr(idxd, 1); 1545 1546 rc = idxd_device_evl_setup(idxd); 1547 if (rc < 0) { 1548 idxd->cmd_status = IDXD_SCMD_DEV_EVL_ERR; 1549 return rc; 1550 } 1551 1552 /* Start device */ 1553 rc = idxd_device_enable(idxd); 1554 if (rc < 0) { 1555 idxd_device_evl_free(idxd); 1556 return rc; 1557 } 1558 1559 /* Setup DMA device without channels */ 1560 rc = idxd_register_dma_device(idxd); 1561 if (rc < 0) { 1562 idxd_device_disable(idxd); 1563 idxd_device_evl_free(idxd); 1564 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR; 1565 return rc; 1566 } 1567 1568 idxd->cmd_status = 0; 1569 return 0; 1570 } 1571 1572 void idxd_device_drv_remove(struct idxd_dev *idxd_dev) 1573 { 1574 struct device *dev = &idxd_dev->conf_dev; 1575 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1576 int i; 1577 1578 for (i = 0; i < idxd->max_wqs; i++) { 1579 struct idxd_wq *wq = idxd->wqs[i]; 1580 struct device *wq_dev = wq_confdev(wq); 1581 1582 if (wq->state == IDXD_WQ_DISABLED) 1583 continue; 1584 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev)); 1585 device_release_driver(wq_dev); 1586 } 1587 1588 idxd_unregister_dma_device(idxd); 1589 idxd_device_disable(idxd); 1590 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1591 idxd_device_reset(idxd); 1592 idxd_device_evl_free(idxd); 1593 } 1594 1595 static enum idxd_dev_type dev_types[] = { 1596 IDXD_DEV_DSA, 1597 IDXD_DEV_IAX, 1598 IDXD_DEV_NONE, 1599 }; 1600 1601 struct idxd_device_driver idxd_drv = { 1602 .type = dev_types, 1603 .probe = idxd_device_drv_probe, 1604 .remove = idxd_device_drv_remove, 1605 .name = "idxd", 1606 }; 1607 EXPORT_SYMBOL_GPL(idxd_drv); 1608