1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <linux/irq.h> 10 #include <uapi/linux/idxd.h> 11 #include "../dmaengine.h" 12 #include "idxd.h" 13 #include "registers.h" 14 15 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 16 u32 *status); 17 static void idxd_device_wqs_clear_state(struct idxd_device *idxd); 18 static void idxd_wq_disable_cleanup(struct idxd_wq *wq); 19 static int idxd_wq_config_write(struct idxd_wq *wq); 20 21 /* Interrupt control bits */ 22 void idxd_unmask_error_interrupts(struct idxd_device *idxd) 23 { 24 union genctrl_reg genctrl; 25 26 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 27 genctrl.softerr_int_en = 1; 28 genctrl.halt_int_en = 1; 29 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 30 } 31 32 void idxd_mask_error_interrupts(struct idxd_device *idxd) 33 { 34 union genctrl_reg genctrl; 35 36 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 37 genctrl.softerr_int_en = 0; 38 genctrl.halt_int_en = 0; 39 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 40 } 41 42 static void free_hw_descs(struct idxd_wq *wq) 43 { 44 int i; 45 46 for (i = 0; i < wq->num_descs; i++) 47 kfree(wq->hw_descs[i]); 48 49 kfree(wq->hw_descs); 50 } 51 52 static int alloc_hw_descs(struct idxd_wq *wq, int num) 53 { 54 struct device *dev = &wq->idxd->pdev->dev; 55 int i; 56 int node = dev_to_node(dev); 57 58 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), 59 GFP_KERNEL, node); 60 if (!wq->hw_descs) 61 return -ENOMEM; 62 63 for (i = 0; i < num; i++) { 64 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), 65 GFP_KERNEL, node); 66 if (!wq->hw_descs[i]) { 67 free_hw_descs(wq); 68 return -ENOMEM; 69 } 70 } 71 72 return 0; 73 } 74 75 static void free_descs(struct idxd_wq *wq) 76 { 77 int i; 78 79 for (i = 0; i < wq->num_descs; i++) 80 kfree(wq->descs[i]); 81 82 kfree(wq->descs); 83 } 84 85 static int alloc_descs(struct idxd_wq *wq, int num) 86 { 87 struct device *dev = &wq->idxd->pdev->dev; 88 int i; 89 int node = dev_to_node(dev); 90 91 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), 92 GFP_KERNEL, node); 93 if (!wq->descs) 94 return -ENOMEM; 95 96 for (i = 0; i < num; i++) { 97 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), 98 GFP_KERNEL, node); 99 if (!wq->descs[i]) { 100 free_descs(wq); 101 return -ENOMEM; 102 } 103 } 104 105 return 0; 106 } 107 108 /* WQ control bits */ 109 int idxd_wq_alloc_resources(struct idxd_wq *wq) 110 { 111 struct idxd_device *idxd = wq->idxd; 112 struct device *dev = &idxd->pdev->dev; 113 int rc, num_descs, i; 114 115 if (wq->type != IDXD_WQT_KERNEL) 116 return 0; 117 118 num_descs = wq_dedicated(wq) ? wq->size : wq->threshold; 119 wq->num_descs = num_descs; 120 121 rc = alloc_hw_descs(wq, num_descs); 122 if (rc < 0) 123 return rc; 124 125 wq->compls_size = num_descs * idxd->data->compl_size; 126 wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL); 127 if (!wq->compls) { 128 rc = -ENOMEM; 129 goto fail_alloc_compls; 130 } 131 132 rc = alloc_descs(wq, num_descs); 133 if (rc < 0) 134 goto fail_alloc_descs; 135 136 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL, 137 dev_to_node(dev)); 138 if (rc < 0) 139 goto fail_sbitmap_init; 140 141 for (i = 0; i < num_descs; i++) { 142 struct idxd_desc *desc = wq->descs[i]; 143 144 desc->hw = wq->hw_descs[i]; 145 if (idxd->data->type == IDXD_TYPE_DSA) 146 desc->completion = &wq->compls[i]; 147 else if (idxd->data->type == IDXD_TYPE_IAX) 148 desc->iax_completion = &wq->iax_compls[i]; 149 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i; 150 desc->id = i; 151 desc->wq = wq; 152 desc->cpu = -1; 153 } 154 155 return 0; 156 157 fail_sbitmap_init: 158 free_descs(wq); 159 fail_alloc_descs: 160 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 161 fail_alloc_compls: 162 free_hw_descs(wq); 163 return rc; 164 } 165 EXPORT_SYMBOL_NS_GPL(idxd_wq_alloc_resources, "IDXD"); 166 167 void idxd_wq_free_resources(struct idxd_wq *wq) 168 { 169 struct device *dev = &wq->idxd->pdev->dev; 170 171 if (wq->type != IDXD_WQT_KERNEL) 172 return; 173 174 free_hw_descs(wq); 175 free_descs(wq); 176 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 177 sbitmap_queue_free(&wq->sbq); 178 } 179 EXPORT_SYMBOL_NS_GPL(idxd_wq_free_resources, "IDXD"); 180 181 int idxd_wq_enable(struct idxd_wq *wq) 182 { 183 struct idxd_device *idxd = wq->idxd; 184 struct device *dev = &idxd->pdev->dev; 185 u32 status; 186 187 if (wq->state == IDXD_WQ_ENABLED) { 188 dev_dbg(dev, "WQ %d already enabled\n", wq->id); 189 return 0; 190 } 191 192 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status); 193 194 if (status != IDXD_CMDSTS_SUCCESS && 195 status != IDXD_CMDSTS_ERR_WQ_ENABLED) { 196 dev_dbg(dev, "WQ enable failed: %#x\n", status); 197 return -ENXIO; 198 } 199 200 wq->state = IDXD_WQ_ENABLED; 201 set_bit(wq->id, idxd->wq_enable_map); 202 dev_dbg(dev, "WQ %d enabled\n", wq->id); 203 return 0; 204 } 205 206 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config) 207 { 208 struct idxd_device *idxd = wq->idxd; 209 struct device *dev = &idxd->pdev->dev; 210 u32 status, operand; 211 212 dev_dbg(dev, "Disabling WQ %d\n", wq->id); 213 214 if (wq->state != IDXD_WQ_ENABLED) { 215 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 216 return 0; 217 } 218 219 /* 220 * Disable WQ does not drain address translations, if WQ attributes are 221 * changed before translations are drained, pending translations can 222 * be issued using updated WQ attibutes, resulting in invalid 223 * translations being cached in the device translation cache. 224 * 225 * To make sure pending translations are drained before WQ 226 * attributes are changed, we use a WQ Drain followed by WQ Reset and 227 * then restore the WQ configuration. 228 */ 229 idxd_wq_drain(wq); 230 231 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 232 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, &status); 233 234 if (status != IDXD_CMDSTS_SUCCESS) { 235 dev_dbg(dev, "WQ reset failed: %#x\n", status); 236 return -ENXIO; 237 } 238 239 idxd_wq_config_write(wq); 240 241 if (reset_config) 242 idxd_wq_disable_cleanup(wq); 243 clear_bit(wq->id, idxd->wq_enable_map); 244 wq->state = IDXD_WQ_DISABLED; 245 dev_dbg(dev, "WQ %d disabled\n", wq->id); 246 return 0; 247 } 248 249 void idxd_wq_drain(struct idxd_wq *wq) 250 { 251 struct idxd_device *idxd = wq->idxd; 252 struct device *dev = &idxd->pdev->dev; 253 u32 operand; 254 255 if (wq->state != IDXD_WQ_ENABLED) { 256 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 257 return; 258 } 259 260 dev_dbg(dev, "Draining WQ %d\n", wq->id); 261 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 262 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL); 263 } 264 265 void idxd_wq_reset(struct idxd_wq *wq) 266 { 267 struct idxd_device *idxd = wq->idxd; 268 struct device *dev = &idxd->pdev->dev; 269 u32 operand; 270 271 if (wq->state != IDXD_WQ_ENABLED) { 272 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 273 return; 274 } 275 276 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 277 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL); 278 idxd_wq_disable_cleanup(wq); 279 } 280 281 int idxd_wq_map_portal(struct idxd_wq *wq) 282 { 283 struct idxd_device *idxd = wq->idxd; 284 struct pci_dev *pdev = idxd->pdev; 285 struct device *dev = &pdev->dev; 286 resource_size_t start; 287 288 start = pci_resource_start(pdev, IDXD_WQ_BAR); 289 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED); 290 291 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 292 if (!wq->portal) 293 return -ENOMEM; 294 295 return 0; 296 } 297 298 void idxd_wq_unmap_portal(struct idxd_wq *wq) 299 { 300 struct device *dev = &wq->idxd->pdev->dev; 301 302 devm_iounmap(dev, wq->portal); 303 wq->portal = NULL; 304 wq->portal_offset = 0; 305 } 306 307 void idxd_wqs_unmap_portal(struct idxd_device *idxd) 308 { 309 int i; 310 311 for (i = 0; i < idxd->max_wqs; i++) { 312 struct idxd_wq *wq = idxd->wqs[i]; 313 314 if (wq->portal) 315 idxd_wq_unmap_portal(wq); 316 } 317 } 318 319 static void __idxd_wq_set_pasid_locked(struct idxd_wq *wq, int pasid) 320 { 321 struct idxd_device *idxd = wq->idxd; 322 union wqcfg wqcfg; 323 unsigned int offset; 324 325 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 326 spin_lock(&idxd->dev_lock); 327 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 328 wqcfg.pasid_en = 1; 329 wqcfg.pasid = pasid; 330 wq->wqcfg->bits[WQCFG_PASID_IDX] = wqcfg.bits[WQCFG_PASID_IDX]; 331 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 332 spin_unlock(&idxd->dev_lock); 333 } 334 335 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid) 336 { 337 int rc; 338 339 rc = idxd_wq_disable(wq, false); 340 if (rc < 0) 341 return rc; 342 343 __idxd_wq_set_pasid_locked(wq, pasid); 344 345 rc = idxd_wq_enable(wq); 346 if (rc < 0) 347 return rc; 348 349 return 0; 350 } 351 352 int idxd_wq_disable_pasid(struct idxd_wq *wq) 353 { 354 struct idxd_device *idxd = wq->idxd; 355 int rc; 356 union wqcfg wqcfg; 357 unsigned int offset; 358 359 rc = idxd_wq_disable(wq, false); 360 if (rc < 0) 361 return rc; 362 363 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 364 spin_lock(&idxd->dev_lock); 365 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 366 wqcfg.pasid_en = 0; 367 wqcfg.pasid = 0; 368 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 369 spin_unlock(&idxd->dev_lock); 370 371 rc = idxd_wq_enable(wq); 372 if (rc < 0) 373 return rc; 374 375 return 0; 376 } 377 378 static void idxd_wq_disable_cleanup(struct idxd_wq *wq) 379 { 380 struct idxd_device *idxd = wq->idxd; 381 382 lockdep_assert_held(&wq->wq_lock); 383 wq->state = IDXD_WQ_DISABLED; 384 memset(wq->wqcfg, 0, idxd->wqcfg_size); 385 wq->type = IDXD_WQT_NONE; 386 wq->threshold = 0; 387 wq->priority = 0; 388 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 389 wq->flags = 0; 390 memset(wq->name, 0, WQ_NAME_SIZE); 391 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 392 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 393 if (wq->opcap_bmap) 394 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 395 } 396 397 static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq) 398 { 399 lockdep_assert_held(&wq->wq_lock); 400 401 wq->size = 0; 402 wq->group = NULL; 403 } 404 405 static void idxd_wq_ref_release(struct percpu_ref *ref) 406 { 407 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active); 408 409 complete(&wq->wq_dead); 410 } 411 412 int idxd_wq_init_percpu_ref(struct idxd_wq *wq) 413 { 414 int rc; 415 416 memset(&wq->wq_active, 0, sizeof(wq->wq_active)); 417 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 418 PERCPU_REF_ALLOW_REINIT, GFP_KERNEL); 419 if (rc < 0) 420 return rc; 421 reinit_completion(&wq->wq_dead); 422 reinit_completion(&wq->wq_resurrect); 423 return 0; 424 } 425 EXPORT_SYMBOL_NS_GPL(idxd_wq_init_percpu_ref, "IDXD"); 426 427 void __idxd_wq_quiesce(struct idxd_wq *wq) 428 { 429 lockdep_assert_held(&wq->wq_lock); 430 reinit_completion(&wq->wq_resurrect); 431 percpu_ref_kill(&wq->wq_active); 432 complete_all(&wq->wq_resurrect); 433 wait_for_completion(&wq->wq_dead); 434 } 435 EXPORT_SYMBOL_NS_GPL(__idxd_wq_quiesce, "IDXD"); 436 437 void idxd_wq_quiesce(struct idxd_wq *wq) 438 { 439 mutex_lock(&wq->wq_lock); 440 __idxd_wq_quiesce(wq); 441 mutex_unlock(&wq->wq_lock); 442 } 443 EXPORT_SYMBOL_NS_GPL(idxd_wq_quiesce, "IDXD"); 444 445 /* Device control bits */ 446 static inline bool idxd_is_enabled(struct idxd_device *idxd) 447 { 448 union gensts_reg gensts; 449 450 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 451 452 if (gensts.state == IDXD_DEVICE_STATE_ENABLED) 453 return true; 454 return false; 455 } 456 457 static inline bool idxd_device_is_halted(struct idxd_device *idxd) 458 { 459 union gensts_reg gensts; 460 461 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 462 463 return (gensts.state == IDXD_DEVICE_STATE_HALT); 464 } 465 466 /* 467 * This is function is only used for reset during probe and will 468 * poll for completion. Once the device is setup with interrupts, 469 * all commands will be done via interrupt completion. 470 */ 471 int idxd_device_init_reset(struct idxd_device *idxd) 472 { 473 struct device *dev = &idxd->pdev->dev; 474 union idxd_command_reg cmd; 475 476 if (idxd_device_is_halted(idxd)) { 477 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 478 return -ENXIO; 479 } 480 481 memset(&cmd, 0, sizeof(cmd)); 482 cmd.cmd = IDXD_CMD_RESET_DEVICE; 483 dev_dbg(dev, "%s: sending reset for init.\n", __func__); 484 spin_lock(&idxd->cmd_lock); 485 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 486 487 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & 488 IDXD_CMDSTS_ACTIVE) 489 cpu_relax(); 490 spin_unlock(&idxd->cmd_lock); 491 return 0; 492 } 493 494 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 495 u32 *status) 496 { 497 union idxd_command_reg cmd; 498 DECLARE_COMPLETION_ONSTACK(done); 499 u32 stat; 500 unsigned long flags; 501 502 if (idxd_device_is_halted(idxd)) { 503 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 504 if (status) 505 *status = IDXD_CMDSTS_HW_ERR; 506 return; 507 } 508 509 memset(&cmd, 0, sizeof(cmd)); 510 cmd.cmd = cmd_code; 511 cmd.operand = operand; 512 cmd.int_req = 1; 513 514 spin_lock_irqsave(&idxd->cmd_lock, flags); 515 wait_event_lock_irq(idxd->cmd_waitq, 516 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags), 517 idxd->cmd_lock); 518 519 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n", 520 __func__, cmd_code, operand); 521 522 idxd->cmd_status = 0; 523 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 524 idxd->cmd_done = &done; 525 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 526 527 /* 528 * After command submitted, release lock and go to sleep until 529 * the command completes via interrupt. 530 */ 531 spin_unlock_irqrestore(&idxd->cmd_lock, flags); 532 wait_for_completion(&done); 533 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 534 spin_lock(&idxd->cmd_lock); 535 if (status) 536 *status = stat; 537 idxd->cmd_status = stat & GENMASK(7, 0); 538 539 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 540 /* Wake up other pending commands */ 541 wake_up(&idxd->cmd_waitq); 542 spin_unlock(&idxd->cmd_lock); 543 } 544 545 int idxd_device_enable(struct idxd_device *idxd) 546 { 547 struct device *dev = &idxd->pdev->dev; 548 u32 status; 549 550 if (idxd_is_enabled(idxd)) { 551 dev_dbg(dev, "Device already enabled\n"); 552 return -ENXIO; 553 } 554 555 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status); 556 557 /* If the command is successful or if the device was enabled */ 558 if (status != IDXD_CMDSTS_SUCCESS && 559 status != IDXD_CMDSTS_ERR_DEV_ENABLED) { 560 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 561 return -ENXIO; 562 } 563 564 idxd->state = IDXD_DEV_ENABLED; 565 return 0; 566 } 567 568 int idxd_device_disable(struct idxd_device *idxd) 569 { 570 struct device *dev = &idxd->pdev->dev; 571 u32 status; 572 573 if (!idxd_is_enabled(idxd)) { 574 dev_dbg(dev, "Device is not enabled\n"); 575 return 0; 576 } 577 578 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status); 579 580 /* If the command is successful or if the device was disabled */ 581 if (status != IDXD_CMDSTS_SUCCESS && 582 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) { 583 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 584 return -ENXIO; 585 } 586 587 idxd_device_clear_state(idxd); 588 return 0; 589 } 590 591 void idxd_device_reset(struct idxd_device *idxd) 592 { 593 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 594 idxd_device_clear_state(idxd); 595 spin_lock(&idxd->dev_lock); 596 idxd_unmask_error_interrupts(idxd); 597 spin_unlock(&idxd->dev_lock); 598 } 599 600 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid) 601 { 602 struct device *dev = &idxd->pdev->dev; 603 u32 operand; 604 605 operand = pasid; 606 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand); 607 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL); 608 dev_dbg(dev, "pasid %d drained\n", pasid); 609 } 610 611 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 612 enum idxd_interrupt_type irq_type) 613 { 614 struct device *dev = &idxd->pdev->dev; 615 u32 operand, status; 616 617 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))) 618 return -EOPNOTSUPP; 619 620 dev_dbg(dev, "get int handle, idx %d\n", idx); 621 622 operand = idx & GENMASK(15, 0); 623 if (irq_type == IDXD_IRQ_IMS) 624 operand |= CMD_INT_HANDLE_IMS; 625 626 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand); 627 628 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status); 629 630 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 631 dev_dbg(dev, "request int handle failed: %#x\n", status); 632 return -ENXIO; 633 } 634 635 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0); 636 637 dev_dbg(dev, "int handle acquired: %u\n", *handle); 638 return 0; 639 } 640 641 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 642 enum idxd_interrupt_type irq_type) 643 { 644 struct device *dev = &idxd->pdev->dev; 645 u32 operand, status; 646 union idxd_command_reg cmd; 647 648 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))) 649 return -EOPNOTSUPP; 650 651 dev_dbg(dev, "release int handle, handle %d\n", handle); 652 653 memset(&cmd, 0, sizeof(cmd)); 654 operand = handle & GENMASK(15, 0); 655 656 if (irq_type == IDXD_IRQ_IMS) 657 operand |= CMD_INT_HANDLE_IMS; 658 659 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE; 660 cmd.operand = operand; 661 662 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand); 663 664 spin_lock(&idxd->cmd_lock); 665 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 666 667 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE) 668 cpu_relax(); 669 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 670 spin_unlock(&idxd->cmd_lock); 671 672 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 673 dev_dbg(dev, "release int handle failed: %#x\n", status); 674 return -ENXIO; 675 } 676 677 dev_dbg(dev, "int handle released.\n"); 678 return 0; 679 } 680 681 /* Device configuration bits */ 682 static void idxd_engines_clear_state(struct idxd_device *idxd) 683 { 684 struct idxd_engine *engine; 685 int i; 686 687 lockdep_assert_held(&idxd->dev_lock); 688 for (i = 0; i < idxd->max_engines; i++) { 689 engine = idxd->engines[i]; 690 engine->group = NULL; 691 } 692 } 693 694 static void idxd_groups_clear_state(struct idxd_device *idxd) 695 { 696 struct idxd_group *group; 697 int i; 698 699 lockdep_assert_held(&idxd->dev_lock); 700 for (i = 0; i < idxd->max_groups; i++) { 701 group = idxd->groups[i]; 702 memset(&group->grpcfg, 0, sizeof(group->grpcfg)); 703 group->num_engines = 0; 704 group->num_wqs = 0; 705 group->use_rdbuf_limit = false; 706 /* 707 * The default value is the same as the value of 708 * total read buffers in GRPCAP. 709 */ 710 group->rdbufs_allowed = idxd->max_rdbufs; 711 group->rdbufs_reserved = 0; 712 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) { 713 group->tc_a = 1; 714 group->tc_b = 1; 715 } else { 716 group->tc_a = -1; 717 group->tc_b = -1; 718 } 719 group->desc_progress_limit = 0; 720 group->batch_progress_limit = 0; 721 } 722 } 723 724 static void idxd_device_wqs_clear_state(struct idxd_device *idxd) 725 { 726 int i; 727 728 for (i = 0; i < idxd->max_wqs; i++) { 729 struct idxd_wq *wq = idxd->wqs[i]; 730 731 mutex_lock(&wq->wq_lock); 732 idxd_wq_disable_cleanup(wq); 733 idxd_wq_device_reset_cleanup(wq); 734 mutex_unlock(&wq->wq_lock); 735 } 736 } 737 738 void idxd_device_clear_state(struct idxd_device *idxd) 739 { 740 /* IDXD is always disabled. Other states are cleared only when IDXD is configurable. */ 741 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 742 /* 743 * Clearing wq state is protected by wq lock. 744 * So no need to be protected by device lock. 745 */ 746 idxd_device_wqs_clear_state(idxd); 747 748 spin_lock(&idxd->dev_lock); 749 idxd_groups_clear_state(idxd); 750 idxd_engines_clear_state(idxd); 751 } else { 752 spin_lock(&idxd->dev_lock); 753 } 754 755 idxd->state = IDXD_DEV_DISABLED; 756 spin_unlock(&idxd->dev_lock); 757 } 758 759 static int idxd_device_evl_setup(struct idxd_device *idxd) 760 { 761 union gencfg_reg gencfg; 762 union evlcfg_reg evlcfg; 763 union genctrl_reg genctrl; 764 struct device *dev = &idxd->pdev->dev; 765 void *addr; 766 dma_addr_t dma_addr; 767 int size; 768 struct idxd_evl *evl = idxd->evl; 769 unsigned long *bmap; 770 int rc; 771 772 if (!evl) 773 return 0; 774 775 size = evl_size(idxd); 776 777 bmap = bitmap_zalloc(size, GFP_KERNEL); 778 if (!bmap) { 779 rc = -ENOMEM; 780 goto err_bmap; 781 } 782 783 /* 784 * Address needs to be page aligned. However, dma_alloc_coherent() provides 785 * at minimal page size aligned address. No manual alignment required. 786 */ 787 addr = dma_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 788 if (!addr) { 789 rc = -ENOMEM; 790 goto err_alloc; 791 } 792 793 mutex_lock(&evl->lock); 794 evl->log = addr; 795 evl->dma = dma_addr; 796 evl->log_size = size; 797 evl->bmap = bmap; 798 799 memset(&evlcfg, 0, sizeof(evlcfg)); 800 evlcfg.bits[0] = dma_addr & GENMASK(63, 12); 801 evlcfg.size = evl->size; 802 803 iowrite64(evlcfg.bits[0], idxd->reg_base + IDXD_EVLCFG_OFFSET); 804 iowrite64(evlcfg.bits[1], idxd->reg_base + IDXD_EVLCFG_OFFSET + 8); 805 806 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 807 genctrl.evl_int_en = 1; 808 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 809 810 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 811 gencfg.evl_en = 1; 812 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 813 814 mutex_unlock(&evl->lock); 815 return 0; 816 817 err_alloc: 818 bitmap_free(bmap); 819 err_bmap: 820 return rc; 821 } 822 823 static void idxd_device_evl_free(struct idxd_device *idxd) 824 { 825 void *evl_log; 826 unsigned int evl_log_size; 827 dma_addr_t evl_dma; 828 union gencfg_reg gencfg; 829 union genctrl_reg genctrl; 830 struct device *dev = &idxd->pdev->dev; 831 struct idxd_evl *evl = idxd->evl; 832 833 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 834 if (!gencfg.evl_en) 835 return; 836 837 mutex_lock(&evl->lock); 838 gencfg.evl_en = 0; 839 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 840 841 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 842 genctrl.evl_int_en = 0; 843 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 844 845 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET); 846 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET + 8); 847 848 bitmap_free(evl->bmap); 849 evl_log = evl->log; 850 evl_log_size = evl->log_size; 851 evl_dma = evl->dma; 852 evl->log = NULL; 853 evl->size = IDXD_EVL_SIZE_MIN; 854 mutex_unlock(&evl->lock); 855 856 dma_free_coherent(dev, evl_log_size, evl_log, evl_dma); 857 } 858 859 static void idxd_group_config_write(struct idxd_group *group) 860 { 861 struct idxd_device *idxd = group->idxd; 862 struct device *dev = &idxd->pdev->dev; 863 int i; 864 u32 grpcfg_offset; 865 866 dev_dbg(dev, "Writing group %d cfg registers\n", group->id); 867 868 /* setup GRPWQCFG */ 869 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 870 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 871 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset); 872 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 873 group->id, i, grpcfg_offset, 874 ioread64(idxd->reg_base + grpcfg_offset)); 875 } 876 877 /* setup GRPENGCFG */ 878 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 879 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 880 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 881 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); 882 883 /* setup GRPFLAGS */ 884 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 885 iowrite64(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); 886 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n", 887 group->id, grpcfg_offset, 888 ioread64(idxd->reg_base + grpcfg_offset)); 889 } 890 891 static int idxd_groups_config_write(struct idxd_device *idxd) 892 893 { 894 union gencfg_reg reg; 895 int i; 896 struct device *dev = &idxd->pdev->dev; 897 898 /* Setup bandwidth rdbuf limit */ 899 if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) { 900 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 901 reg.rdbuf_limit = idxd->rdbuf_limit; 902 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 903 } 904 905 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET, 906 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET)); 907 908 for (i = 0; i < idxd->max_groups; i++) { 909 struct idxd_group *group = idxd->groups[i]; 910 911 idxd_group_config_write(group); 912 } 913 914 return 0; 915 } 916 917 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd) 918 { 919 struct pci_dev *pdev = idxd->pdev; 920 921 if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV)) 922 return true; 923 return false; 924 } 925 926 static int idxd_wq_config_write(struct idxd_wq *wq) 927 { 928 struct idxd_device *idxd = wq->idxd; 929 struct device *dev = &idxd->pdev->dev; 930 u32 wq_offset; 931 int i, n; 932 933 if (!wq->group) 934 return 0; 935 936 /* 937 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after 938 * wq reset. This will copy back the sticky values that are present on some devices. 939 */ 940 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 941 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 942 wq->wqcfg->bits[i] |= ioread32(idxd->reg_base + wq_offset); 943 } 944 945 if (wq->size == 0 && wq->type != IDXD_WQT_NONE) 946 wq->size = WQ_DEFAULT_QUEUE_DEPTH; 947 948 /* byte 0-3 */ 949 wq->wqcfg->wq_size = wq->size; 950 951 /* bytes 4-7 */ 952 wq->wqcfg->wq_thresh = wq->threshold; 953 954 /* byte 8-11 */ 955 if (wq_dedicated(wq)) 956 wq->wqcfg->mode = 1; 957 958 /* 959 * The WQ priv bit is set depending on the WQ type. priv = 1 if the 960 * WQ type is kernel to indicate privileged access. This setting only 961 * matters for dedicated WQ. According to the DSA spec: 962 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the 963 * Privileged Mode Enable field of the PCI Express PASID capability 964 * is 0, this field must be 0. 965 * 966 * In the case of a dedicated kernel WQ that is not able to support 967 * the PASID cap, then the configuration will be rejected. 968 */ 969 if (wq_dedicated(wq) && wq->wqcfg->pasid_en && 970 !idxd_device_pasid_priv_enabled(idxd) && 971 wq->type == IDXD_WQT_KERNEL) { 972 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV; 973 return -EOPNOTSUPP; 974 } 975 976 wq->wqcfg->priority = wq->priority; 977 978 if (idxd->hw.gen_cap.block_on_fault && 979 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags) && 980 !test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags)) 981 wq->wqcfg->bof = 1; 982 983 if (idxd->hw.wq_cap.wq_ats_support) 984 wq->wqcfg->wq_ats_disable = test_bit(WQ_FLAG_ATS_DISABLE, &wq->flags); 985 986 if (idxd->hw.wq_cap.wq_prs_support) 987 wq->wqcfg->wq_prs_disable = test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags); 988 989 /* bytes 12-15 */ 990 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 991 idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size)); 992 993 /* bytes 32-63 */ 994 if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) { 995 memset(wq->wqcfg->op_config, 0, IDXD_MAX_OPCAP_BITS / 8); 996 for_each_set_bit(n, wq->opcap_bmap, IDXD_MAX_OPCAP_BITS) { 997 int pos = n % BITS_PER_LONG_LONG; 998 int idx = n / BITS_PER_LONG_LONG; 999 1000 wq->wqcfg->op_config[idx] |= BIT(pos); 1001 } 1002 } 1003 1004 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 1005 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1006 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 1007 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); 1008 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 1009 wq->id, i, wq_offset, 1010 ioread32(idxd->reg_base + wq_offset)); 1011 } 1012 1013 return 0; 1014 } 1015 1016 static int idxd_wqs_config_write(struct idxd_device *idxd) 1017 { 1018 int i, rc; 1019 1020 for (i = 0; i < idxd->max_wqs; i++) { 1021 struct idxd_wq *wq = idxd->wqs[i]; 1022 1023 rc = idxd_wq_config_write(wq); 1024 if (rc < 0) 1025 return rc; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static void idxd_group_flags_setup(struct idxd_device *idxd) 1032 { 1033 int i; 1034 1035 /* TC-A 0 and TC-B 1 should be defaults */ 1036 for (i = 0; i < idxd->max_groups; i++) { 1037 struct idxd_group *group = idxd->groups[i]; 1038 1039 if (group->tc_a == -1) 1040 group->tc_a = group->grpcfg.flags.tc_a = 0; 1041 else 1042 group->grpcfg.flags.tc_a = group->tc_a; 1043 if (group->tc_b == -1) 1044 group->tc_b = group->grpcfg.flags.tc_b = 1; 1045 else 1046 group->grpcfg.flags.tc_b = group->tc_b; 1047 group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit; 1048 group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved; 1049 group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed; 1050 group->grpcfg.flags.desc_progress_limit = group->desc_progress_limit; 1051 group->grpcfg.flags.batch_progress_limit = group->batch_progress_limit; 1052 } 1053 } 1054 1055 static int idxd_engines_setup(struct idxd_device *idxd) 1056 { 1057 int i, engines = 0; 1058 struct idxd_engine *eng; 1059 struct idxd_group *group; 1060 1061 for (i = 0; i < idxd->max_groups; i++) { 1062 group = idxd->groups[i]; 1063 group->grpcfg.engines = 0; 1064 } 1065 1066 for (i = 0; i < idxd->max_engines; i++) { 1067 eng = idxd->engines[i]; 1068 group = eng->group; 1069 1070 if (!group) 1071 continue; 1072 1073 group->grpcfg.engines |= BIT(eng->id); 1074 engines++; 1075 } 1076 1077 if (!engines) 1078 return -EINVAL; 1079 1080 return 0; 1081 } 1082 1083 static int idxd_wqs_setup(struct idxd_device *idxd) 1084 { 1085 struct idxd_wq *wq; 1086 struct idxd_group *group; 1087 int i, j, configured = 0; 1088 struct device *dev = &idxd->pdev->dev; 1089 1090 for (i = 0; i < idxd->max_groups; i++) { 1091 group = idxd->groups[i]; 1092 for (j = 0; j < 4; j++) 1093 group->grpcfg.wqs[j] = 0; 1094 } 1095 1096 for (i = 0; i < idxd->max_wqs; i++) { 1097 wq = idxd->wqs[i]; 1098 group = wq->group; 1099 1100 if (!wq->group) 1101 continue; 1102 1103 if (wq_shared(wq) && !wq_shared_supported(wq)) { 1104 idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT; 1105 dev_warn(dev, "No shared wq support but configured.\n"); 1106 return -EINVAL; 1107 } 1108 1109 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 1110 configured++; 1111 } 1112 1113 if (configured == 0) { 1114 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED; 1115 return -EINVAL; 1116 } 1117 1118 return 0; 1119 } 1120 1121 int idxd_device_config(struct idxd_device *idxd) 1122 { 1123 int rc; 1124 1125 lockdep_assert_held(&idxd->dev_lock); 1126 rc = idxd_wqs_setup(idxd); 1127 if (rc < 0) 1128 return rc; 1129 1130 rc = idxd_engines_setup(idxd); 1131 if (rc < 0) 1132 return rc; 1133 1134 idxd_group_flags_setup(idxd); 1135 1136 rc = idxd_wqs_config_write(idxd); 1137 if (rc < 0) 1138 return rc; 1139 1140 rc = idxd_groups_config_write(idxd); 1141 if (rc < 0) 1142 return rc; 1143 1144 return 0; 1145 } 1146 1147 static int idxd_wq_load_config(struct idxd_wq *wq) 1148 { 1149 struct idxd_device *idxd = wq->idxd; 1150 struct device *dev = &idxd->pdev->dev; 1151 int wqcfg_offset; 1152 int i; 1153 1154 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0); 1155 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size); 1156 1157 wq->size = wq->wqcfg->wq_size; 1158 wq->threshold = wq->wqcfg->wq_thresh; 1159 1160 /* The driver does not support shared WQ mode in read-only config yet */ 1161 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en) 1162 return -EOPNOTSUPP; 1163 1164 set_bit(WQ_FLAG_DEDICATED, &wq->flags); 1165 1166 wq->priority = wq->wqcfg->priority; 1167 1168 wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift; 1169 idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift); 1170 1171 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1172 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i); 1173 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]); 1174 } 1175 1176 return 0; 1177 } 1178 1179 static void idxd_group_load_config(struct idxd_group *group) 1180 { 1181 struct idxd_device *idxd = group->idxd; 1182 struct device *dev = &idxd->pdev->dev; 1183 int i, j, grpcfg_offset; 1184 1185 /* 1186 * Load WQS bit fields 1187 * Iterate through all 256 bits 64 bits at a time 1188 */ 1189 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 1190 struct idxd_wq *wq; 1191 1192 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 1193 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset); 1194 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 1195 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]); 1196 1197 if (i * 64 >= idxd->max_wqs) 1198 break; 1199 1200 /* Iterate through all 64 bits and check for wq set */ 1201 for (j = 0; j < 64; j++) { 1202 int id = i * 64 + j; 1203 1204 /* No need to check beyond max wqs */ 1205 if (id >= idxd->max_wqs) 1206 break; 1207 1208 /* Set group assignment for wq if wq bit is set */ 1209 if (group->grpcfg.wqs[i] & BIT(j)) { 1210 wq = idxd->wqs[id]; 1211 wq->group = group; 1212 } 1213 } 1214 } 1215 1216 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 1217 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset); 1218 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 1219 grpcfg_offset, group->grpcfg.engines); 1220 1221 /* Iterate through all 64 bits to check engines set */ 1222 for (i = 0; i < 64; i++) { 1223 if (i >= idxd->max_engines) 1224 break; 1225 1226 if (group->grpcfg.engines & BIT(i)) { 1227 struct idxd_engine *engine = idxd->engines[i]; 1228 1229 engine->group = group; 1230 } 1231 } 1232 1233 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 1234 group->grpcfg.flags.bits = ioread64(idxd->reg_base + grpcfg_offset); 1235 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n", 1236 group->id, grpcfg_offset, group->grpcfg.flags.bits); 1237 } 1238 1239 int idxd_device_load_config(struct idxd_device *idxd) 1240 { 1241 union gencfg_reg reg; 1242 int i, rc; 1243 1244 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 1245 idxd->rdbuf_limit = reg.rdbuf_limit; 1246 1247 for (i = 0; i < idxd->max_groups; i++) { 1248 struct idxd_group *group = idxd->groups[i]; 1249 1250 idxd_group_load_config(group); 1251 } 1252 1253 for (i = 0; i < idxd->max_wqs; i++) { 1254 struct idxd_wq *wq = idxd->wqs[i]; 1255 1256 rc = idxd_wq_load_config(wq); 1257 if (rc < 0) 1258 return rc; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static void idxd_flush_pending_descs(struct idxd_irq_entry *ie) 1265 { 1266 struct idxd_desc *desc, *itr; 1267 struct llist_node *head; 1268 LIST_HEAD(flist); 1269 enum idxd_complete_type ctype; 1270 1271 spin_lock(&ie->list_lock); 1272 head = llist_del_all(&ie->pending_llist); 1273 if (head) { 1274 llist_for_each_entry_safe(desc, itr, head, llnode) 1275 list_add_tail(&desc->list, &ie->work_list); 1276 } 1277 1278 list_for_each_entry_safe(desc, itr, &ie->work_list, list) 1279 list_move_tail(&desc->list, &flist); 1280 spin_unlock(&ie->list_lock); 1281 1282 list_for_each_entry_safe(desc, itr, &flist, list) { 1283 struct dma_async_tx_descriptor *tx; 1284 1285 list_del(&desc->list); 1286 ctype = desc->completion->status ? IDXD_COMPLETE_NORMAL : IDXD_COMPLETE_ABORT; 1287 /* 1288 * wq is being disabled. Any remaining descriptors are 1289 * likely to be stuck and can be dropped. callback could 1290 * point to code that is no longer accessible, for example 1291 * if dmatest module has been unloaded. 1292 */ 1293 tx = &desc->txd; 1294 tx->callback = NULL; 1295 tx->callback_result = NULL; 1296 idxd_dma_complete_txd(desc, ctype, true, NULL, NULL); 1297 } 1298 } 1299 1300 static void idxd_device_set_perm_entry(struct idxd_device *idxd, 1301 struct idxd_irq_entry *ie) 1302 { 1303 union msix_perm mperm; 1304 1305 if (ie->pasid == IOMMU_PASID_INVALID) 1306 return; 1307 1308 mperm.bits = 0; 1309 mperm.pasid = ie->pasid; 1310 mperm.pasid_en = 1; 1311 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8); 1312 } 1313 1314 static void idxd_device_clear_perm_entry(struct idxd_device *idxd, 1315 struct idxd_irq_entry *ie) 1316 { 1317 iowrite32(0, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8); 1318 } 1319 1320 void idxd_wq_free_irq(struct idxd_wq *wq) 1321 { 1322 struct idxd_device *idxd = wq->idxd; 1323 struct idxd_irq_entry *ie = &wq->ie; 1324 1325 if (wq->type != IDXD_WQT_KERNEL) 1326 return; 1327 1328 free_irq(ie->vector, ie); 1329 idxd_flush_pending_descs(ie); 1330 if (idxd->request_int_handles) 1331 idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX); 1332 idxd_device_clear_perm_entry(idxd, ie); 1333 ie->vector = -1; 1334 ie->int_handle = INVALID_INT_HANDLE; 1335 ie->pasid = IOMMU_PASID_INVALID; 1336 } 1337 1338 int idxd_wq_request_irq(struct idxd_wq *wq) 1339 { 1340 struct idxd_device *idxd = wq->idxd; 1341 struct pci_dev *pdev = idxd->pdev; 1342 struct device *dev = &pdev->dev; 1343 struct idxd_irq_entry *ie; 1344 int rc; 1345 1346 if (wq->type != IDXD_WQT_KERNEL) 1347 return 0; 1348 1349 ie = &wq->ie; 1350 ie->vector = pci_irq_vector(pdev, ie->id); 1351 ie->pasid = device_pasid_enabled(idxd) ? idxd->pasid : IOMMU_PASID_INVALID; 1352 idxd_device_set_perm_entry(idxd, ie); 1353 1354 rc = request_threaded_irq(ie->vector, NULL, idxd_wq_thread, 0, "idxd-portal", ie); 1355 if (rc < 0) { 1356 dev_err(dev, "Failed to request irq %d.\n", ie->vector); 1357 goto err_irq; 1358 } 1359 1360 if (idxd->request_int_handles) { 1361 rc = idxd_device_request_int_handle(idxd, ie->id, &ie->int_handle, 1362 IDXD_IRQ_MSIX); 1363 if (rc < 0) 1364 goto err_int_handle; 1365 } else { 1366 ie->int_handle = ie->id; 1367 } 1368 1369 return 0; 1370 1371 err_int_handle: 1372 ie->int_handle = INVALID_INT_HANDLE; 1373 free_irq(ie->vector, ie); 1374 err_irq: 1375 idxd_device_clear_perm_entry(idxd, ie); 1376 ie->pasid = IOMMU_PASID_INVALID; 1377 return rc; 1378 } 1379 1380 int idxd_drv_enable_wq(struct idxd_wq *wq) 1381 { 1382 struct idxd_device *idxd = wq->idxd; 1383 struct device *dev = &idxd->pdev->dev; 1384 int rc = -ENXIO; 1385 1386 lockdep_assert_held(&wq->wq_lock); 1387 1388 if (idxd->state != IDXD_DEV_ENABLED) { 1389 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED; 1390 goto err; 1391 } 1392 1393 if (wq->state != IDXD_WQ_DISABLED) { 1394 dev_dbg(dev, "wq %d already enabled.\n", wq->id); 1395 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED; 1396 rc = -EBUSY; 1397 goto err; 1398 } 1399 1400 if (!wq->group) { 1401 dev_dbg(dev, "wq %d not attached to group.\n", wq->id); 1402 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP; 1403 goto err; 1404 } 1405 1406 if (strlen(wq->name) == 0) { 1407 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME; 1408 dev_dbg(dev, "wq %d name not set.\n", wq->id); 1409 goto err; 1410 } 1411 1412 /* Shared WQ checks */ 1413 if (wq_shared(wq)) { 1414 if (!wq_shared_supported(wq)) { 1415 idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM; 1416 dev_dbg(dev, "PASID not enabled and shared wq.\n"); 1417 goto err; 1418 } 1419 /* 1420 * Shared wq with the threshold set to 0 means the user 1421 * did not set the threshold or transitioned from a 1422 * dedicated wq but did not set threshold. A value 1423 * of 0 would effectively disable the shared wq. The 1424 * driver does not allow a value of 0 to be set for 1425 * threshold via sysfs. 1426 */ 1427 if (wq->threshold == 0) { 1428 idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH; 1429 dev_dbg(dev, "Shared wq and threshold 0.\n"); 1430 goto err; 1431 } 1432 } 1433 1434 /* 1435 * In the event that the WQ is configurable for pasid, the driver 1436 * should setup the pasid, pasid_en bit. This is true for both kernel 1437 * and user shared workqueues. There is no need to setup priv bit in 1438 * that in-kernel DMA will also do user privileged requests. 1439 * A dedicated wq that is not 'kernel' type will configure pasid and 1440 * pasid_en later on so there is no need to setup. 1441 */ 1442 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 1443 if (wq_pasid_enabled(wq)) { 1444 if (is_idxd_wq_kernel(wq) || wq_shared(wq)) { 1445 u32 pasid = wq_dedicated(wq) ? idxd->pasid : 0; 1446 1447 __idxd_wq_set_pasid_locked(wq, pasid); 1448 } 1449 } 1450 } 1451 1452 rc = 0; 1453 spin_lock(&idxd->dev_lock); 1454 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1455 rc = idxd_device_config(idxd); 1456 spin_unlock(&idxd->dev_lock); 1457 if (rc < 0) { 1458 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc); 1459 goto err; 1460 } 1461 1462 rc = idxd_wq_enable(wq); 1463 if (rc < 0) { 1464 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc); 1465 goto err; 1466 } 1467 1468 rc = idxd_wq_map_portal(wq); 1469 if (rc < 0) { 1470 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR; 1471 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc); 1472 goto err_map_portal; 1473 } 1474 1475 wq->client_count = 0; 1476 1477 rc = idxd_wq_request_irq(wq); 1478 if (rc < 0) { 1479 idxd->cmd_status = IDXD_SCMD_WQ_IRQ_ERR; 1480 dev_dbg(dev, "WQ %d irq setup failed: %d\n", wq->id, rc); 1481 goto err_irq; 1482 } 1483 1484 rc = idxd_wq_alloc_resources(wq); 1485 if (rc < 0) { 1486 idxd->cmd_status = IDXD_SCMD_WQ_RES_ALLOC_ERR; 1487 dev_dbg(dev, "WQ resource alloc failed\n"); 1488 goto err_res_alloc; 1489 } 1490 1491 rc = idxd_wq_init_percpu_ref(wq); 1492 if (rc < 0) { 1493 idxd->cmd_status = IDXD_SCMD_PERCPU_ERR; 1494 dev_dbg(dev, "percpu_ref setup failed\n"); 1495 goto err_ref; 1496 } 1497 1498 return 0; 1499 1500 err_ref: 1501 idxd_wq_free_resources(wq); 1502 err_res_alloc: 1503 idxd_wq_free_irq(wq); 1504 err_irq: 1505 idxd_wq_unmap_portal(wq); 1506 err_map_portal: 1507 if (idxd_wq_disable(wq, false)) 1508 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq))); 1509 err: 1510 return rc; 1511 } 1512 EXPORT_SYMBOL_NS_GPL(idxd_drv_enable_wq, "IDXD"); 1513 1514 void idxd_drv_disable_wq(struct idxd_wq *wq) 1515 { 1516 struct idxd_device *idxd = wq->idxd; 1517 struct device *dev = &idxd->pdev->dev; 1518 1519 lockdep_assert_held(&wq->wq_lock); 1520 1521 if (idxd_wq_refcount(wq)) 1522 dev_warn(dev, "Clients has claim on wq %d: %d\n", 1523 wq->id, idxd_wq_refcount(wq)); 1524 1525 idxd_wq_unmap_portal(wq); 1526 idxd_wq_drain(wq); 1527 idxd_wq_free_irq(wq); 1528 idxd_wq_reset(wq); 1529 idxd_wq_free_resources(wq); 1530 percpu_ref_exit(&wq->wq_active); 1531 wq->type = IDXD_WQT_NONE; 1532 wq->client_count = 0; 1533 } 1534 EXPORT_SYMBOL_NS_GPL(idxd_drv_disable_wq, "IDXD"); 1535 1536 int idxd_device_drv_probe(struct idxd_dev *idxd_dev) 1537 { 1538 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1539 int rc = 0; 1540 1541 /* 1542 * Device should be in disabled state for the idxd_drv to load. If it's in 1543 * enabled state, then the device was altered outside of driver's control. 1544 * If the state is in halted state, then we don't want to proceed. 1545 */ 1546 if (idxd->state != IDXD_DEV_DISABLED) { 1547 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED; 1548 return -ENXIO; 1549 } 1550 1551 /* Device configuration */ 1552 spin_lock(&idxd->dev_lock); 1553 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1554 rc = idxd_device_config(idxd); 1555 spin_unlock(&idxd->dev_lock); 1556 if (rc < 0) 1557 return -ENXIO; 1558 1559 /* 1560 * System PASID is preserved across device disable/enable cycle, but 1561 * genconfig register content gets cleared during device reset. We 1562 * need to re-enable user interrupts for kernel work queue completion 1563 * IRQ to function. 1564 */ 1565 if (idxd->pasid != IOMMU_PASID_INVALID) 1566 idxd_set_user_intr(idxd, 1); 1567 1568 rc = idxd_device_evl_setup(idxd); 1569 if (rc < 0) { 1570 idxd->cmd_status = IDXD_SCMD_DEV_EVL_ERR; 1571 return rc; 1572 } 1573 1574 /* Start device */ 1575 rc = idxd_device_enable(idxd); 1576 if (rc < 0) { 1577 idxd_device_evl_free(idxd); 1578 return rc; 1579 } 1580 1581 /* Setup DMA device without channels */ 1582 rc = idxd_register_dma_device(idxd); 1583 if (rc < 0) { 1584 idxd_device_disable(idxd); 1585 idxd_device_evl_free(idxd); 1586 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR; 1587 return rc; 1588 } 1589 1590 idxd->cmd_status = 0; 1591 return 0; 1592 } 1593 1594 void idxd_device_drv_remove(struct idxd_dev *idxd_dev) 1595 { 1596 struct device *dev = &idxd_dev->conf_dev; 1597 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1598 int i; 1599 1600 for (i = 0; i < idxd->max_wqs; i++) { 1601 struct idxd_wq *wq = idxd->wqs[i]; 1602 struct device *wq_dev = wq_confdev(wq); 1603 1604 if (wq->state == IDXD_WQ_DISABLED) 1605 continue; 1606 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev)); 1607 device_release_driver(wq_dev); 1608 } 1609 1610 idxd_unregister_dma_device(idxd); 1611 idxd_device_disable(idxd); 1612 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1613 idxd_device_reset(idxd); 1614 idxd_device_evl_free(idxd); 1615 } 1616 1617 static enum idxd_dev_type dev_types[] = { 1618 IDXD_DEV_DSA, 1619 IDXD_DEV_IAX, 1620 IDXD_DEV_NONE, 1621 }; 1622 1623 struct idxd_device_driver idxd_drv = { 1624 .type = dev_types, 1625 .probe = idxd_device_drv_probe, 1626 .remove = idxd_device_drv_remove, 1627 .name = "idxd", 1628 }; 1629 EXPORT_SYMBOL_GPL(idxd_drv); 1630