1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <linux/irq.h> 10 #include <linux/msi.h> 11 #include <uapi/linux/idxd.h> 12 #include "../dmaengine.h" 13 #include "idxd.h" 14 #include "registers.h" 15 16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 17 u32 *status); 18 static void idxd_device_wqs_clear_state(struct idxd_device *idxd); 19 static void idxd_wq_disable_cleanup(struct idxd_wq *wq); 20 21 /* Interrupt control bits */ 22 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id) 23 { 24 struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector); 25 26 pci_msi_mask_irq(data); 27 } 28 29 void idxd_mask_msix_vectors(struct idxd_device *idxd) 30 { 31 struct pci_dev *pdev = idxd->pdev; 32 int msixcnt = pci_msix_vec_count(pdev); 33 int i; 34 35 for (i = 0; i < msixcnt; i++) 36 idxd_mask_msix_vector(idxd, i); 37 } 38 39 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id) 40 { 41 struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector); 42 43 pci_msi_unmask_irq(data); 44 } 45 46 void idxd_unmask_error_interrupts(struct idxd_device *idxd) 47 { 48 union genctrl_reg genctrl; 49 50 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 51 genctrl.softerr_int_en = 1; 52 genctrl.halt_int_en = 1; 53 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 54 } 55 56 void idxd_mask_error_interrupts(struct idxd_device *idxd) 57 { 58 union genctrl_reg genctrl; 59 60 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 61 genctrl.softerr_int_en = 0; 62 genctrl.halt_int_en = 0; 63 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 64 } 65 66 static void free_hw_descs(struct idxd_wq *wq) 67 { 68 int i; 69 70 for (i = 0; i < wq->num_descs; i++) 71 kfree(wq->hw_descs[i]); 72 73 kfree(wq->hw_descs); 74 } 75 76 static int alloc_hw_descs(struct idxd_wq *wq, int num) 77 { 78 struct device *dev = &wq->idxd->pdev->dev; 79 int i; 80 int node = dev_to_node(dev); 81 82 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), 83 GFP_KERNEL, node); 84 if (!wq->hw_descs) 85 return -ENOMEM; 86 87 for (i = 0; i < num; i++) { 88 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), 89 GFP_KERNEL, node); 90 if (!wq->hw_descs[i]) { 91 free_hw_descs(wq); 92 return -ENOMEM; 93 } 94 } 95 96 return 0; 97 } 98 99 static void free_descs(struct idxd_wq *wq) 100 { 101 int i; 102 103 for (i = 0; i < wq->num_descs; i++) 104 kfree(wq->descs[i]); 105 106 kfree(wq->descs); 107 } 108 109 static int alloc_descs(struct idxd_wq *wq, int num) 110 { 111 struct device *dev = &wq->idxd->pdev->dev; 112 int i; 113 int node = dev_to_node(dev); 114 115 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), 116 GFP_KERNEL, node); 117 if (!wq->descs) 118 return -ENOMEM; 119 120 for (i = 0; i < num; i++) { 121 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), 122 GFP_KERNEL, node); 123 if (!wq->descs[i]) { 124 free_descs(wq); 125 return -ENOMEM; 126 } 127 } 128 129 return 0; 130 } 131 132 /* WQ control bits */ 133 int idxd_wq_alloc_resources(struct idxd_wq *wq) 134 { 135 struct idxd_device *idxd = wq->idxd; 136 struct device *dev = &idxd->pdev->dev; 137 int rc, num_descs, i; 138 139 if (wq->type != IDXD_WQT_KERNEL) 140 return 0; 141 142 num_descs = wq_dedicated(wq) ? wq->size : wq->threshold; 143 wq->num_descs = num_descs; 144 145 rc = alloc_hw_descs(wq, num_descs); 146 if (rc < 0) 147 return rc; 148 149 wq->compls_size = num_descs * idxd->data->compl_size; 150 wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL); 151 if (!wq->compls) { 152 rc = -ENOMEM; 153 goto fail_alloc_compls; 154 } 155 156 rc = alloc_descs(wq, num_descs); 157 if (rc < 0) 158 goto fail_alloc_descs; 159 160 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL, 161 dev_to_node(dev)); 162 if (rc < 0) 163 goto fail_sbitmap_init; 164 165 for (i = 0; i < num_descs; i++) { 166 struct idxd_desc *desc = wq->descs[i]; 167 168 desc->hw = wq->hw_descs[i]; 169 if (idxd->data->type == IDXD_TYPE_DSA) 170 desc->completion = &wq->compls[i]; 171 else if (idxd->data->type == IDXD_TYPE_IAX) 172 desc->iax_completion = &wq->iax_compls[i]; 173 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i; 174 desc->id = i; 175 desc->wq = wq; 176 desc->cpu = -1; 177 } 178 179 return 0; 180 181 fail_sbitmap_init: 182 free_descs(wq); 183 fail_alloc_descs: 184 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 185 fail_alloc_compls: 186 free_hw_descs(wq); 187 return rc; 188 } 189 190 void idxd_wq_free_resources(struct idxd_wq *wq) 191 { 192 struct device *dev = &wq->idxd->pdev->dev; 193 194 if (wq->type != IDXD_WQT_KERNEL) 195 return; 196 197 free_hw_descs(wq); 198 free_descs(wq); 199 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 200 sbitmap_queue_free(&wq->sbq); 201 } 202 203 int idxd_wq_enable(struct idxd_wq *wq) 204 { 205 struct idxd_device *idxd = wq->idxd; 206 struct device *dev = &idxd->pdev->dev; 207 u32 status; 208 209 if (wq->state == IDXD_WQ_ENABLED) { 210 dev_dbg(dev, "WQ %d already enabled\n", wq->id); 211 return -ENXIO; 212 } 213 214 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status); 215 216 if (status != IDXD_CMDSTS_SUCCESS && 217 status != IDXD_CMDSTS_ERR_WQ_ENABLED) { 218 dev_dbg(dev, "WQ enable failed: %#x\n", status); 219 return -ENXIO; 220 } 221 222 wq->state = IDXD_WQ_ENABLED; 223 dev_dbg(dev, "WQ %d enabled\n", wq->id); 224 return 0; 225 } 226 227 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config) 228 { 229 struct idxd_device *idxd = wq->idxd; 230 struct device *dev = &idxd->pdev->dev; 231 u32 status, operand; 232 233 dev_dbg(dev, "Disabling WQ %d\n", wq->id); 234 235 if (wq->state != IDXD_WQ_ENABLED) { 236 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 237 return 0; 238 } 239 240 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 241 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status); 242 243 if (status != IDXD_CMDSTS_SUCCESS) { 244 dev_dbg(dev, "WQ disable failed: %#x\n", status); 245 return -ENXIO; 246 } 247 248 if (reset_config) 249 idxd_wq_disable_cleanup(wq); 250 wq->state = IDXD_WQ_DISABLED; 251 dev_dbg(dev, "WQ %d disabled\n", wq->id); 252 return 0; 253 } 254 255 void idxd_wq_drain(struct idxd_wq *wq) 256 { 257 struct idxd_device *idxd = wq->idxd; 258 struct device *dev = &idxd->pdev->dev; 259 u32 operand; 260 261 if (wq->state != IDXD_WQ_ENABLED) { 262 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 263 return; 264 } 265 266 dev_dbg(dev, "Draining WQ %d\n", wq->id); 267 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 268 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL); 269 } 270 271 void idxd_wq_reset(struct idxd_wq *wq) 272 { 273 struct idxd_device *idxd = wq->idxd; 274 struct device *dev = &idxd->pdev->dev; 275 u32 operand; 276 277 if (wq->state != IDXD_WQ_ENABLED) { 278 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 279 return; 280 } 281 282 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 283 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL); 284 idxd_wq_disable_cleanup(wq); 285 wq->state = IDXD_WQ_DISABLED; 286 } 287 288 int idxd_wq_map_portal(struct idxd_wq *wq) 289 { 290 struct idxd_device *idxd = wq->idxd; 291 struct pci_dev *pdev = idxd->pdev; 292 struct device *dev = &pdev->dev; 293 resource_size_t start; 294 295 start = pci_resource_start(pdev, IDXD_WQ_BAR); 296 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED); 297 298 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 299 if (!wq->portal) 300 return -ENOMEM; 301 302 return 0; 303 } 304 305 void idxd_wq_unmap_portal(struct idxd_wq *wq) 306 { 307 struct device *dev = &wq->idxd->pdev->dev; 308 309 devm_iounmap(dev, wq->portal); 310 wq->portal = NULL; 311 wq->portal_offset = 0; 312 } 313 314 void idxd_wqs_unmap_portal(struct idxd_device *idxd) 315 { 316 int i; 317 318 for (i = 0; i < idxd->max_wqs; i++) { 319 struct idxd_wq *wq = idxd->wqs[i]; 320 321 if (wq->portal) 322 idxd_wq_unmap_portal(wq); 323 } 324 } 325 326 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid) 327 { 328 struct idxd_device *idxd = wq->idxd; 329 int rc; 330 union wqcfg wqcfg; 331 unsigned int offset; 332 333 rc = idxd_wq_disable(wq, false); 334 if (rc < 0) 335 return rc; 336 337 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 338 spin_lock(&idxd->dev_lock); 339 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 340 wqcfg.pasid_en = 1; 341 wqcfg.pasid = pasid; 342 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 343 spin_unlock(&idxd->dev_lock); 344 345 rc = idxd_wq_enable(wq); 346 if (rc < 0) 347 return rc; 348 349 return 0; 350 } 351 352 int idxd_wq_disable_pasid(struct idxd_wq *wq) 353 { 354 struct idxd_device *idxd = wq->idxd; 355 int rc; 356 union wqcfg wqcfg; 357 unsigned int offset; 358 359 rc = idxd_wq_disable(wq, false); 360 if (rc < 0) 361 return rc; 362 363 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 364 spin_lock(&idxd->dev_lock); 365 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 366 wqcfg.pasid_en = 0; 367 wqcfg.pasid = 0; 368 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 369 spin_unlock(&idxd->dev_lock); 370 371 rc = idxd_wq_enable(wq); 372 if (rc < 0) 373 return rc; 374 375 return 0; 376 } 377 378 static void idxd_wq_disable_cleanup(struct idxd_wq *wq) 379 { 380 struct idxd_device *idxd = wq->idxd; 381 382 lockdep_assert_held(&wq->wq_lock); 383 memset(wq->wqcfg, 0, idxd->wqcfg_size); 384 wq->type = IDXD_WQT_NONE; 385 wq->size = 0; 386 wq->group = NULL; 387 wq->threshold = 0; 388 wq->priority = 0; 389 wq->ats_dis = 0; 390 clear_bit(WQ_FLAG_DEDICATED, &wq->flags); 391 clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags); 392 memset(wq->name, 0, WQ_NAME_SIZE); 393 } 394 395 static void idxd_wq_ref_release(struct percpu_ref *ref) 396 { 397 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active); 398 399 complete(&wq->wq_dead); 400 } 401 402 int idxd_wq_init_percpu_ref(struct idxd_wq *wq) 403 { 404 int rc; 405 406 memset(&wq->wq_active, 0, sizeof(wq->wq_active)); 407 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 408 PERCPU_REF_ALLOW_REINIT, GFP_KERNEL); 409 if (rc < 0) 410 return rc; 411 reinit_completion(&wq->wq_dead); 412 reinit_completion(&wq->wq_resurrect); 413 return 0; 414 } 415 416 void __idxd_wq_quiesce(struct idxd_wq *wq) 417 { 418 lockdep_assert_held(&wq->wq_lock); 419 reinit_completion(&wq->wq_resurrect); 420 percpu_ref_kill(&wq->wq_active); 421 complete_all(&wq->wq_resurrect); 422 wait_for_completion(&wq->wq_dead); 423 } 424 425 void idxd_wq_quiesce(struct idxd_wq *wq) 426 { 427 mutex_lock(&wq->wq_lock); 428 __idxd_wq_quiesce(wq); 429 mutex_unlock(&wq->wq_lock); 430 } 431 432 /* Device control bits */ 433 static inline bool idxd_is_enabled(struct idxd_device *idxd) 434 { 435 union gensts_reg gensts; 436 437 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 438 439 if (gensts.state == IDXD_DEVICE_STATE_ENABLED) 440 return true; 441 return false; 442 } 443 444 static inline bool idxd_device_is_halted(struct idxd_device *idxd) 445 { 446 union gensts_reg gensts; 447 448 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 449 450 return (gensts.state == IDXD_DEVICE_STATE_HALT); 451 } 452 453 /* 454 * This is function is only used for reset during probe and will 455 * poll for completion. Once the device is setup with interrupts, 456 * all commands will be done via interrupt completion. 457 */ 458 int idxd_device_init_reset(struct idxd_device *idxd) 459 { 460 struct device *dev = &idxd->pdev->dev; 461 union idxd_command_reg cmd; 462 463 if (idxd_device_is_halted(idxd)) { 464 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 465 return -ENXIO; 466 } 467 468 memset(&cmd, 0, sizeof(cmd)); 469 cmd.cmd = IDXD_CMD_RESET_DEVICE; 470 dev_dbg(dev, "%s: sending reset for init.\n", __func__); 471 spin_lock(&idxd->cmd_lock); 472 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 473 474 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & 475 IDXD_CMDSTS_ACTIVE) 476 cpu_relax(); 477 spin_unlock(&idxd->cmd_lock); 478 return 0; 479 } 480 481 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 482 u32 *status) 483 { 484 union idxd_command_reg cmd; 485 DECLARE_COMPLETION_ONSTACK(done); 486 u32 stat; 487 488 if (idxd_device_is_halted(idxd)) { 489 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 490 if (status) 491 *status = IDXD_CMDSTS_HW_ERR; 492 return; 493 } 494 495 memset(&cmd, 0, sizeof(cmd)); 496 cmd.cmd = cmd_code; 497 cmd.operand = operand; 498 cmd.int_req = 1; 499 500 spin_lock(&idxd->cmd_lock); 501 wait_event_lock_irq(idxd->cmd_waitq, 502 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags), 503 idxd->cmd_lock); 504 505 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n", 506 __func__, cmd_code, operand); 507 508 idxd->cmd_status = 0; 509 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 510 idxd->cmd_done = &done; 511 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 512 513 /* 514 * After command submitted, release lock and go to sleep until 515 * the command completes via interrupt. 516 */ 517 spin_unlock(&idxd->cmd_lock); 518 wait_for_completion(&done); 519 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 520 spin_lock(&idxd->cmd_lock); 521 if (status) 522 *status = stat; 523 idxd->cmd_status = stat & GENMASK(7, 0); 524 525 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 526 /* Wake up other pending commands */ 527 wake_up(&idxd->cmd_waitq); 528 spin_unlock(&idxd->cmd_lock); 529 } 530 531 int idxd_device_enable(struct idxd_device *idxd) 532 { 533 struct device *dev = &idxd->pdev->dev; 534 u32 status; 535 536 if (idxd_is_enabled(idxd)) { 537 dev_dbg(dev, "Device already enabled\n"); 538 return -ENXIO; 539 } 540 541 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status); 542 543 /* If the command is successful or if the device was enabled */ 544 if (status != IDXD_CMDSTS_SUCCESS && 545 status != IDXD_CMDSTS_ERR_DEV_ENABLED) { 546 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 547 return -ENXIO; 548 } 549 550 idxd->state = IDXD_DEV_ENABLED; 551 return 0; 552 } 553 554 int idxd_device_disable(struct idxd_device *idxd) 555 { 556 struct device *dev = &idxd->pdev->dev; 557 u32 status; 558 559 if (!idxd_is_enabled(idxd)) { 560 dev_dbg(dev, "Device is not enabled\n"); 561 return 0; 562 } 563 564 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status); 565 566 /* If the command is successful or if the device was disabled */ 567 if (status != IDXD_CMDSTS_SUCCESS && 568 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) { 569 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 570 return -ENXIO; 571 } 572 573 spin_lock(&idxd->dev_lock); 574 idxd_device_clear_state(idxd); 575 idxd->state = IDXD_DEV_DISABLED; 576 spin_unlock(&idxd->dev_lock); 577 return 0; 578 } 579 580 void idxd_device_reset(struct idxd_device *idxd) 581 { 582 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 583 spin_lock(&idxd->dev_lock); 584 idxd_device_clear_state(idxd); 585 idxd->state = IDXD_DEV_DISABLED; 586 idxd_unmask_error_interrupts(idxd); 587 idxd_msix_perm_setup(idxd); 588 spin_unlock(&idxd->dev_lock); 589 } 590 591 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid) 592 { 593 struct device *dev = &idxd->pdev->dev; 594 u32 operand; 595 596 operand = pasid; 597 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand); 598 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL); 599 dev_dbg(dev, "pasid %d drained\n", pasid); 600 } 601 602 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 603 enum idxd_interrupt_type irq_type) 604 { 605 struct device *dev = &idxd->pdev->dev; 606 u32 operand, status; 607 608 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))) 609 return -EOPNOTSUPP; 610 611 dev_dbg(dev, "get int handle, idx %d\n", idx); 612 613 operand = idx & GENMASK(15, 0); 614 if (irq_type == IDXD_IRQ_IMS) 615 operand |= CMD_INT_HANDLE_IMS; 616 617 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand); 618 619 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status); 620 621 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 622 dev_dbg(dev, "request int handle failed: %#x\n", status); 623 return -ENXIO; 624 } 625 626 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0); 627 628 dev_dbg(dev, "int handle acquired: %u\n", *handle); 629 return 0; 630 } 631 632 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 633 enum idxd_interrupt_type irq_type) 634 { 635 struct device *dev = &idxd->pdev->dev; 636 u32 operand, status; 637 union idxd_command_reg cmd; 638 639 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))) 640 return -EOPNOTSUPP; 641 642 dev_dbg(dev, "release int handle, handle %d\n", handle); 643 644 memset(&cmd, 0, sizeof(cmd)); 645 operand = handle & GENMASK(15, 0); 646 647 if (irq_type == IDXD_IRQ_IMS) 648 operand |= CMD_INT_HANDLE_IMS; 649 650 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE; 651 cmd.operand = operand; 652 653 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand); 654 655 spin_lock(&idxd->cmd_lock); 656 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 657 658 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE) 659 cpu_relax(); 660 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 661 spin_unlock(&idxd->cmd_lock); 662 663 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 664 dev_dbg(dev, "release int handle failed: %#x\n", status); 665 return -ENXIO; 666 } 667 668 dev_dbg(dev, "int handle released.\n"); 669 return 0; 670 } 671 672 /* Device configuration bits */ 673 static void idxd_engines_clear_state(struct idxd_device *idxd) 674 { 675 struct idxd_engine *engine; 676 int i; 677 678 lockdep_assert_held(&idxd->dev_lock); 679 for (i = 0; i < idxd->max_engines; i++) { 680 engine = idxd->engines[i]; 681 engine->group = NULL; 682 } 683 } 684 685 static void idxd_groups_clear_state(struct idxd_device *idxd) 686 { 687 struct idxd_group *group; 688 int i; 689 690 lockdep_assert_held(&idxd->dev_lock); 691 for (i = 0; i < idxd->max_groups; i++) { 692 group = idxd->groups[i]; 693 memset(&group->grpcfg, 0, sizeof(group->grpcfg)); 694 group->num_engines = 0; 695 group->num_wqs = 0; 696 group->use_token_limit = false; 697 group->tokens_allowed = 0; 698 group->tokens_reserved = 0; 699 group->tc_a = -1; 700 group->tc_b = -1; 701 } 702 } 703 704 static void idxd_device_wqs_clear_state(struct idxd_device *idxd) 705 { 706 int i; 707 708 lockdep_assert_held(&idxd->dev_lock); 709 for (i = 0; i < idxd->max_wqs; i++) { 710 struct idxd_wq *wq = idxd->wqs[i]; 711 712 if (wq->state == IDXD_WQ_ENABLED) { 713 idxd_wq_disable_cleanup(wq); 714 wq->state = IDXD_WQ_DISABLED; 715 } 716 } 717 } 718 719 void idxd_device_clear_state(struct idxd_device *idxd) 720 { 721 idxd_groups_clear_state(idxd); 722 idxd_engines_clear_state(idxd); 723 idxd_device_wqs_clear_state(idxd); 724 } 725 726 void idxd_msix_perm_setup(struct idxd_device *idxd) 727 { 728 union msix_perm mperm; 729 int i, msixcnt; 730 731 msixcnt = pci_msix_vec_count(idxd->pdev); 732 if (msixcnt < 0) 733 return; 734 735 mperm.bits = 0; 736 mperm.pasid = idxd->pasid; 737 mperm.pasid_en = device_pasid_enabled(idxd); 738 for (i = 1; i < msixcnt; i++) 739 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8); 740 } 741 742 void idxd_msix_perm_clear(struct idxd_device *idxd) 743 { 744 union msix_perm mperm; 745 int i, msixcnt; 746 747 msixcnt = pci_msix_vec_count(idxd->pdev); 748 if (msixcnt < 0) 749 return; 750 751 mperm.bits = 0; 752 for (i = 1; i < msixcnt; i++) 753 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8); 754 } 755 756 static void idxd_group_config_write(struct idxd_group *group) 757 { 758 struct idxd_device *idxd = group->idxd; 759 struct device *dev = &idxd->pdev->dev; 760 int i; 761 u32 grpcfg_offset; 762 763 dev_dbg(dev, "Writing group %d cfg registers\n", group->id); 764 765 /* setup GRPWQCFG */ 766 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 767 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 768 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset); 769 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 770 group->id, i, grpcfg_offset, 771 ioread64(idxd->reg_base + grpcfg_offset)); 772 } 773 774 /* setup GRPENGCFG */ 775 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 776 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 777 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 778 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); 779 780 /* setup GRPFLAGS */ 781 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 782 iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); 783 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 784 group->id, grpcfg_offset, 785 ioread32(idxd->reg_base + grpcfg_offset)); 786 } 787 788 static int idxd_groups_config_write(struct idxd_device *idxd) 789 790 { 791 union gencfg_reg reg; 792 int i; 793 struct device *dev = &idxd->pdev->dev; 794 795 /* Setup bandwidth token limit */ 796 if (idxd->hw.gen_cap.config_en && idxd->token_limit) { 797 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 798 reg.token_limit = idxd->token_limit; 799 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 800 } 801 802 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET, 803 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET)); 804 805 for (i = 0; i < idxd->max_groups; i++) { 806 struct idxd_group *group = idxd->groups[i]; 807 808 idxd_group_config_write(group); 809 } 810 811 return 0; 812 } 813 814 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd) 815 { 816 struct pci_dev *pdev = idxd->pdev; 817 818 if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV)) 819 return true; 820 return false; 821 } 822 823 static int idxd_wq_config_write(struct idxd_wq *wq) 824 { 825 struct idxd_device *idxd = wq->idxd; 826 struct device *dev = &idxd->pdev->dev; 827 u32 wq_offset; 828 int i; 829 830 if (!wq->group) 831 return 0; 832 833 /* 834 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after 835 * wq reset. This will copy back the sticky values that are present on some devices. 836 */ 837 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 838 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 839 wq->wqcfg->bits[i] = ioread32(idxd->reg_base + wq_offset); 840 } 841 842 /* byte 0-3 */ 843 wq->wqcfg->wq_size = wq->size; 844 845 if (wq->size == 0) { 846 idxd->cmd_status = IDXD_SCMD_WQ_NO_SIZE; 847 dev_warn(dev, "Incorrect work queue size: 0\n"); 848 return -EINVAL; 849 } 850 851 /* bytes 4-7 */ 852 wq->wqcfg->wq_thresh = wq->threshold; 853 854 /* byte 8-11 */ 855 if (wq_dedicated(wq)) 856 wq->wqcfg->mode = 1; 857 858 if (device_pasid_enabled(idxd)) { 859 wq->wqcfg->pasid_en = 1; 860 if (wq->type == IDXD_WQT_KERNEL && wq_dedicated(wq)) 861 wq->wqcfg->pasid = idxd->pasid; 862 } 863 864 /* 865 * Here the priv bit is set depending on the WQ type. priv = 1 if the 866 * WQ type is kernel to indicate privileged access. This setting only 867 * matters for dedicated WQ. According to the DSA spec: 868 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the 869 * Privileged Mode Enable field of the PCI Express PASID capability 870 * is 0, this field must be 0. 871 * 872 * In the case of a dedicated kernel WQ that is not able to support 873 * the PASID cap, then the configuration will be rejected. 874 */ 875 wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL); 876 if (wq_dedicated(wq) && wq->wqcfg->pasid_en && 877 !idxd_device_pasid_priv_enabled(idxd) && 878 wq->type == IDXD_WQT_KERNEL) { 879 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV; 880 return -EOPNOTSUPP; 881 } 882 883 wq->wqcfg->priority = wq->priority; 884 885 if (idxd->hw.gen_cap.block_on_fault && 886 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags)) 887 wq->wqcfg->bof = 1; 888 889 if (idxd->hw.wq_cap.wq_ats_support) 890 wq->wqcfg->wq_ats_disable = wq->ats_dis; 891 892 /* bytes 12-15 */ 893 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 894 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size); 895 896 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 897 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 898 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 899 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); 900 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 901 wq->id, i, wq_offset, 902 ioread32(idxd->reg_base + wq_offset)); 903 } 904 905 return 0; 906 } 907 908 static int idxd_wqs_config_write(struct idxd_device *idxd) 909 { 910 int i, rc; 911 912 for (i = 0; i < idxd->max_wqs; i++) { 913 struct idxd_wq *wq = idxd->wqs[i]; 914 915 rc = idxd_wq_config_write(wq); 916 if (rc < 0) 917 return rc; 918 } 919 920 return 0; 921 } 922 923 static void idxd_group_flags_setup(struct idxd_device *idxd) 924 { 925 int i; 926 927 /* TC-A 0 and TC-B 1 should be defaults */ 928 for (i = 0; i < idxd->max_groups; i++) { 929 struct idxd_group *group = idxd->groups[i]; 930 931 if (group->tc_a == -1) 932 group->tc_a = group->grpcfg.flags.tc_a = 0; 933 else 934 group->grpcfg.flags.tc_a = group->tc_a; 935 if (group->tc_b == -1) 936 group->tc_b = group->grpcfg.flags.tc_b = 1; 937 else 938 group->grpcfg.flags.tc_b = group->tc_b; 939 group->grpcfg.flags.use_token_limit = group->use_token_limit; 940 group->grpcfg.flags.tokens_reserved = group->tokens_reserved; 941 if (group->tokens_allowed) 942 group->grpcfg.flags.tokens_allowed = 943 group->tokens_allowed; 944 else 945 group->grpcfg.flags.tokens_allowed = idxd->max_tokens; 946 } 947 } 948 949 static int idxd_engines_setup(struct idxd_device *idxd) 950 { 951 int i, engines = 0; 952 struct idxd_engine *eng; 953 struct idxd_group *group; 954 955 for (i = 0; i < idxd->max_groups; i++) { 956 group = idxd->groups[i]; 957 group->grpcfg.engines = 0; 958 } 959 960 for (i = 0; i < idxd->max_engines; i++) { 961 eng = idxd->engines[i]; 962 group = eng->group; 963 964 if (!group) 965 continue; 966 967 group->grpcfg.engines |= BIT(eng->id); 968 engines++; 969 } 970 971 if (!engines) 972 return -EINVAL; 973 974 return 0; 975 } 976 977 static int idxd_wqs_setup(struct idxd_device *idxd) 978 { 979 struct idxd_wq *wq; 980 struct idxd_group *group; 981 int i, j, configured = 0; 982 struct device *dev = &idxd->pdev->dev; 983 984 for (i = 0; i < idxd->max_groups; i++) { 985 group = idxd->groups[i]; 986 for (j = 0; j < 4; j++) 987 group->grpcfg.wqs[j] = 0; 988 } 989 990 for (i = 0; i < idxd->max_wqs; i++) { 991 wq = idxd->wqs[i]; 992 group = wq->group; 993 994 if (!wq->group) 995 continue; 996 if (!wq->size) 997 continue; 998 999 if (wq_shared(wq) && !device_swq_supported(idxd)) { 1000 idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT; 1001 dev_warn(dev, "No shared wq support but configured.\n"); 1002 return -EINVAL; 1003 } 1004 1005 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 1006 configured++; 1007 } 1008 1009 if (configured == 0) { 1010 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED; 1011 return -EINVAL; 1012 } 1013 1014 return 0; 1015 } 1016 1017 int idxd_device_config(struct idxd_device *idxd) 1018 { 1019 int rc; 1020 1021 lockdep_assert_held(&idxd->dev_lock); 1022 rc = idxd_wqs_setup(idxd); 1023 if (rc < 0) 1024 return rc; 1025 1026 rc = idxd_engines_setup(idxd); 1027 if (rc < 0) 1028 return rc; 1029 1030 idxd_group_flags_setup(idxd); 1031 1032 rc = idxd_wqs_config_write(idxd); 1033 if (rc < 0) 1034 return rc; 1035 1036 rc = idxd_groups_config_write(idxd); 1037 if (rc < 0) 1038 return rc; 1039 1040 return 0; 1041 } 1042 1043 static int idxd_wq_load_config(struct idxd_wq *wq) 1044 { 1045 struct idxd_device *idxd = wq->idxd; 1046 struct device *dev = &idxd->pdev->dev; 1047 int wqcfg_offset; 1048 int i; 1049 1050 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0); 1051 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size); 1052 1053 wq->size = wq->wqcfg->wq_size; 1054 wq->threshold = wq->wqcfg->wq_thresh; 1055 1056 /* The driver does not support shared WQ mode in read-only config yet */ 1057 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en) 1058 return -EOPNOTSUPP; 1059 1060 set_bit(WQ_FLAG_DEDICATED, &wq->flags); 1061 1062 wq->priority = wq->wqcfg->priority; 1063 1064 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1065 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i); 1066 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]); 1067 } 1068 1069 return 0; 1070 } 1071 1072 static void idxd_group_load_config(struct idxd_group *group) 1073 { 1074 struct idxd_device *idxd = group->idxd; 1075 struct device *dev = &idxd->pdev->dev; 1076 int i, j, grpcfg_offset; 1077 1078 /* 1079 * Load WQS bit fields 1080 * Iterate through all 256 bits 64 bits at a time 1081 */ 1082 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 1083 struct idxd_wq *wq; 1084 1085 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 1086 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset); 1087 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 1088 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]); 1089 1090 if (i * 64 >= idxd->max_wqs) 1091 break; 1092 1093 /* Iterate through all 64 bits and check for wq set */ 1094 for (j = 0; j < 64; j++) { 1095 int id = i * 64 + j; 1096 1097 /* No need to check beyond max wqs */ 1098 if (id >= idxd->max_wqs) 1099 break; 1100 1101 /* Set group assignment for wq if wq bit is set */ 1102 if (group->grpcfg.wqs[i] & BIT(j)) { 1103 wq = idxd->wqs[id]; 1104 wq->group = group; 1105 } 1106 } 1107 } 1108 1109 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 1110 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset); 1111 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 1112 grpcfg_offset, group->grpcfg.engines); 1113 1114 /* Iterate through all 64 bits to check engines set */ 1115 for (i = 0; i < 64; i++) { 1116 if (i >= idxd->max_engines) 1117 break; 1118 1119 if (group->grpcfg.engines & BIT(i)) { 1120 struct idxd_engine *engine = idxd->engines[i]; 1121 1122 engine->group = group; 1123 } 1124 } 1125 1126 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 1127 group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset); 1128 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 1129 group->id, grpcfg_offset, group->grpcfg.flags.bits); 1130 } 1131 1132 int idxd_device_load_config(struct idxd_device *idxd) 1133 { 1134 union gencfg_reg reg; 1135 int i, rc; 1136 1137 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 1138 idxd->token_limit = reg.token_limit; 1139 1140 for (i = 0; i < idxd->max_groups; i++) { 1141 struct idxd_group *group = idxd->groups[i]; 1142 1143 idxd_group_load_config(group); 1144 } 1145 1146 for (i = 0; i < idxd->max_wqs; i++) { 1147 struct idxd_wq *wq = idxd->wqs[i]; 1148 1149 rc = idxd_wq_load_config(wq); 1150 if (rc < 0) 1151 return rc; 1152 } 1153 1154 return 0; 1155 } 1156 1157 int __drv_enable_wq(struct idxd_wq *wq) 1158 { 1159 struct idxd_device *idxd = wq->idxd; 1160 struct device *dev = &idxd->pdev->dev; 1161 int rc = -ENXIO; 1162 1163 lockdep_assert_held(&wq->wq_lock); 1164 1165 if (idxd->state != IDXD_DEV_ENABLED) { 1166 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED; 1167 goto err; 1168 } 1169 1170 if (wq->state != IDXD_WQ_DISABLED) { 1171 dev_dbg(dev, "wq %d already enabled.\n", wq->id); 1172 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED; 1173 rc = -EBUSY; 1174 goto err; 1175 } 1176 1177 if (!wq->group) { 1178 dev_dbg(dev, "wq %d not attached to group.\n", wq->id); 1179 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP; 1180 goto err; 1181 } 1182 1183 if (strlen(wq->name) == 0) { 1184 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME; 1185 dev_dbg(dev, "wq %d name not set.\n", wq->id); 1186 goto err; 1187 } 1188 1189 /* Shared WQ checks */ 1190 if (wq_shared(wq)) { 1191 if (!device_swq_supported(idxd)) { 1192 idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM; 1193 dev_dbg(dev, "PASID not enabled and shared wq.\n"); 1194 goto err; 1195 } 1196 /* 1197 * Shared wq with the threshold set to 0 means the user 1198 * did not set the threshold or transitioned from a 1199 * dedicated wq but did not set threshold. A value 1200 * of 0 would effectively disable the shared wq. The 1201 * driver does not allow a value of 0 to be set for 1202 * threshold via sysfs. 1203 */ 1204 if (wq->threshold == 0) { 1205 idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH; 1206 dev_dbg(dev, "Shared wq and threshold 0.\n"); 1207 goto err; 1208 } 1209 } 1210 1211 rc = 0; 1212 spin_lock(&idxd->dev_lock); 1213 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1214 rc = idxd_device_config(idxd); 1215 spin_unlock(&idxd->dev_lock); 1216 if (rc < 0) { 1217 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc); 1218 goto err; 1219 } 1220 1221 /* 1222 * Device has 1 misc interrupt and N interrupts for descriptor completion. To 1223 * assign WQ to interrupt, we will take the N+1 interrupt since vector 0 is 1224 * for the misc interrupt. 1225 */ 1226 wq->ie = &idxd->irq_entries[wq->id + 1]; 1227 1228 rc = idxd_wq_enable(wq); 1229 if (rc < 0) { 1230 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc); 1231 goto err; 1232 } 1233 1234 rc = idxd_wq_map_portal(wq); 1235 if (rc < 0) { 1236 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR; 1237 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc); 1238 goto err_map_portal; 1239 } 1240 1241 wq->client_count = 0; 1242 return 0; 1243 1244 err_map_portal: 1245 rc = idxd_wq_disable(wq, false); 1246 if (rc < 0) 1247 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq))); 1248 err: 1249 return rc; 1250 } 1251 1252 int drv_enable_wq(struct idxd_wq *wq) 1253 { 1254 int rc; 1255 1256 mutex_lock(&wq->wq_lock); 1257 rc = __drv_enable_wq(wq); 1258 mutex_unlock(&wq->wq_lock); 1259 return rc; 1260 } 1261 1262 void __drv_disable_wq(struct idxd_wq *wq) 1263 { 1264 struct idxd_device *idxd = wq->idxd; 1265 struct device *dev = &idxd->pdev->dev; 1266 1267 lockdep_assert_held(&wq->wq_lock); 1268 1269 if (idxd_wq_refcount(wq)) 1270 dev_warn(dev, "Clients has claim on wq %d: %d\n", 1271 wq->id, idxd_wq_refcount(wq)); 1272 1273 idxd_wq_unmap_portal(wq); 1274 1275 idxd_wq_drain(wq); 1276 idxd_wq_reset(wq); 1277 1278 wq->ie = NULL; 1279 wq->client_count = 0; 1280 } 1281 1282 void drv_disable_wq(struct idxd_wq *wq) 1283 { 1284 mutex_lock(&wq->wq_lock); 1285 __drv_disable_wq(wq); 1286 mutex_unlock(&wq->wq_lock); 1287 } 1288 1289 int idxd_device_drv_probe(struct idxd_dev *idxd_dev) 1290 { 1291 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1292 int rc = 0; 1293 1294 /* 1295 * Device should be in disabled state for the idxd_drv to load. If it's in 1296 * enabled state, then the device was altered outside of driver's control. 1297 * If the state is in halted state, then we don't want to proceed. 1298 */ 1299 if (idxd->state != IDXD_DEV_DISABLED) { 1300 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED; 1301 return -ENXIO; 1302 } 1303 1304 /* Device configuration */ 1305 spin_lock(&idxd->dev_lock); 1306 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1307 rc = idxd_device_config(idxd); 1308 spin_unlock(&idxd->dev_lock); 1309 if (rc < 0) 1310 return -ENXIO; 1311 1312 /* Start device */ 1313 rc = idxd_device_enable(idxd); 1314 if (rc < 0) 1315 return rc; 1316 1317 /* Setup DMA device without channels */ 1318 rc = idxd_register_dma_device(idxd); 1319 if (rc < 0) { 1320 idxd_device_disable(idxd); 1321 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR; 1322 return rc; 1323 } 1324 1325 idxd->cmd_status = 0; 1326 return 0; 1327 } 1328 1329 void idxd_device_drv_remove(struct idxd_dev *idxd_dev) 1330 { 1331 struct device *dev = &idxd_dev->conf_dev; 1332 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1333 int i; 1334 1335 for (i = 0; i < idxd->max_wqs; i++) { 1336 struct idxd_wq *wq = idxd->wqs[i]; 1337 struct device *wq_dev = wq_confdev(wq); 1338 1339 if (wq->state == IDXD_WQ_DISABLED) 1340 continue; 1341 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev)); 1342 device_release_driver(wq_dev); 1343 } 1344 1345 idxd_unregister_dma_device(idxd); 1346 idxd_device_disable(idxd); 1347 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1348 idxd_device_reset(idxd); 1349 } 1350 1351 static enum idxd_dev_type dev_types[] = { 1352 IDXD_DEV_DSA, 1353 IDXD_DEV_IAX, 1354 IDXD_DEV_NONE, 1355 }; 1356 1357 struct idxd_device_driver idxd_drv = { 1358 .type = dev_types, 1359 .probe = idxd_device_drv_probe, 1360 .remove = idxd_device_drv_remove, 1361 .name = "idxd", 1362 }; 1363 EXPORT_SYMBOL_GPL(idxd_drv); 1364