1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <linux/irq.h> 10 #include <linux/msi.h> 11 #include <uapi/linux/idxd.h> 12 #include "../dmaengine.h" 13 #include "idxd.h" 14 #include "registers.h" 15 16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 17 u32 *status); 18 19 /* Interrupt control bits */ 20 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id) 21 { 22 struct irq_data *data = irq_get_irq_data(idxd->msix_entries[vec_id].vector); 23 24 pci_msi_mask_irq(data); 25 } 26 27 void idxd_mask_msix_vectors(struct idxd_device *idxd) 28 { 29 struct pci_dev *pdev = idxd->pdev; 30 int msixcnt = pci_msix_vec_count(pdev); 31 int i; 32 33 for (i = 0; i < msixcnt; i++) 34 idxd_mask_msix_vector(idxd, i); 35 } 36 37 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id) 38 { 39 struct irq_data *data = irq_get_irq_data(idxd->msix_entries[vec_id].vector); 40 41 pci_msi_unmask_irq(data); 42 } 43 44 void idxd_unmask_error_interrupts(struct idxd_device *idxd) 45 { 46 union genctrl_reg genctrl; 47 48 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 49 genctrl.softerr_int_en = 1; 50 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 51 } 52 53 void idxd_mask_error_interrupts(struct idxd_device *idxd) 54 { 55 union genctrl_reg genctrl; 56 57 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 58 genctrl.softerr_int_en = 0; 59 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 60 } 61 62 static void free_hw_descs(struct idxd_wq *wq) 63 { 64 int i; 65 66 for (i = 0; i < wq->num_descs; i++) 67 kfree(wq->hw_descs[i]); 68 69 kfree(wq->hw_descs); 70 } 71 72 static int alloc_hw_descs(struct idxd_wq *wq, int num) 73 { 74 struct device *dev = &wq->idxd->pdev->dev; 75 int i; 76 int node = dev_to_node(dev); 77 78 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), 79 GFP_KERNEL, node); 80 if (!wq->hw_descs) 81 return -ENOMEM; 82 83 for (i = 0; i < num; i++) { 84 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), 85 GFP_KERNEL, node); 86 if (!wq->hw_descs[i]) { 87 free_hw_descs(wq); 88 return -ENOMEM; 89 } 90 } 91 92 return 0; 93 } 94 95 static void free_descs(struct idxd_wq *wq) 96 { 97 int i; 98 99 for (i = 0; i < wq->num_descs; i++) 100 kfree(wq->descs[i]); 101 102 kfree(wq->descs); 103 } 104 105 static int alloc_descs(struct idxd_wq *wq, int num) 106 { 107 struct device *dev = &wq->idxd->pdev->dev; 108 int i; 109 int node = dev_to_node(dev); 110 111 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), 112 GFP_KERNEL, node); 113 if (!wq->descs) 114 return -ENOMEM; 115 116 for (i = 0; i < num; i++) { 117 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), 118 GFP_KERNEL, node); 119 if (!wq->descs[i]) { 120 free_descs(wq); 121 return -ENOMEM; 122 } 123 } 124 125 return 0; 126 } 127 128 /* WQ control bits */ 129 int idxd_wq_alloc_resources(struct idxd_wq *wq) 130 { 131 struct idxd_device *idxd = wq->idxd; 132 struct device *dev = &idxd->pdev->dev; 133 int rc, num_descs, i; 134 135 if (wq->type != IDXD_WQT_KERNEL) 136 return 0; 137 138 wq->num_descs = wq->size; 139 num_descs = wq->size; 140 141 rc = alloc_hw_descs(wq, num_descs); 142 if (rc < 0) 143 return rc; 144 145 wq->compls_size = num_descs * sizeof(struct dsa_completion_record); 146 wq->compls = dma_alloc_coherent(dev, wq->compls_size, 147 &wq->compls_addr, GFP_KERNEL); 148 if (!wq->compls) { 149 rc = -ENOMEM; 150 goto fail_alloc_compls; 151 } 152 153 rc = alloc_descs(wq, num_descs); 154 if (rc < 0) 155 goto fail_alloc_descs; 156 157 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL, 158 dev_to_node(dev)); 159 if (rc < 0) 160 goto fail_sbitmap_init; 161 162 for (i = 0; i < num_descs; i++) { 163 struct idxd_desc *desc = wq->descs[i]; 164 165 desc->hw = wq->hw_descs[i]; 166 desc->completion = &wq->compls[i]; 167 desc->compl_dma = wq->compls_addr + 168 sizeof(struct dsa_completion_record) * i; 169 desc->id = i; 170 desc->wq = wq; 171 desc->cpu = -1; 172 dma_async_tx_descriptor_init(&desc->txd, &wq->dma_chan); 173 desc->txd.tx_submit = idxd_dma_tx_submit; 174 } 175 176 return 0; 177 178 fail_sbitmap_init: 179 free_descs(wq); 180 fail_alloc_descs: 181 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 182 fail_alloc_compls: 183 free_hw_descs(wq); 184 return rc; 185 } 186 187 void idxd_wq_free_resources(struct idxd_wq *wq) 188 { 189 struct device *dev = &wq->idxd->pdev->dev; 190 191 if (wq->type != IDXD_WQT_KERNEL) 192 return; 193 194 free_hw_descs(wq); 195 free_descs(wq); 196 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 197 sbitmap_queue_free(&wq->sbq); 198 } 199 200 int idxd_wq_enable(struct idxd_wq *wq) 201 { 202 struct idxd_device *idxd = wq->idxd; 203 struct device *dev = &idxd->pdev->dev; 204 u32 status; 205 206 if (wq->state == IDXD_WQ_ENABLED) { 207 dev_dbg(dev, "WQ %d already enabled\n", wq->id); 208 return -ENXIO; 209 } 210 211 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status); 212 213 if (status != IDXD_CMDSTS_SUCCESS && 214 status != IDXD_CMDSTS_ERR_WQ_ENABLED) { 215 dev_dbg(dev, "WQ enable failed: %#x\n", status); 216 return -ENXIO; 217 } 218 219 wq->state = IDXD_WQ_ENABLED; 220 dev_dbg(dev, "WQ %d enabled\n", wq->id); 221 return 0; 222 } 223 224 int idxd_wq_disable(struct idxd_wq *wq) 225 { 226 struct idxd_device *idxd = wq->idxd; 227 struct device *dev = &idxd->pdev->dev; 228 u32 status, operand; 229 230 dev_dbg(dev, "Disabling WQ %d\n", wq->id); 231 232 if (wq->state != IDXD_WQ_ENABLED) { 233 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 234 return 0; 235 } 236 237 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 238 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status); 239 240 if (status != IDXD_CMDSTS_SUCCESS) { 241 dev_dbg(dev, "WQ disable failed: %#x\n", status); 242 return -ENXIO; 243 } 244 245 wq->state = IDXD_WQ_DISABLED; 246 dev_dbg(dev, "WQ %d disabled\n", wq->id); 247 return 0; 248 } 249 250 void idxd_wq_drain(struct idxd_wq *wq) 251 { 252 struct idxd_device *idxd = wq->idxd; 253 struct device *dev = &idxd->pdev->dev; 254 u32 operand; 255 256 if (wq->state != IDXD_WQ_ENABLED) { 257 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 258 return; 259 } 260 261 dev_dbg(dev, "Draining WQ %d\n", wq->id); 262 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 263 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL); 264 } 265 266 int idxd_wq_map_portal(struct idxd_wq *wq) 267 { 268 struct idxd_device *idxd = wq->idxd; 269 struct pci_dev *pdev = idxd->pdev; 270 struct device *dev = &pdev->dev; 271 resource_size_t start; 272 273 start = pci_resource_start(pdev, IDXD_WQ_BAR); 274 start = start + wq->id * IDXD_PORTAL_SIZE; 275 276 wq->dportal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 277 if (!wq->dportal) 278 return -ENOMEM; 279 dev_dbg(dev, "wq %d portal mapped at %p\n", wq->id, wq->dportal); 280 281 return 0; 282 } 283 284 void idxd_wq_unmap_portal(struct idxd_wq *wq) 285 { 286 struct device *dev = &wq->idxd->pdev->dev; 287 288 devm_iounmap(dev, wq->dportal); 289 } 290 291 /* Device control bits */ 292 static inline bool idxd_is_enabled(struct idxd_device *idxd) 293 { 294 union gensts_reg gensts; 295 296 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 297 298 if (gensts.state == IDXD_DEVICE_STATE_ENABLED) 299 return true; 300 return false; 301 } 302 303 /* 304 * This is function is only used for reset during probe and will 305 * poll for completion. Once the device is setup with interrupts, 306 * all commands will be done via interrupt completion. 307 */ 308 void idxd_device_init_reset(struct idxd_device *idxd) 309 { 310 struct device *dev = &idxd->pdev->dev; 311 union idxd_command_reg cmd; 312 unsigned long flags; 313 314 memset(&cmd, 0, sizeof(cmd)); 315 cmd.cmd = IDXD_CMD_RESET_DEVICE; 316 dev_dbg(dev, "%s: sending reset for init.\n", __func__); 317 spin_lock_irqsave(&idxd->dev_lock, flags); 318 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 319 320 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & 321 IDXD_CMDSTS_ACTIVE) 322 cpu_relax(); 323 spin_unlock_irqrestore(&idxd->dev_lock, flags); 324 } 325 326 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 327 u32 *status) 328 { 329 union idxd_command_reg cmd; 330 DECLARE_COMPLETION_ONSTACK(done); 331 unsigned long flags; 332 333 memset(&cmd, 0, sizeof(cmd)); 334 cmd.cmd = cmd_code; 335 cmd.operand = operand; 336 cmd.int_req = 1; 337 338 spin_lock_irqsave(&idxd->dev_lock, flags); 339 wait_event_lock_irq(idxd->cmd_waitq, 340 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags), 341 idxd->dev_lock); 342 343 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n", 344 __func__, cmd_code, operand); 345 346 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 347 idxd->cmd_done = &done; 348 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 349 350 /* 351 * After command submitted, release lock and go to sleep until 352 * the command completes via interrupt. 353 */ 354 spin_unlock_irqrestore(&idxd->dev_lock, flags); 355 wait_for_completion(&done); 356 spin_lock_irqsave(&idxd->dev_lock, flags); 357 if (status) 358 *status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 359 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 360 /* Wake up other pending commands */ 361 wake_up(&idxd->cmd_waitq); 362 spin_unlock_irqrestore(&idxd->dev_lock, flags); 363 } 364 365 int idxd_device_enable(struct idxd_device *idxd) 366 { 367 struct device *dev = &idxd->pdev->dev; 368 u32 status; 369 370 if (idxd_is_enabled(idxd)) { 371 dev_dbg(dev, "Device already enabled\n"); 372 return -ENXIO; 373 } 374 375 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status); 376 377 /* If the command is successful or if the device was enabled */ 378 if (status != IDXD_CMDSTS_SUCCESS && 379 status != IDXD_CMDSTS_ERR_DEV_ENABLED) { 380 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 381 return -ENXIO; 382 } 383 384 idxd->state = IDXD_DEV_ENABLED; 385 return 0; 386 } 387 388 int idxd_device_disable(struct idxd_device *idxd) 389 { 390 struct device *dev = &idxd->pdev->dev; 391 u32 status; 392 393 if (!idxd_is_enabled(idxd)) { 394 dev_dbg(dev, "Device is not enabled\n"); 395 return 0; 396 } 397 398 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status); 399 400 /* If the command is successful or if the device was disabled */ 401 if (status != IDXD_CMDSTS_SUCCESS && 402 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) { 403 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 404 return -ENXIO; 405 } 406 407 idxd->state = IDXD_DEV_CONF_READY; 408 return 0; 409 } 410 411 void idxd_device_reset(struct idxd_device *idxd) 412 { 413 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 414 } 415 416 /* Device configuration bits */ 417 static void idxd_group_config_write(struct idxd_group *group) 418 { 419 struct idxd_device *idxd = group->idxd; 420 struct device *dev = &idxd->pdev->dev; 421 int i; 422 u32 grpcfg_offset; 423 424 dev_dbg(dev, "Writing group %d cfg registers\n", group->id); 425 426 /* setup GRPWQCFG */ 427 for (i = 0; i < 4; i++) { 428 grpcfg_offset = idxd->grpcfg_offset + 429 group->id * 64 + i * sizeof(u64); 430 iowrite64(group->grpcfg.wqs[i], 431 idxd->reg_base + grpcfg_offset); 432 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 433 group->id, i, grpcfg_offset, 434 ioread64(idxd->reg_base + grpcfg_offset)); 435 } 436 437 /* setup GRPENGCFG */ 438 grpcfg_offset = idxd->grpcfg_offset + group->id * 64 + 32; 439 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 440 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 441 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); 442 443 /* setup GRPFLAGS */ 444 grpcfg_offset = idxd->grpcfg_offset + group->id * 64 + 40; 445 iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); 446 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 447 group->id, grpcfg_offset, 448 ioread32(idxd->reg_base + grpcfg_offset)); 449 } 450 451 static int idxd_groups_config_write(struct idxd_device *idxd) 452 453 { 454 union gencfg_reg reg; 455 int i; 456 struct device *dev = &idxd->pdev->dev; 457 458 /* Setup bandwidth token limit */ 459 if (idxd->token_limit) { 460 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 461 reg.token_limit = idxd->token_limit; 462 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 463 } 464 465 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET, 466 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET)); 467 468 for (i = 0; i < idxd->max_groups; i++) { 469 struct idxd_group *group = &idxd->groups[i]; 470 471 idxd_group_config_write(group); 472 } 473 474 return 0; 475 } 476 477 static int idxd_wq_config_write(struct idxd_wq *wq) 478 { 479 struct idxd_device *idxd = wq->idxd; 480 struct device *dev = &idxd->pdev->dev; 481 u32 wq_offset; 482 int i; 483 484 if (!wq->group) 485 return 0; 486 487 memset(&wq->wqcfg, 0, sizeof(union wqcfg)); 488 489 /* byte 0-3 */ 490 wq->wqcfg.wq_size = wq->size; 491 492 if (wq->size == 0) { 493 dev_warn(dev, "Incorrect work queue size: 0\n"); 494 return -EINVAL; 495 } 496 497 /* bytes 4-7 */ 498 wq->wqcfg.wq_thresh = wq->threshold; 499 500 /* byte 8-11 */ 501 wq->wqcfg.priv = !!(wq->type == IDXD_WQT_KERNEL); 502 wq->wqcfg.mode = 1; 503 504 wq->wqcfg.priority = wq->priority; 505 506 /* bytes 12-15 */ 507 wq->wqcfg.max_xfer_shift = idxd->hw.gen_cap.max_xfer_shift; 508 wq->wqcfg.max_batch_shift = idxd->hw.gen_cap.max_batch_shift; 509 510 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 511 for (i = 0; i < 8; i++) { 512 wq_offset = idxd->wqcfg_offset + wq->id * 32 + i * sizeof(u32); 513 iowrite32(wq->wqcfg.bits[i], idxd->reg_base + wq_offset); 514 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 515 wq->id, i, wq_offset, 516 ioread32(idxd->reg_base + wq_offset)); 517 } 518 519 return 0; 520 } 521 522 static int idxd_wqs_config_write(struct idxd_device *idxd) 523 { 524 int i, rc; 525 526 for (i = 0; i < idxd->max_wqs; i++) { 527 struct idxd_wq *wq = &idxd->wqs[i]; 528 529 rc = idxd_wq_config_write(wq); 530 if (rc < 0) 531 return rc; 532 } 533 534 return 0; 535 } 536 537 static void idxd_group_flags_setup(struct idxd_device *idxd) 538 { 539 int i; 540 541 /* TC-A 0 and TC-B 1 should be defaults */ 542 for (i = 0; i < idxd->max_groups; i++) { 543 struct idxd_group *group = &idxd->groups[i]; 544 545 if (group->tc_a == -1) 546 group->tc_a = group->grpcfg.flags.tc_a = 0; 547 else 548 group->grpcfg.flags.tc_a = group->tc_a; 549 if (group->tc_b == -1) 550 group->tc_b = group->grpcfg.flags.tc_b = 1; 551 else 552 group->grpcfg.flags.tc_b = group->tc_b; 553 group->grpcfg.flags.use_token_limit = group->use_token_limit; 554 group->grpcfg.flags.tokens_reserved = group->tokens_reserved; 555 if (group->tokens_allowed) 556 group->grpcfg.flags.tokens_allowed = 557 group->tokens_allowed; 558 else 559 group->grpcfg.flags.tokens_allowed = idxd->max_tokens; 560 } 561 } 562 563 static int idxd_engines_setup(struct idxd_device *idxd) 564 { 565 int i, engines = 0; 566 struct idxd_engine *eng; 567 struct idxd_group *group; 568 569 for (i = 0; i < idxd->max_groups; i++) { 570 group = &idxd->groups[i]; 571 group->grpcfg.engines = 0; 572 } 573 574 for (i = 0; i < idxd->max_engines; i++) { 575 eng = &idxd->engines[i]; 576 group = eng->group; 577 578 if (!group) 579 continue; 580 581 group->grpcfg.engines |= BIT(eng->id); 582 engines++; 583 } 584 585 if (!engines) 586 return -EINVAL; 587 588 return 0; 589 } 590 591 static int idxd_wqs_setup(struct idxd_device *idxd) 592 { 593 struct idxd_wq *wq; 594 struct idxd_group *group; 595 int i, j, configured = 0; 596 struct device *dev = &idxd->pdev->dev; 597 598 for (i = 0; i < idxd->max_groups; i++) { 599 group = &idxd->groups[i]; 600 for (j = 0; j < 4; j++) 601 group->grpcfg.wqs[j] = 0; 602 } 603 604 for (i = 0; i < idxd->max_wqs; i++) { 605 wq = &idxd->wqs[i]; 606 group = wq->group; 607 608 if (!wq->group) 609 continue; 610 if (!wq->size) 611 continue; 612 613 if (!wq_dedicated(wq)) { 614 dev_warn(dev, "No shared workqueue support.\n"); 615 return -EINVAL; 616 } 617 618 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 619 configured++; 620 } 621 622 if (configured == 0) 623 return -EINVAL; 624 625 return 0; 626 } 627 628 int idxd_device_config(struct idxd_device *idxd) 629 { 630 int rc; 631 632 lockdep_assert_held(&idxd->dev_lock); 633 rc = idxd_wqs_setup(idxd); 634 if (rc < 0) 635 return rc; 636 637 rc = idxd_engines_setup(idxd); 638 if (rc < 0) 639 return rc; 640 641 idxd_group_flags_setup(idxd); 642 643 rc = idxd_wqs_config_write(idxd); 644 if (rc < 0) 645 return rc; 646 647 rc = idxd_groups_config_write(idxd); 648 if (rc < 0) 649 return rc; 650 651 return 0; 652 } 653