1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <linux/irq.h> 10 #include <linux/msi.h> 11 #include <uapi/linux/idxd.h> 12 #include "../dmaengine.h" 13 #include "idxd.h" 14 #include "registers.h" 15 16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 17 u32 *status); 18 static void idxd_device_wqs_clear_state(struct idxd_device *idxd); 19 static void idxd_wq_disable_cleanup(struct idxd_wq *wq); 20 21 /* Interrupt control bits */ 22 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id) 23 { 24 struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector); 25 26 pci_msi_mask_irq(data); 27 } 28 29 void idxd_mask_msix_vectors(struct idxd_device *idxd) 30 { 31 struct pci_dev *pdev = idxd->pdev; 32 int msixcnt = pci_msix_vec_count(pdev); 33 int i; 34 35 for (i = 0; i < msixcnt; i++) 36 idxd_mask_msix_vector(idxd, i); 37 } 38 39 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id) 40 { 41 struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector); 42 43 pci_msi_unmask_irq(data); 44 } 45 46 void idxd_unmask_error_interrupts(struct idxd_device *idxd) 47 { 48 union genctrl_reg genctrl; 49 50 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 51 genctrl.softerr_int_en = 1; 52 genctrl.halt_int_en = 1; 53 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 54 } 55 56 void idxd_mask_error_interrupts(struct idxd_device *idxd) 57 { 58 union genctrl_reg genctrl; 59 60 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 61 genctrl.softerr_int_en = 0; 62 genctrl.halt_int_en = 0; 63 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 64 } 65 66 static void free_hw_descs(struct idxd_wq *wq) 67 { 68 int i; 69 70 for (i = 0; i < wq->num_descs; i++) 71 kfree(wq->hw_descs[i]); 72 73 kfree(wq->hw_descs); 74 } 75 76 static int alloc_hw_descs(struct idxd_wq *wq, int num) 77 { 78 struct device *dev = &wq->idxd->pdev->dev; 79 int i; 80 int node = dev_to_node(dev); 81 82 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), 83 GFP_KERNEL, node); 84 if (!wq->hw_descs) 85 return -ENOMEM; 86 87 for (i = 0; i < num; i++) { 88 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), 89 GFP_KERNEL, node); 90 if (!wq->hw_descs[i]) { 91 free_hw_descs(wq); 92 return -ENOMEM; 93 } 94 } 95 96 return 0; 97 } 98 99 static void free_descs(struct idxd_wq *wq) 100 { 101 int i; 102 103 for (i = 0; i < wq->num_descs; i++) 104 kfree(wq->descs[i]); 105 106 kfree(wq->descs); 107 } 108 109 static int alloc_descs(struct idxd_wq *wq, int num) 110 { 111 struct device *dev = &wq->idxd->pdev->dev; 112 int i; 113 int node = dev_to_node(dev); 114 115 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), 116 GFP_KERNEL, node); 117 if (!wq->descs) 118 return -ENOMEM; 119 120 for (i = 0; i < num; i++) { 121 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), 122 GFP_KERNEL, node); 123 if (!wq->descs[i]) { 124 free_descs(wq); 125 return -ENOMEM; 126 } 127 } 128 129 return 0; 130 } 131 132 /* WQ control bits */ 133 int idxd_wq_alloc_resources(struct idxd_wq *wq) 134 { 135 struct idxd_device *idxd = wq->idxd; 136 struct device *dev = &idxd->pdev->dev; 137 int rc, num_descs, i; 138 int align; 139 u64 tmp; 140 141 if (wq->type != IDXD_WQT_KERNEL) 142 return 0; 143 144 wq->num_descs = wq->size; 145 num_descs = wq->size; 146 147 rc = alloc_hw_descs(wq, num_descs); 148 if (rc < 0) 149 return rc; 150 151 align = idxd->data->align; 152 wq->compls_size = num_descs * idxd->data->compl_size + align; 153 wq->compls_raw = dma_alloc_coherent(dev, wq->compls_size, 154 &wq->compls_addr_raw, GFP_KERNEL); 155 if (!wq->compls_raw) { 156 rc = -ENOMEM; 157 goto fail_alloc_compls; 158 } 159 160 /* Adjust alignment */ 161 wq->compls_addr = (wq->compls_addr_raw + (align - 1)) & ~(align - 1); 162 tmp = (u64)wq->compls_raw; 163 tmp = (tmp + (align - 1)) & ~(align - 1); 164 wq->compls = (struct dsa_completion_record *)tmp; 165 166 rc = alloc_descs(wq, num_descs); 167 if (rc < 0) 168 goto fail_alloc_descs; 169 170 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL, 171 dev_to_node(dev)); 172 if (rc < 0) 173 goto fail_sbitmap_init; 174 175 for (i = 0; i < num_descs; i++) { 176 struct idxd_desc *desc = wq->descs[i]; 177 178 desc->hw = wq->hw_descs[i]; 179 if (idxd->data->type == IDXD_TYPE_DSA) 180 desc->completion = &wq->compls[i]; 181 else if (idxd->data->type == IDXD_TYPE_IAX) 182 desc->iax_completion = &wq->iax_compls[i]; 183 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i; 184 desc->id = i; 185 desc->wq = wq; 186 desc->cpu = -1; 187 } 188 189 return 0; 190 191 fail_sbitmap_init: 192 free_descs(wq); 193 fail_alloc_descs: 194 dma_free_coherent(dev, wq->compls_size, wq->compls_raw, 195 wq->compls_addr_raw); 196 fail_alloc_compls: 197 free_hw_descs(wq); 198 return rc; 199 } 200 201 void idxd_wq_free_resources(struct idxd_wq *wq) 202 { 203 struct device *dev = &wq->idxd->pdev->dev; 204 205 if (wq->type != IDXD_WQT_KERNEL) 206 return; 207 208 free_hw_descs(wq); 209 free_descs(wq); 210 dma_free_coherent(dev, wq->compls_size, wq->compls_raw, 211 wq->compls_addr_raw); 212 sbitmap_queue_free(&wq->sbq); 213 } 214 215 int idxd_wq_enable(struct idxd_wq *wq) 216 { 217 struct idxd_device *idxd = wq->idxd; 218 struct device *dev = &idxd->pdev->dev; 219 u32 status; 220 221 if (wq->state == IDXD_WQ_ENABLED) { 222 dev_dbg(dev, "WQ %d already enabled\n", wq->id); 223 return -ENXIO; 224 } 225 226 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status); 227 228 if (status != IDXD_CMDSTS_SUCCESS && 229 status != IDXD_CMDSTS_ERR_WQ_ENABLED) { 230 dev_dbg(dev, "WQ enable failed: %#x\n", status); 231 return -ENXIO; 232 } 233 234 wq->state = IDXD_WQ_ENABLED; 235 dev_dbg(dev, "WQ %d enabled\n", wq->id); 236 return 0; 237 } 238 239 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config) 240 { 241 struct idxd_device *idxd = wq->idxd; 242 struct device *dev = &idxd->pdev->dev; 243 u32 status, operand; 244 245 dev_dbg(dev, "Disabling WQ %d\n", wq->id); 246 247 if (wq->state != IDXD_WQ_ENABLED) { 248 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 249 return 0; 250 } 251 252 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 253 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status); 254 255 if (status != IDXD_CMDSTS_SUCCESS) { 256 dev_dbg(dev, "WQ disable failed: %#x\n", status); 257 return -ENXIO; 258 } 259 260 if (reset_config) 261 idxd_wq_disable_cleanup(wq); 262 wq->state = IDXD_WQ_DISABLED; 263 dev_dbg(dev, "WQ %d disabled\n", wq->id); 264 return 0; 265 } 266 267 void idxd_wq_drain(struct idxd_wq *wq) 268 { 269 struct idxd_device *idxd = wq->idxd; 270 struct device *dev = &idxd->pdev->dev; 271 u32 operand; 272 273 if (wq->state != IDXD_WQ_ENABLED) { 274 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 275 return; 276 } 277 278 dev_dbg(dev, "Draining WQ %d\n", wq->id); 279 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 280 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL); 281 } 282 283 void idxd_wq_reset(struct idxd_wq *wq) 284 { 285 struct idxd_device *idxd = wq->idxd; 286 struct device *dev = &idxd->pdev->dev; 287 u32 operand; 288 289 if (wq->state != IDXD_WQ_ENABLED) { 290 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 291 return; 292 } 293 294 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 295 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL); 296 idxd_wq_disable_cleanup(wq); 297 wq->state = IDXD_WQ_DISABLED; 298 } 299 300 int idxd_wq_map_portal(struct idxd_wq *wq) 301 { 302 struct idxd_device *idxd = wq->idxd; 303 struct pci_dev *pdev = idxd->pdev; 304 struct device *dev = &pdev->dev; 305 resource_size_t start; 306 307 start = pci_resource_start(pdev, IDXD_WQ_BAR); 308 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED); 309 310 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 311 if (!wq->portal) 312 return -ENOMEM; 313 314 return 0; 315 } 316 317 void idxd_wq_unmap_portal(struct idxd_wq *wq) 318 { 319 struct device *dev = &wq->idxd->pdev->dev; 320 321 devm_iounmap(dev, wq->portal); 322 wq->portal = NULL; 323 } 324 325 void idxd_wqs_unmap_portal(struct idxd_device *idxd) 326 { 327 int i; 328 329 for (i = 0; i < idxd->max_wqs; i++) { 330 struct idxd_wq *wq = idxd->wqs[i]; 331 332 if (wq->portal) 333 idxd_wq_unmap_portal(wq); 334 } 335 } 336 337 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid) 338 { 339 struct idxd_device *idxd = wq->idxd; 340 int rc; 341 union wqcfg wqcfg; 342 unsigned int offset; 343 unsigned long flags; 344 345 rc = idxd_wq_disable(wq, false); 346 if (rc < 0) 347 return rc; 348 349 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 350 spin_lock_irqsave(&idxd->dev_lock, flags); 351 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 352 wqcfg.pasid_en = 1; 353 wqcfg.pasid = pasid; 354 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 355 spin_unlock_irqrestore(&idxd->dev_lock, flags); 356 357 rc = idxd_wq_enable(wq); 358 if (rc < 0) 359 return rc; 360 361 return 0; 362 } 363 364 int idxd_wq_disable_pasid(struct idxd_wq *wq) 365 { 366 struct idxd_device *idxd = wq->idxd; 367 int rc; 368 union wqcfg wqcfg; 369 unsigned int offset; 370 unsigned long flags; 371 372 rc = idxd_wq_disable(wq, false); 373 if (rc < 0) 374 return rc; 375 376 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 377 spin_lock_irqsave(&idxd->dev_lock, flags); 378 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 379 wqcfg.pasid_en = 0; 380 wqcfg.pasid = 0; 381 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 382 spin_unlock_irqrestore(&idxd->dev_lock, flags); 383 384 rc = idxd_wq_enable(wq); 385 if (rc < 0) 386 return rc; 387 388 return 0; 389 } 390 391 static void idxd_wq_disable_cleanup(struct idxd_wq *wq) 392 { 393 struct idxd_device *idxd = wq->idxd; 394 395 lockdep_assert_held(&wq->wq_lock); 396 memset(wq->wqcfg, 0, idxd->wqcfg_size); 397 wq->type = IDXD_WQT_NONE; 398 wq->size = 0; 399 wq->group = NULL; 400 wq->threshold = 0; 401 wq->priority = 0; 402 wq->ats_dis = 0; 403 clear_bit(WQ_FLAG_DEDICATED, &wq->flags); 404 memset(wq->name, 0, WQ_NAME_SIZE); 405 } 406 407 static void idxd_wq_ref_release(struct percpu_ref *ref) 408 { 409 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active); 410 411 complete(&wq->wq_dead); 412 } 413 414 int idxd_wq_init_percpu_ref(struct idxd_wq *wq) 415 { 416 int rc; 417 418 memset(&wq->wq_active, 0, sizeof(wq->wq_active)); 419 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 0, GFP_KERNEL); 420 if (rc < 0) 421 return rc; 422 reinit_completion(&wq->wq_dead); 423 return 0; 424 } 425 426 void idxd_wq_quiesce(struct idxd_wq *wq) 427 { 428 percpu_ref_kill(&wq->wq_active); 429 wait_for_completion(&wq->wq_dead); 430 percpu_ref_exit(&wq->wq_active); 431 } 432 433 /* Device control bits */ 434 static inline bool idxd_is_enabled(struct idxd_device *idxd) 435 { 436 union gensts_reg gensts; 437 438 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 439 440 if (gensts.state == IDXD_DEVICE_STATE_ENABLED) 441 return true; 442 return false; 443 } 444 445 static inline bool idxd_device_is_halted(struct idxd_device *idxd) 446 { 447 union gensts_reg gensts; 448 449 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 450 451 return (gensts.state == IDXD_DEVICE_STATE_HALT); 452 } 453 454 /* 455 * This is function is only used for reset during probe and will 456 * poll for completion. Once the device is setup with interrupts, 457 * all commands will be done via interrupt completion. 458 */ 459 int idxd_device_init_reset(struct idxd_device *idxd) 460 { 461 struct device *dev = &idxd->pdev->dev; 462 union idxd_command_reg cmd; 463 unsigned long flags; 464 465 if (idxd_device_is_halted(idxd)) { 466 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 467 return -ENXIO; 468 } 469 470 memset(&cmd, 0, sizeof(cmd)); 471 cmd.cmd = IDXD_CMD_RESET_DEVICE; 472 dev_dbg(dev, "%s: sending reset for init.\n", __func__); 473 spin_lock_irqsave(&idxd->cmd_lock, flags); 474 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 475 476 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & 477 IDXD_CMDSTS_ACTIVE) 478 cpu_relax(); 479 spin_unlock_irqrestore(&idxd->cmd_lock, flags); 480 return 0; 481 } 482 483 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 484 u32 *status) 485 { 486 union idxd_command_reg cmd; 487 DECLARE_COMPLETION_ONSTACK(done); 488 unsigned long flags; 489 u32 stat; 490 491 if (idxd_device_is_halted(idxd)) { 492 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 493 if (status) 494 *status = IDXD_CMDSTS_HW_ERR; 495 return; 496 } 497 498 memset(&cmd, 0, sizeof(cmd)); 499 cmd.cmd = cmd_code; 500 cmd.operand = operand; 501 cmd.int_req = 1; 502 503 spin_lock_irqsave(&idxd->cmd_lock, flags); 504 wait_event_lock_irq(idxd->cmd_waitq, 505 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags), 506 idxd->cmd_lock); 507 508 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n", 509 __func__, cmd_code, operand); 510 511 idxd->cmd_status = 0; 512 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 513 idxd->cmd_done = &done; 514 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 515 516 /* 517 * After command submitted, release lock and go to sleep until 518 * the command completes via interrupt. 519 */ 520 spin_unlock_irqrestore(&idxd->cmd_lock, flags); 521 wait_for_completion(&done); 522 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 523 spin_lock_irqsave(&idxd->cmd_lock, flags); 524 if (status) 525 *status = stat; 526 idxd->cmd_status = stat & GENMASK(7, 0); 527 528 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 529 /* Wake up other pending commands */ 530 wake_up(&idxd->cmd_waitq); 531 spin_unlock_irqrestore(&idxd->cmd_lock, flags); 532 } 533 534 int idxd_device_enable(struct idxd_device *idxd) 535 { 536 struct device *dev = &idxd->pdev->dev; 537 u32 status; 538 539 if (idxd_is_enabled(idxd)) { 540 dev_dbg(dev, "Device already enabled\n"); 541 return -ENXIO; 542 } 543 544 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status); 545 546 /* If the command is successful or if the device was enabled */ 547 if (status != IDXD_CMDSTS_SUCCESS && 548 status != IDXD_CMDSTS_ERR_DEV_ENABLED) { 549 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 550 return -ENXIO; 551 } 552 553 idxd->state = IDXD_DEV_ENABLED; 554 return 0; 555 } 556 557 int idxd_device_disable(struct idxd_device *idxd) 558 { 559 struct device *dev = &idxd->pdev->dev; 560 u32 status; 561 unsigned long flags; 562 563 if (!idxd_is_enabled(idxd)) { 564 dev_dbg(dev, "Device is not enabled\n"); 565 return 0; 566 } 567 568 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status); 569 570 /* If the command is successful or if the device was disabled */ 571 if (status != IDXD_CMDSTS_SUCCESS && 572 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) { 573 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 574 return -ENXIO; 575 } 576 577 spin_lock_irqsave(&idxd->dev_lock, flags); 578 idxd_device_clear_state(idxd); 579 idxd->state = IDXD_DEV_DISABLED; 580 spin_unlock_irqrestore(&idxd->dev_lock, flags); 581 return 0; 582 } 583 584 void idxd_device_reset(struct idxd_device *idxd) 585 { 586 unsigned long flags; 587 588 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 589 spin_lock_irqsave(&idxd->dev_lock, flags); 590 idxd_device_clear_state(idxd); 591 idxd->state = IDXD_DEV_DISABLED; 592 spin_unlock_irqrestore(&idxd->dev_lock, flags); 593 } 594 595 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid) 596 { 597 struct device *dev = &idxd->pdev->dev; 598 u32 operand; 599 600 operand = pasid; 601 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand); 602 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL); 603 dev_dbg(dev, "pasid %d drained\n", pasid); 604 } 605 606 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 607 enum idxd_interrupt_type irq_type) 608 { 609 struct device *dev = &idxd->pdev->dev; 610 u32 operand, status; 611 612 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))) 613 return -EOPNOTSUPP; 614 615 dev_dbg(dev, "get int handle, idx %d\n", idx); 616 617 operand = idx & GENMASK(15, 0); 618 if (irq_type == IDXD_IRQ_IMS) 619 operand |= CMD_INT_HANDLE_IMS; 620 621 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand); 622 623 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status); 624 625 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 626 dev_dbg(dev, "request int handle failed: %#x\n", status); 627 return -ENXIO; 628 } 629 630 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0); 631 632 dev_dbg(dev, "int handle acquired: %u\n", *handle); 633 return 0; 634 } 635 636 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 637 enum idxd_interrupt_type irq_type) 638 { 639 struct device *dev = &idxd->pdev->dev; 640 u32 operand, status; 641 union idxd_command_reg cmd; 642 unsigned long flags; 643 644 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))) 645 return -EOPNOTSUPP; 646 647 dev_dbg(dev, "release int handle, handle %d\n", handle); 648 649 memset(&cmd, 0, sizeof(cmd)); 650 operand = handle & GENMASK(15, 0); 651 652 if (irq_type == IDXD_IRQ_IMS) 653 operand |= CMD_INT_HANDLE_IMS; 654 655 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE; 656 cmd.operand = operand; 657 658 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand); 659 660 spin_lock_irqsave(&idxd->cmd_lock, flags); 661 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 662 663 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE) 664 cpu_relax(); 665 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 666 spin_unlock_irqrestore(&idxd->cmd_lock, flags); 667 668 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 669 dev_dbg(dev, "release int handle failed: %#x\n", status); 670 return -ENXIO; 671 } 672 673 dev_dbg(dev, "int handle released.\n"); 674 return 0; 675 } 676 677 /* Device configuration bits */ 678 static void idxd_engines_clear_state(struct idxd_device *idxd) 679 { 680 struct idxd_engine *engine; 681 int i; 682 683 lockdep_assert_held(&idxd->dev_lock); 684 for (i = 0; i < idxd->max_engines; i++) { 685 engine = idxd->engines[i]; 686 engine->group = NULL; 687 } 688 } 689 690 static void idxd_groups_clear_state(struct idxd_device *idxd) 691 { 692 struct idxd_group *group; 693 int i; 694 695 lockdep_assert_held(&idxd->dev_lock); 696 for (i = 0; i < idxd->max_groups; i++) { 697 group = idxd->groups[i]; 698 memset(&group->grpcfg, 0, sizeof(group->grpcfg)); 699 group->num_engines = 0; 700 group->num_wqs = 0; 701 group->use_token_limit = false; 702 group->tokens_allowed = 0; 703 group->tokens_reserved = 0; 704 group->tc_a = -1; 705 group->tc_b = -1; 706 } 707 } 708 709 static void idxd_device_wqs_clear_state(struct idxd_device *idxd) 710 { 711 int i; 712 713 lockdep_assert_held(&idxd->dev_lock); 714 for (i = 0; i < idxd->max_wqs; i++) { 715 struct idxd_wq *wq = idxd->wqs[i]; 716 717 if (wq->state == IDXD_WQ_ENABLED) { 718 idxd_wq_disable_cleanup(wq); 719 wq->state = IDXD_WQ_DISABLED; 720 } 721 } 722 } 723 724 void idxd_device_clear_state(struct idxd_device *idxd) 725 { 726 idxd_groups_clear_state(idxd); 727 idxd_engines_clear_state(idxd); 728 idxd_device_wqs_clear_state(idxd); 729 } 730 731 void idxd_msix_perm_setup(struct idxd_device *idxd) 732 { 733 union msix_perm mperm; 734 int i, msixcnt; 735 736 msixcnt = pci_msix_vec_count(idxd->pdev); 737 if (msixcnt < 0) 738 return; 739 740 mperm.bits = 0; 741 mperm.pasid = idxd->pasid; 742 mperm.pasid_en = device_pasid_enabled(idxd); 743 for (i = 1; i < msixcnt; i++) 744 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8); 745 } 746 747 void idxd_msix_perm_clear(struct idxd_device *idxd) 748 { 749 union msix_perm mperm; 750 int i, msixcnt; 751 752 msixcnt = pci_msix_vec_count(idxd->pdev); 753 if (msixcnt < 0) 754 return; 755 756 mperm.bits = 0; 757 for (i = 1; i < msixcnt; i++) 758 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8); 759 } 760 761 static void idxd_group_config_write(struct idxd_group *group) 762 { 763 struct idxd_device *idxd = group->idxd; 764 struct device *dev = &idxd->pdev->dev; 765 int i; 766 u32 grpcfg_offset; 767 768 dev_dbg(dev, "Writing group %d cfg registers\n", group->id); 769 770 /* setup GRPWQCFG */ 771 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 772 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 773 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset); 774 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 775 group->id, i, grpcfg_offset, 776 ioread64(idxd->reg_base + grpcfg_offset)); 777 } 778 779 /* setup GRPENGCFG */ 780 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 781 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 782 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 783 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); 784 785 /* setup GRPFLAGS */ 786 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 787 iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); 788 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 789 group->id, grpcfg_offset, 790 ioread32(idxd->reg_base + grpcfg_offset)); 791 } 792 793 static int idxd_groups_config_write(struct idxd_device *idxd) 794 795 { 796 union gencfg_reg reg; 797 int i; 798 struct device *dev = &idxd->pdev->dev; 799 800 /* Setup bandwidth token limit */ 801 if (idxd->token_limit) { 802 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 803 reg.token_limit = idxd->token_limit; 804 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 805 } 806 807 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET, 808 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET)); 809 810 for (i = 0; i < idxd->max_groups; i++) { 811 struct idxd_group *group = idxd->groups[i]; 812 813 idxd_group_config_write(group); 814 } 815 816 return 0; 817 } 818 819 static int idxd_wq_config_write(struct idxd_wq *wq) 820 { 821 struct idxd_device *idxd = wq->idxd; 822 struct device *dev = &idxd->pdev->dev; 823 u32 wq_offset; 824 int i; 825 826 if (!wq->group) 827 return 0; 828 829 /* 830 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after 831 * wq reset. This will copy back the sticky values that are present on some devices. 832 */ 833 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 834 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 835 wq->wqcfg->bits[i] = ioread32(idxd->reg_base + wq_offset); 836 } 837 838 /* byte 0-3 */ 839 wq->wqcfg->wq_size = wq->size; 840 841 if (wq->size == 0) { 842 dev_warn(dev, "Incorrect work queue size: 0\n"); 843 return -EINVAL; 844 } 845 846 /* bytes 4-7 */ 847 wq->wqcfg->wq_thresh = wq->threshold; 848 849 /* byte 8-11 */ 850 wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL); 851 if (wq_dedicated(wq)) 852 wq->wqcfg->mode = 1; 853 854 if (device_pasid_enabled(idxd)) { 855 wq->wqcfg->pasid_en = 1; 856 if (wq->type == IDXD_WQT_KERNEL && wq_dedicated(wq)) 857 wq->wqcfg->pasid = idxd->pasid; 858 } 859 860 wq->wqcfg->priority = wq->priority; 861 862 if (idxd->hw.gen_cap.block_on_fault && 863 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags)) 864 wq->wqcfg->bof = 1; 865 866 if (idxd->hw.wq_cap.wq_ats_support) 867 wq->wqcfg->wq_ats_disable = wq->ats_dis; 868 869 /* bytes 12-15 */ 870 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 871 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size); 872 873 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 874 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 875 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 876 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); 877 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 878 wq->id, i, wq_offset, 879 ioread32(idxd->reg_base + wq_offset)); 880 } 881 882 return 0; 883 } 884 885 static int idxd_wqs_config_write(struct idxd_device *idxd) 886 { 887 int i, rc; 888 889 for (i = 0; i < idxd->max_wqs; i++) { 890 struct idxd_wq *wq = idxd->wqs[i]; 891 892 rc = idxd_wq_config_write(wq); 893 if (rc < 0) 894 return rc; 895 } 896 897 return 0; 898 } 899 900 static void idxd_group_flags_setup(struct idxd_device *idxd) 901 { 902 int i; 903 904 /* TC-A 0 and TC-B 1 should be defaults */ 905 for (i = 0; i < idxd->max_groups; i++) { 906 struct idxd_group *group = idxd->groups[i]; 907 908 if (group->tc_a == -1) 909 group->tc_a = group->grpcfg.flags.tc_a = 0; 910 else 911 group->grpcfg.flags.tc_a = group->tc_a; 912 if (group->tc_b == -1) 913 group->tc_b = group->grpcfg.flags.tc_b = 1; 914 else 915 group->grpcfg.flags.tc_b = group->tc_b; 916 group->grpcfg.flags.use_token_limit = group->use_token_limit; 917 group->grpcfg.flags.tokens_reserved = group->tokens_reserved; 918 if (group->tokens_allowed) 919 group->grpcfg.flags.tokens_allowed = 920 group->tokens_allowed; 921 else 922 group->grpcfg.flags.tokens_allowed = idxd->max_tokens; 923 } 924 } 925 926 static int idxd_engines_setup(struct idxd_device *idxd) 927 { 928 int i, engines = 0; 929 struct idxd_engine *eng; 930 struct idxd_group *group; 931 932 for (i = 0; i < idxd->max_groups; i++) { 933 group = idxd->groups[i]; 934 group->grpcfg.engines = 0; 935 } 936 937 for (i = 0; i < idxd->max_engines; i++) { 938 eng = idxd->engines[i]; 939 group = eng->group; 940 941 if (!group) 942 continue; 943 944 group->grpcfg.engines |= BIT(eng->id); 945 engines++; 946 } 947 948 if (!engines) 949 return -EINVAL; 950 951 return 0; 952 } 953 954 static int idxd_wqs_setup(struct idxd_device *idxd) 955 { 956 struct idxd_wq *wq; 957 struct idxd_group *group; 958 int i, j, configured = 0; 959 struct device *dev = &idxd->pdev->dev; 960 961 for (i = 0; i < idxd->max_groups; i++) { 962 group = idxd->groups[i]; 963 for (j = 0; j < 4; j++) 964 group->grpcfg.wqs[j] = 0; 965 } 966 967 for (i = 0; i < idxd->max_wqs; i++) { 968 wq = idxd->wqs[i]; 969 group = wq->group; 970 971 if (!wq->group) 972 continue; 973 if (!wq->size) 974 continue; 975 976 if (wq_shared(wq) && !device_swq_supported(idxd)) { 977 dev_warn(dev, "No shared wq support but configured.\n"); 978 return -EINVAL; 979 } 980 981 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 982 configured++; 983 } 984 985 if (configured == 0) 986 return -EINVAL; 987 988 return 0; 989 } 990 991 int idxd_device_config(struct idxd_device *idxd) 992 { 993 int rc; 994 995 lockdep_assert_held(&idxd->dev_lock); 996 rc = idxd_wqs_setup(idxd); 997 if (rc < 0) 998 return rc; 999 1000 rc = idxd_engines_setup(idxd); 1001 if (rc < 0) 1002 return rc; 1003 1004 idxd_group_flags_setup(idxd); 1005 1006 rc = idxd_wqs_config_write(idxd); 1007 if (rc < 0) 1008 return rc; 1009 1010 rc = idxd_groups_config_write(idxd); 1011 if (rc < 0) 1012 return rc; 1013 1014 return 0; 1015 } 1016 1017 static int idxd_wq_load_config(struct idxd_wq *wq) 1018 { 1019 struct idxd_device *idxd = wq->idxd; 1020 struct device *dev = &idxd->pdev->dev; 1021 int wqcfg_offset; 1022 int i; 1023 1024 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0); 1025 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size); 1026 1027 wq->size = wq->wqcfg->wq_size; 1028 wq->threshold = wq->wqcfg->wq_thresh; 1029 if (wq->wqcfg->priv) 1030 wq->type = IDXD_WQT_KERNEL; 1031 1032 /* The driver does not support shared WQ mode in read-only config yet */ 1033 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en) 1034 return -EOPNOTSUPP; 1035 1036 set_bit(WQ_FLAG_DEDICATED, &wq->flags); 1037 1038 wq->priority = wq->wqcfg->priority; 1039 1040 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1041 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i); 1042 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]); 1043 } 1044 1045 return 0; 1046 } 1047 1048 static void idxd_group_load_config(struct idxd_group *group) 1049 { 1050 struct idxd_device *idxd = group->idxd; 1051 struct device *dev = &idxd->pdev->dev; 1052 int i, j, grpcfg_offset; 1053 1054 /* 1055 * Load WQS bit fields 1056 * Iterate through all 256 bits 64 bits at a time 1057 */ 1058 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 1059 struct idxd_wq *wq; 1060 1061 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 1062 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset); 1063 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 1064 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]); 1065 1066 if (i * 64 >= idxd->max_wqs) 1067 break; 1068 1069 /* Iterate through all 64 bits and check for wq set */ 1070 for (j = 0; j < 64; j++) { 1071 int id = i * 64 + j; 1072 1073 /* No need to check beyond max wqs */ 1074 if (id >= idxd->max_wqs) 1075 break; 1076 1077 /* Set group assignment for wq if wq bit is set */ 1078 if (group->grpcfg.wqs[i] & BIT(j)) { 1079 wq = idxd->wqs[id]; 1080 wq->group = group; 1081 } 1082 } 1083 } 1084 1085 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 1086 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset); 1087 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 1088 grpcfg_offset, group->grpcfg.engines); 1089 1090 /* Iterate through all 64 bits to check engines set */ 1091 for (i = 0; i < 64; i++) { 1092 if (i >= idxd->max_engines) 1093 break; 1094 1095 if (group->grpcfg.engines & BIT(i)) { 1096 struct idxd_engine *engine = idxd->engines[i]; 1097 1098 engine->group = group; 1099 } 1100 } 1101 1102 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 1103 group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset); 1104 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 1105 group->id, grpcfg_offset, group->grpcfg.flags.bits); 1106 } 1107 1108 int idxd_device_load_config(struct idxd_device *idxd) 1109 { 1110 union gencfg_reg reg; 1111 int i, rc; 1112 1113 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 1114 idxd->token_limit = reg.token_limit; 1115 1116 for (i = 0; i < idxd->max_groups; i++) { 1117 struct idxd_group *group = idxd->groups[i]; 1118 1119 idxd_group_load_config(group); 1120 } 1121 1122 for (i = 0; i < idxd->max_wqs; i++) { 1123 struct idxd_wq *wq = idxd->wqs[i]; 1124 1125 rc = idxd_wq_load_config(wq); 1126 if (rc < 0) 1127 return rc; 1128 } 1129 1130 return 0; 1131 } 1132 1133 int __drv_enable_wq(struct idxd_wq *wq) 1134 { 1135 struct idxd_device *idxd = wq->idxd; 1136 struct device *dev = &idxd->pdev->dev; 1137 unsigned long flags; 1138 int rc = -ENXIO; 1139 1140 lockdep_assert_held(&wq->wq_lock); 1141 1142 if (idxd->state != IDXD_DEV_ENABLED) 1143 goto err; 1144 1145 if (wq->state != IDXD_WQ_DISABLED) { 1146 dev_dbg(dev, "wq %d already enabled.\n", wq->id); 1147 rc = -EBUSY; 1148 goto err; 1149 } 1150 1151 if (!wq->group) { 1152 dev_dbg(dev, "wq %d not attached to group.\n", wq->id); 1153 goto err; 1154 } 1155 1156 if (strlen(wq->name) == 0) { 1157 dev_dbg(dev, "wq %d name not set.\n", wq->id); 1158 goto err; 1159 } 1160 1161 /* Shared WQ checks */ 1162 if (wq_shared(wq)) { 1163 if (!device_swq_supported(idxd)) { 1164 dev_dbg(dev, "PASID not enabled and shared wq.\n"); 1165 goto err; 1166 } 1167 /* 1168 * Shared wq with the threshold set to 0 means the user 1169 * did not set the threshold or transitioned from a 1170 * dedicated wq but did not set threshold. A value 1171 * of 0 would effectively disable the shared wq. The 1172 * driver does not allow a value of 0 to be set for 1173 * threshold via sysfs. 1174 */ 1175 if (wq->threshold == 0) { 1176 dev_dbg(dev, "Shared wq and threshold 0.\n"); 1177 goto err; 1178 } 1179 } 1180 1181 rc = 0; 1182 spin_lock_irqsave(&idxd->dev_lock, flags); 1183 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1184 rc = idxd_device_config(idxd); 1185 spin_unlock_irqrestore(&idxd->dev_lock, flags); 1186 if (rc < 0) { 1187 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc); 1188 goto err; 1189 } 1190 1191 rc = idxd_wq_enable(wq); 1192 if (rc < 0) { 1193 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc); 1194 goto err; 1195 } 1196 1197 rc = idxd_wq_map_portal(wq); 1198 if (rc < 0) { 1199 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc); 1200 goto err_map_portal; 1201 } 1202 1203 wq->client_count = 0; 1204 1205 if (is_idxd_wq_cdev(wq)) { 1206 rc = idxd_wq_add_cdev(wq); 1207 if (rc < 0) { 1208 dev_dbg(dev, "wq %d cdev creation failed\n", wq->id); 1209 goto err_client; 1210 } 1211 } 1212 1213 return 0; 1214 1215 err_client: 1216 idxd_wq_unmap_portal(wq); 1217 err_map_portal: 1218 rc = idxd_wq_disable(wq, false); 1219 if (rc < 0) 1220 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq))); 1221 err: 1222 return rc; 1223 } 1224 1225 int drv_enable_wq(struct idxd_wq *wq) 1226 { 1227 int rc; 1228 1229 mutex_lock(&wq->wq_lock); 1230 rc = __drv_enable_wq(wq); 1231 mutex_unlock(&wq->wq_lock); 1232 return rc; 1233 } 1234 1235 void __drv_disable_wq(struct idxd_wq *wq) 1236 { 1237 struct idxd_device *idxd = wq->idxd; 1238 struct device *dev = &idxd->pdev->dev; 1239 1240 lockdep_assert_held(&wq->wq_lock); 1241 1242 if (is_idxd_wq_cdev(wq)) 1243 idxd_wq_del_cdev(wq); 1244 1245 if (idxd_wq_refcount(wq)) 1246 dev_warn(dev, "Clients has claim on wq %d: %d\n", 1247 wq->id, idxd_wq_refcount(wq)); 1248 1249 idxd_wq_unmap_portal(wq); 1250 1251 idxd_wq_drain(wq); 1252 idxd_wq_reset(wq); 1253 1254 wq->client_count = 0; 1255 } 1256 1257 void drv_disable_wq(struct idxd_wq *wq) 1258 { 1259 mutex_lock(&wq->wq_lock); 1260 __drv_disable_wq(wq); 1261 mutex_unlock(&wq->wq_lock); 1262 } 1263 1264 int idxd_device_drv_probe(struct idxd_dev *idxd_dev) 1265 { 1266 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1267 unsigned long flags; 1268 int rc = 0; 1269 1270 /* 1271 * Device should be in disabled state for the idxd_drv to load. If it's in 1272 * enabled state, then the device was altered outside of driver's control. 1273 * If the state is in halted state, then we don't want to proceed. 1274 */ 1275 if (idxd->state != IDXD_DEV_DISABLED) 1276 return -ENXIO; 1277 1278 /* Device configuration */ 1279 spin_lock_irqsave(&idxd->dev_lock, flags); 1280 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1281 rc = idxd_device_config(idxd); 1282 spin_unlock_irqrestore(&idxd->dev_lock, flags); 1283 if (rc < 0) 1284 return -ENXIO; 1285 1286 /* Start device */ 1287 rc = idxd_device_enable(idxd); 1288 if (rc < 0) 1289 return rc; 1290 1291 /* Setup DMA device without channels */ 1292 rc = idxd_register_dma_device(idxd); 1293 if (rc < 0) { 1294 idxd_device_disable(idxd); 1295 return rc; 1296 } 1297 1298 return 0; 1299 } 1300 1301 void idxd_device_drv_remove(struct idxd_dev *idxd_dev) 1302 { 1303 struct device *dev = &idxd_dev->conf_dev; 1304 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1305 int i; 1306 1307 for (i = 0; i < idxd->max_wqs; i++) { 1308 struct idxd_wq *wq = idxd->wqs[i]; 1309 struct device *wq_dev = wq_confdev(wq); 1310 1311 if (wq->state == IDXD_WQ_DISABLED) 1312 continue; 1313 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev)); 1314 device_release_driver(wq_dev); 1315 } 1316 1317 idxd_unregister_dma_device(idxd); 1318 idxd_device_disable(idxd); 1319 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1320 idxd_device_reset(idxd); 1321 } 1322 1323 static enum idxd_dev_type dev_types[] = { 1324 IDXD_DEV_DSA, 1325 IDXD_DEV_IAX, 1326 IDXD_DEV_NONE, 1327 }; 1328 1329 struct idxd_device_driver idxd_drv = { 1330 .type = dev_types, 1331 .probe = idxd_device_drv_probe, 1332 .remove = idxd_device_drv_remove, 1333 .name = "idxd", 1334 }; 1335