1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * 7 * Driver for the Freescale eDMA engine with flexible channel multiplexing 8 * capability for DMA request sources. The eDMA block can be found on some 9 * Vybrid and Layerscape SoCs. 10 */ 11 12 #include <dt-bindings/dma/fsl-edma.h> 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/clk.h> 16 #include <linux/of.h> 17 #include <linux/of_dma.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pm_domain.h> 21 #include <linux/property.h> 22 23 #include "fsl-edma-common.h" 24 25 static void fsl_edma_synchronize(struct dma_chan *chan) 26 { 27 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 28 29 vchan_synchronize(&fsl_chan->vchan); 30 } 31 32 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 33 { 34 struct fsl_edma_engine *fsl_edma = dev_id; 35 unsigned int intr, ch; 36 struct edma_regs *regs = &fsl_edma->regs; 37 38 intr = edma_readl(fsl_edma, regs->intl); 39 if (!intr) 40 return IRQ_NONE; 41 42 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 43 if (intr & (0x1 << ch)) { 44 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 45 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 46 } 47 } 48 return IRQ_HANDLED; 49 } 50 51 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 52 { 53 struct fsl_edma_chan *fsl_chan = dev_id; 54 unsigned int intr; 55 56 intr = edma_readl_chreg(fsl_chan, ch_int); 57 if (!intr) 58 return IRQ_HANDLED; 59 60 edma_writel_chreg(fsl_chan, 1, ch_int); 61 62 fsl_edma_tx_chan_handler(fsl_chan); 63 64 return IRQ_HANDLED; 65 } 66 67 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 68 { 69 struct fsl_edma_engine *fsl_edma = dev_id; 70 unsigned int err, ch; 71 struct edma_regs *regs = &fsl_edma->regs; 72 73 err = edma_readl(fsl_edma, regs->errl); 74 if (!err) 75 return IRQ_NONE; 76 77 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 78 if (err & (0x1 << ch)) { 79 fsl_edma_disable_request(&fsl_edma->chans[ch]); 80 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 81 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 82 } 83 } 84 return IRQ_HANDLED; 85 } 86 87 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 88 { 89 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 90 return IRQ_HANDLED; 91 92 return fsl_edma_err_handler(irq, dev_id); 93 } 94 95 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 96 struct of_dma *ofdma) 97 { 98 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 99 struct dma_chan *chan, *_chan; 100 struct fsl_edma_chan *fsl_chan; 101 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 102 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 103 104 if (dma_spec->args_count != 2) 105 return NULL; 106 107 mutex_lock(&fsl_edma->fsl_edma_mutex); 108 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 109 if (chan->client_count) 110 continue; 111 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 112 chan = dma_get_slave_channel(chan); 113 if (chan) { 114 chan->device->privatecnt++; 115 fsl_chan = to_fsl_edma_chan(chan); 116 fsl_chan->slave_id = dma_spec->args[1]; 117 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, 118 true); 119 mutex_unlock(&fsl_edma->fsl_edma_mutex); 120 return chan; 121 } 122 } 123 } 124 mutex_unlock(&fsl_edma->fsl_edma_mutex); 125 return NULL; 126 } 127 128 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 129 struct of_dma *ofdma) 130 { 131 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 132 struct dma_chan *chan, *_chan; 133 struct fsl_edma_chan *fsl_chan; 134 bool b_chmux; 135 int i; 136 137 if (dma_spec->args_count != 3) 138 return NULL; 139 140 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 141 142 mutex_lock(&fsl_edma->fsl_edma_mutex); 143 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 144 device_node) { 145 146 if (chan->client_count) 147 continue; 148 149 fsl_chan = to_fsl_edma_chan(chan); 150 i = fsl_chan - fsl_edma->chans; 151 152 fsl_chan->priority = dma_spec->args[1]; 153 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; 154 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; 155 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; 156 157 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) 158 continue; 159 160 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) 161 continue; 162 163 if (!b_chmux && i == dma_spec->args[0]) { 164 chan = dma_get_slave_channel(chan); 165 chan->device->privatecnt++; 166 mutex_unlock(&fsl_edma->fsl_edma_mutex); 167 return chan; 168 } else if (b_chmux && !fsl_chan->srcid) { 169 /* if controller support channel mux, choose a free channel */ 170 chan = dma_get_slave_channel(chan); 171 chan->device->privatecnt++; 172 fsl_chan->srcid = dma_spec->args[0]; 173 mutex_unlock(&fsl_edma->fsl_edma_mutex); 174 return chan; 175 } 176 } 177 mutex_unlock(&fsl_edma->fsl_edma_mutex); 178 return NULL; 179 } 180 181 static int 182 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 183 { 184 int ret; 185 186 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 187 188 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 189 if (fsl_edma->txirq < 0) 190 return fsl_edma->txirq; 191 192 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 193 if (fsl_edma->errirq < 0) 194 return fsl_edma->errirq; 195 196 if (fsl_edma->txirq == fsl_edma->errirq) { 197 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 198 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 199 if (ret) { 200 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 201 return ret; 202 } 203 } else { 204 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 205 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 206 if (ret) { 207 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 208 return ret; 209 } 210 211 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 212 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 213 if (ret) { 214 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 215 return ret; 216 } 217 } 218 219 return 0; 220 } 221 222 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 223 { 224 int ret; 225 int i; 226 227 for (i = 0; i < fsl_edma->n_chans; i++) { 228 229 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 230 231 if (fsl_edma->chan_masked & BIT(i)) 232 continue; 233 234 /* request channel irq */ 235 fsl_chan->txirq = platform_get_irq(pdev, i); 236 if (fsl_chan->txirq < 0) 237 return -EINVAL; 238 239 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, 240 fsl_edma3_tx_handler, IRQF_SHARED, 241 fsl_chan->chan_name, fsl_chan); 242 if (ret) { 243 dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i); 244 return -EINVAL; 245 } 246 } 247 248 return 0; 249 } 250 251 static int 252 fsl_edma2_irq_init(struct platform_device *pdev, 253 struct fsl_edma_engine *fsl_edma) 254 { 255 int i, ret, irq; 256 int count; 257 258 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 259 260 count = platform_irq_count(pdev); 261 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 262 if (count <= 2) { 263 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 264 return -EINVAL; 265 } 266 /* 267 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 268 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 269 * For now, just simply request irq without IRQF_SHARED flag, since 16 270 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 271 */ 272 for (i = 0; i < count; i++) { 273 irq = platform_get_irq(pdev, i); 274 if (irq < 0) 275 return -ENXIO; 276 277 /* The last IRQ is for eDMA err */ 278 if (i == count - 1) 279 ret = devm_request_irq(&pdev->dev, irq, 280 fsl_edma_err_handler, 281 0, "eDMA2-ERR", fsl_edma); 282 else 283 ret = devm_request_irq(&pdev->dev, irq, 284 fsl_edma_tx_handler, 0, 285 fsl_edma->chans[i].chan_name, 286 fsl_edma); 287 if (ret) 288 return ret; 289 } 290 291 return 0; 292 } 293 294 static void fsl_edma_irq_exit( 295 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 296 { 297 if (fsl_edma->txirq == fsl_edma->errirq) { 298 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 299 } else { 300 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 301 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 302 } 303 } 304 305 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 306 { 307 int i; 308 309 for (i = 0; i < nr_clocks; i++) 310 clk_disable_unprepare(fsl_edma->muxclk[i]); 311 } 312 313 static struct fsl_edma_drvdata vf610_data = { 314 .dmamuxs = DMAMUX_NR, 315 .flags = FSL_EDMA_DRV_WRAP_IO, 316 .chreg_off = EDMA_TCD, 317 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 318 .setup_irq = fsl_edma_irq_init, 319 }; 320 321 static struct fsl_edma_drvdata ls1028a_data = { 322 .dmamuxs = DMAMUX_NR, 323 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 324 .chreg_off = EDMA_TCD, 325 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 326 .setup_irq = fsl_edma_irq_init, 327 }; 328 329 static struct fsl_edma_drvdata imx7ulp_data = { 330 .dmamuxs = 1, 331 .chreg_off = EDMA_TCD, 332 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 333 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 334 .setup_irq = fsl_edma2_irq_init, 335 }; 336 337 static struct fsl_edma_drvdata imx8qm_data = { 338 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 339 .chreg_space_sz = 0x10000, 340 .chreg_off = 0x10000, 341 .setup_irq = fsl_edma3_irq_init, 342 }; 343 344 static struct fsl_edma_drvdata imx8qm_audio_data = { 345 .flags = FSL_EDMA_DRV_QUIRK_SWAPPED | FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 346 .chreg_space_sz = 0x10000, 347 .chreg_off = 0x10000, 348 .setup_irq = fsl_edma3_irq_init, 349 }; 350 351 static struct fsl_edma_drvdata imx93_data3 = { 352 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 353 .chreg_space_sz = 0x10000, 354 .chreg_off = 0x10000, 355 .setup_irq = fsl_edma3_irq_init, 356 }; 357 358 static struct fsl_edma_drvdata imx93_data4 = { 359 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, 360 .chreg_space_sz = 0x8000, 361 .chreg_off = 0x10000, 362 .setup_irq = fsl_edma3_irq_init, 363 }; 364 365 static const struct of_device_id fsl_edma_dt_ids[] = { 366 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 367 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 368 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 369 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 370 { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data}, 371 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 372 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 373 { /* sentinel */ } 374 }; 375 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 376 377 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 378 { 379 struct fsl_edma_chan *fsl_chan; 380 struct device_link *link; 381 struct device *pd_chan; 382 struct device *dev; 383 int i; 384 385 dev = &pdev->dev; 386 387 for (i = 0; i < fsl_edma->n_chans; i++) { 388 if (fsl_edma->chan_masked & BIT(i)) 389 continue; 390 391 fsl_chan = &fsl_edma->chans[i]; 392 393 pd_chan = dev_pm_domain_attach_by_id(dev, i); 394 if (IS_ERR_OR_NULL(pd_chan)) { 395 dev_err(dev, "Failed attach pd %d\n", i); 396 return -EINVAL; 397 } 398 399 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 400 DL_FLAG_PM_RUNTIME | 401 DL_FLAG_RPM_ACTIVE); 402 if (!link) { 403 dev_err(dev, "Failed to add device_link to %d\n", i); 404 return -EINVAL; 405 } 406 407 fsl_chan->pd_dev = pd_chan; 408 409 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 410 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 411 pm_runtime_set_active(fsl_chan->pd_dev); 412 } 413 414 return 0; 415 } 416 417 static int fsl_edma_probe(struct platform_device *pdev) 418 { 419 struct device_node *np = pdev->dev.of_node; 420 struct fsl_edma_engine *fsl_edma; 421 const struct fsl_edma_drvdata *drvdata = NULL; 422 u32 chan_mask[2] = {0, 0}; 423 struct edma_regs *regs; 424 int chans; 425 int ret, i; 426 427 drvdata = device_get_match_data(&pdev->dev); 428 if (!drvdata) { 429 dev_err(&pdev->dev, "unable to find driver data\n"); 430 return -EINVAL; 431 } 432 433 ret = of_property_read_u32(np, "dma-channels", &chans); 434 if (ret) { 435 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 436 return ret; 437 } 438 439 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 440 GFP_KERNEL); 441 if (!fsl_edma) 442 return -ENOMEM; 443 444 fsl_edma->drvdata = drvdata; 445 fsl_edma->n_chans = chans; 446 mutex_init(&fsl_edma->fsl_edma_mutex); 447 448 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 449 if (IS_ERR(fsl_edma->membase)) 450 return PTR_ERR(fsl_edma->membase); 451 452 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 453 fsl_edma_setup_regs(fsl_edma); 454 regs = &fsl_edma->regs; 455 } 456 457 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 458 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 459 if (IS_ERR(fsl_edma->dmaclk)) { 460 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 461 return PTR_ERR(fsl_edma->dmaclk); 462 } 463 } 464 465 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 466 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp"); 467 if (IS_ERR(fsl_edma->chclk)) { 468 dev_err(&pdev->dev, "Missing MP block clock.\n"); 469 return PTR_ERR(fsl_edma->chclk); 470 } 471 } 472 473 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 474 475 if (ret > 0) { 476 fsl_edma->chan_masked = chan_mask[1]; 477 fsl_edma->chan_masked <<= 32; 478 fsl_edma->chan_masked |= chan_mask[0]; 479 } 480 481 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 482 char clkname[32]; 483 484 /* eDMAv3 mux register move to TCD area if ch_mux exist */ 485 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) 486 break; 487 488 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 489 1 + i); 490 if (IS_ERR(fsl_edma->muxbase[i])) { 491 /* on error: disable all previously enabled clks */ 492 fsl_disable_clocks(fsl_edma, i); 493 return PTR_ERR(fsl_edma->muxbase[i]); 494 } 495 496 sprintf(clkname, "dmamux%d", i); 497 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 498 if (IS_ERR(fsl_edma->muxclk[i])) { 499 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 500 /* on error: disable all previously enabled clks */ 501 return PTR_ERR(fsl_edma->muxclk[i]); 502 } 503 } 504 505 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 506 507 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 508 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 509 if (ret) 510 return ret; 511 } 512 513 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 514 for (i = 0; i < fsl_edma->n_chans; i++) { 515 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 516 int len; 517 518 if (fsl_edma->chan_masked & BIT(i)) 519 continue; 520 521 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 522 dev_name(&pdev->dev), i); 523 524 fsl_chan->edma = fsl_edma; 525 fsl_chan->pm_state = RUNNING; 526 fsl_chan->slave_id = 0; 527 fsl_chan->idle = true; 528 fsl_chan->dma_dir = DMA_NONE; 529 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 530 531 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 532 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 533 fsl_chan->tcd = fsl_edma->membase 534 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 535 536 fsl_chan->pdev = pdev; 537 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 538 539 edma_write_tcdreg(fsl_chan, 0, csr); 540 fsl_edma_chan_mux(fsl_chan, 0, false); 541 } 542 543 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 544 if (ret) 545 return ret; 546 547 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 548 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 549 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 550 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 551 552 fsl_edma->dma_dev.dev = &pdev->dev; 553 fsl_edma->dma_dev.device_alloc_chan_resources 554 = fsl_edma_alloc_chan_resources; 555 fsl_edma->dma_dev.device_free_chan_resources 556 = fsl_edma_free_chan_resources; 557 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 558 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 559 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 560 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 561 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 562 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 563 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 564 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 565 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 566 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 567 568 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 569 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 570 571 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 572 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 573 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 574 } 575 576 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 577 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 578 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 579 580 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 581 DMAENGINE_ALIGN_64_BYTES : 582 DMAENGINE_ALIGN_32_BYTES; 583 584 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 585 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff); 586 587 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 588 589 platform_set_drvdata(pdev, fsl_edma); 590 591 ret = dma_async_device_register(&fsl_edma->dma_dev); 592 if (ret) { 593 dev_err(&pdev->dev, 594 "Can't register Freescale eDMA engine. (%d)\n", ret); 595 return ret; 596 } 597 598 ret = of_dma_controller_register(np, 599 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate, 600 fsl_edma); 601 if (ret) { 602 dev_err(&pdev->dev, 603 "Can't register Freescale eDMA of_dma. (%d)\n", ret); 604 dma_async_device_unregister(&fsl_edma->dma_dev); 605 return ret; 606 } 607 608 /* enable round robin arbitration */ 609 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 610 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 611 612 return 0; 613 } 614 615 static void fsl_edma_remove(struct platform_device *pdev) 616 { 617 struct device_node *np = pdev->dev.of_node; 618 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 619 620 fsl_edma_irq_exit(pdev, fsl_edma); 621 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 622 of_dma_controller_free(np); 623 dma_async_device_unregister(&fsl_edma->dma_dev); 624 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); 625 } 626 627 static int fsl_edma_suspend_late(struct device *dev) 628 { 629 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 630 struct fsl_edma_chan *fsl_chan; 631 unsigned long flags; 632 int i; 633 634 for (i = 0; i < fsl_edma->n_chans; i++) { 635 fsl_chan = &fsl_edma->chans[i]; 636 if (fsl_edma->chan_masked & BIT(i)) 637 continue; 638 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 639 /* Make sure chan is idle or will force disable. */ 640 if (unlikely(!fsl_chan->idle)) { 641 dev_warn(dev, "WARN: There is non-idle channel."); 642 fsl_edma_disable_request(fsl_chan); 643 fsl_edma_chan_mux(fsl_chan, 0, false); 644 } 645 646 fsl_chan->pm_state = SUSPENDED; 647 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 648 } 649 650 return 0; 651 } 652 653 static int fsl_edma_resume_early(struct device *dev) 654 { 655 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 656 struct fsl_edma_chan *fsl_chan; 657 struct edma_regs *regs = &fsl_edma->regs; 658 int i; 659 660 for (i = 0; i < fsl_edma->n_chans; i++) { 661 fsl_chan = &fsl_edma->chans[i]; 662 if (fsl_edma->chan_masked & BIT(i)) 663 continue; 664 fsl_chan->pm_state = RUNNING; 665 edma_write_tcdreg(fsl_chan, 0, csr); 666 if (fsl_chan->slave_id != 0) 667 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); 668 } 669 670 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 671 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 672 673 return 0; 674 } 675 676 /* 677 * eDMA provides the service to others, so it should be suspend late 678 * and resume early. When eDMA suspend, all of the clients should stop 679 * the DMA data transmission and let the channel idle. 680 */ 681 static const struct dev_pm_ops fsl_edma_pm_ops = { 682 .suspend_late = fsl_edma_suspend_late, 683 .resume_early = fsl_edma_resume_early, 684 }; 685 686 static struct platform_driver fsl_edma_driver = { 687 .driver = { 688 .name = "fsl-edma", 689 .of_match_table = fsl_edma_dt_ids, 690 .pm = &fsl_edma_pm_ops, 691 }, 692 .probe = fsl_edma_probe, 693 .remove_new = fsl_edma_remove, 694 }; 695 696 static int __init fsl_edma_init(void) 697 { 698 return platform_driver_register(&fsl_edma_driver); 699 } 700 subsys_initcall(fsl_edma_init); 701 702 static void __exit fsl_edma_exit(void) 703 { 704 platform_driver_unregister(&fsl_edma_driver); 705 } 706 module_exit(fsl_edma_exit); 707 708 MODULE_ALIAS("platform:fsl-edma"); 709 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 710 MODULE_LICENSE("GPL v2"); 711