1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * Copyright 2024 NXP 7 * 8 * Driver for the Freescale eDMA engine with flexible channel multiplexing 9 * capability for DMA request sources. The eDMA block can be found on some 10 * Vybrid, Layerscape and S32G SoCs. 11 */ 12 13 #include <dt-bindings/dma/fsl-edma.h> 14 #include <linux/bitfield.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_dma.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/pm_domain.h> 23 #include <linux/property.h> 24 25 #include "fsl-edma-common.h" 26 27 static void fsl_edma_synchronize(struct dma_chan *chan) 28 { 29 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 30 31 vchan_synchronize(&fsl_chan->vchan); 32 } 33 34 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 35 { 36 struct fsl_edma_engine *fsl_edma = dev_id; 37 unsigned int intr, ch; 38 struct edma_regs *regs = &fsl_edma->regs; 39 40 intr = edma_readl(fsl_edma, regs->intl); 41 if (!intr) 42 return IRQ_NONE; 43 44 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 45 if (intr & (0x1 << ch)) { 46 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 47 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 48 } 49 } 50 return IRQ_HANDLED; 51 } 52 53 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 54 { 55 struct fsl_edma_chan *fsl_chan = dev_id; 56 unsigned int intr; 57 58 intr = edma_readl_chreg(fsl_chan, ch_int); 59 if (!intr) 60 return IRQ_HANDLED; 61 62 edma_writel_chreg(fsl_chan, 1, ch_int); 63 64 fsl_edma_tx_chan_handler(fsl_chan); 65 66 return IRQ_HANDLED; 67 } 68 69 static irqreturn_t fsl_edma2_tx_handler(int irq, void *devi_id) 70 { 71 struct fsl_edma_chan *fsl_chan = devi_id; 72 73 return fsl_edma_tx_handler(irq, fsl_chan->edma); 74 } 75 76 static irqreturn_t fsl_edma3_or_tx_handler(int irq, void *dev_id, 77 u8 start, u8 end) 78 { 79 struct fsl_edma_engine *fsl_edma = dev_id; 80 struct fsl_edma_chan *chan; 81 int i; 82 83 end = min(end, fsl_edma->n_chans); 84 85 for (i = start; i < end; i++) { 86 chan = &fsl_edma->chans[i]; 87 88 fsl_edma3_tx_handler(irq, chan); 89 } 90 91 return IRQ_HANDLED; 92 } 93 94 static irqreturn_t fsl_edma3_tx_0_15_handler(int irq, void *dev_id) 95 { 96 return fsl_edma3_or_tx_handler(irq, dev_id, 0, 16); 97 } 98 99 static irqreturn_t fsl_edma3_tx_16_31_handler(int irq, void *dev_id) 100 { 101 return fsl_edma3_or_tx_handler(irq, dev_id, 16, 32); 102 } 103 104 static irqreturn_t fsl_edma3_or_err_handler(int irq, void *dev_id) 105 { 106 struct fsl_edma_engine *fsl_edma = dev_id; 107 struct edma_regs *regs = &fsl_edma->regs; 108 unsigned int err, ch, ch_es; 109 struct fsl_edma_chan *chan; 110 111 err = edma_readl(fsl_edma, regs->es); 112 if (!(err & EDMA_V3_MP_ES_VLD)) 113 return IRQ_NONE; 114 115 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 116 chan = &fsl_edma->chans[ch]; 117 118 ch_es = edma_readl_chreg(chan, ch_es); 119 if (!(ch_es & EDMA_V3_CH_ES_ERR)) 120 continue; 121 122 edma_writel_chreg(chan, EDMA_V3_CH_ES_ERR, ch_es); 123 fsl_edma_disable_request(chan); 124 fsl_edma->chans[ch].status = DMA_ERROR; 125 } 126 127 return IRQ_HANDLED; 128 } 129 130 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 131 { 132 struct fsl_edma_engine *fsl_edma = dev_id; 133 unsigned int err, ch; 134 struct edma_regs *regs = &fsl_edma->regs; 135 136 err = edma_readl(fsl_edma, regs->errl); 137 if (!err) 138 return IRQ_NONE; 139 140 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 141 if (err & (0x1 << ch)) { 142 fsl_edma_disable_request(&fsl_edma->chans[ch]); 143 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 144 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 145 } 146 } 147 return IRQ_HANDLED; 148 } 149 150 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 151 { 152 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 153 return IRQ_HANDLED; 154 155 return fsl_edma_err_handler(irq, dev_id); 156 } 157 158 static bool fsl_edma_srcid_in_use(struct fsl_edma_engine *fsl_edma, u32 srcid) 159 { 160 struct fsl_edma_chan *fsl_chan; 161 int i; 162 163 for (i = 0; i < fsl_edma->n_chans; i++) { 164 fsl_chan = &fsl_edma->chans[i]; 165 166 if (fsl_chan->srcid && srcid == fsl_chan->srcid) { 167 dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!"); 168 return true; 169 } 170 } 171 return false; 172 } 173 174 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 175 struct of_dma *ofdma) 176 { 177 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 178 struct dma_chan *chan, *_chan; 179 struct fsl_edma_chan *fsl_chan; 180 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 181 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 182 183 if (dma_spec->args_count != 2) 184 return NULL; 185 186 guard(mutex)(&fsl_edma->fsl_edma_mutex); 187 188 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 189 if (chan->client_count) 190 continue; 191 192 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[1])) 193 return NULL; 194 195 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 196 chan = dma_get_slave_channel(chan); 197 if (chan) { 198 chan->device->privatecnt++; 199 fsl_chan = to_fsl_edma_chan(chan); 200 fsl_chan->srcid = dma_spec->args[1]; 201 202 if (!fsl_chan->srcid) { 203 dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n", 204 fsl_chan->srcid); 205 return NULL; 206 } 207 208 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, 209 true); 210 return chan; 211 } 212 } 213 } 214 return NULL; 215 } 216 217 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 218 struct of_dma *ofdma) 219 { 220 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 221 struct dma_chan *chan, *_chan; 222 struct fsl_edma_chan *fsl_chan; 223 bool b_chmux; 224 int i; 225 226 if (dma_spec->args_count != 3) 227 return NULL; 228 229 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 230 231 guard(mutex)(&fsl_edma->fsl_edma_mutex); 232 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 233 device_node) { 234 235 if (chan->client_count) 236 continue; 237 238 fsl_chan = to_fsl_edma_chan(chan); 239 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[0])) 240 return NULL; 241 i = fsl_chan - fsl_edma->chans; 242 243 fsl_chan->priority = dma_spec->args[1]; 244 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; 245 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; 246 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; 247 248 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) 249 continue; 250 251 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) 252 continue; 253 254 if (!b_chmux && i == dma_spec->args[0]) { 255 chan = dma_get_slave_channel(chan); 256 chan->device->privatecnt++; 257 return chan; 258 } else if (b_chmux && !fsl_chan->srcid) { 259 /* if controller support channel mux, choose a free channel */ 260 chan = dma_get_slave_channel(chan); 261 chan->device->privatecnt++; 262 fsl_chan->srcid = dma_spec->args[0]; 263 return chan; 264 } 265 } 266 return NULL; 267 } 268 269 static int 270 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 271 { 272 int ret; 273 274 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 275 276 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 277 if (fsl_edma->txirq < 0) 278 return fsl_edma->txirq; 279 280 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 281 if (fsl_edma->errirq < 0) 282 return fsl_edma->errirq; 283 284 if (fsl_edma->txirq == fsl_edma->errirq) { 285 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 286 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 287 if (ret) { 288 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 289 return ret; 290 } 291 } else { 292 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 293 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 294 if (ret) { 295 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 296 return ret; 297 } 298 299 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 300 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 301 if (ret) { 302 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 303 return ret; 304 } 305 } 306 307 return 0; 308 } 309 310 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 311 { 312 int i; 313 314 for (i = 0; i < fsl_edma->n_chans; i++) { 315 316 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 317 318 if (fsl_edma->chan_masked & BIT(i)) 319 continue; 320 321 /* request channel irq */ 322 fsl_chan->txirq = platform_get_irq(pdev, i); 323 if (fsl_chan->txirq < 0) 324 return -EINVAL; 325 326 fsl_chan->irq_handler = fsl_edma3_tx_handler; 327 } 328 329 return 0; 330 } 331 332 static int fsl_edma3_or_irq_init(struct platform_device *pdev, 333 struct fsl_edma_engine *fsl_edma) 334 { 335 int ret; 336 337 fsl_edma->txirq = platform_get_irq_byname(pdev, "tx-0-15"); 338 if (fsl_edma->txirq < 0) 339 return fsl_edma->txirq; 340 341 fsl_edma->txirq_16_31 = platform_get_irq_byname(pdev, "tx-16-31"); 342 if (fsl_edma->txirq_16_31 < 0) 343 return fsl_edma->txirq_16_31; 344 345 fsl_edma->errirq = platform_get_irq_byname(pdev, "err"); 346 if (fsl_edma->errirq < 0) 347 return fsl_edma->errirq; 348 349 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 350 fsl_edma3_tx_0_15_handler, 0, "eDMA tx0_15", 351 fsl_edma); 352 if (ret) 353 return dev_err_probe(&pdev->dev, ret, 354 "Can't register eDMA tx0_15 IRQ.\n"); 355 356 if (fsl_edma->n_chans > 16) { 357 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq_16_31, 358 fsl_edma3_tx_16_31_handler, 0, 359 "eDMA tx16_31", fsl_edma); 360 if (ret) 361 return dev_err_probe(&pdev->dev, ret, 362 "Can't register eDMA tx16_31 IRQ.\n"); 363 } 364 365 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 366 fsl_edma3_or_err_handler, 0, "eDMA err", 367 fsl_edma); 368 if (ret) 369 return dev_err_probe(&pdev->dev, ret, 370 "Can't register eDMA err IRQ.\n"); 371 372 return 0; 373 } 374 375 static int 376 fsl_edma2_irq_init(struct platform_device *pdev, 377 struct fsl_edma_engine *fsl_edma) 378 { 379 int i, ret, irq; 380 int count; 381 382 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 383 384 count = platform_irq_count(pdev); 385 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 386 if (count <= 2) { 387 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 388 return -EINVAL; 389 } 390 /* 391 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 392 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 393 * For now, just simply request irq without IRQF_SHARED flag, since 16 394 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 395 */ 396 for (i = 0; i < count; i++) { 397 irq = platform_get_irq(pdev, i); 398 ret = 0; 399 if (irq < 0) 400 return -ENXIO; 401 402 /* The last IRQ is for eDMA err */ 403 if (i == count - 1) { 404 ret = devm_request_irq(&pdev->dev, irq, 405 fsl_edma_err_handler, 406 0, "eDMA2-ERR", fsl_edma); 407 } else { 408 fsl_edma->chans[i].txirq = irq; 409 fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler; 410 } 411 412 if (ret) 413 return ret; 414 } 415 416 return 0; 417 } 418 419 static void fsl_edma_irq_exit( 420 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 421 { 422 if (fsl_edma->txirq == fsl_edma->errirq) { 423 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 424 } else { 425 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 426 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 427 } 428 } 429 430 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 431 { 432 int i; 433 434 for (i = 0; i < nr_clocks; i++) 435 clk_disable_unprepare(fsl_edma->muxclk[i]); 436 } 437 438 static struct fsl_edma_drvdata vf610_data = { 439 .dmamuxs = DMAMUX_NR, 440 .flags = FSL_EDMA_DRV_WRAP_IO, 441 .chreg_off = EDMA_TCD, 442 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 443 .setup_irq = fsl_edma_irq_init, 444 }; 445 446 static struct fsl_edma_drvdata ls1028a_data = { 447 .dmamuxs = DMAMUX_NR, 448 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 449 .chreg_off = EDMA_TCD, 450 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 451 .setup_irq = fsl_edma_irq_init, 452 }; 453 454 static struct fsl_edma_drvdata imx7ulp_data = { 455 .dmamuxs = 1, 456 .chreg_off = EDMA_TCD, 457 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 458 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 459 .setup_irq = fsl_edma2_irq_init, 460 }; 461 462 static struct fsl_edma_drvdata imx8qm_data = { 463 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE, 464 .chreg_space_sz = 0x10000, 465 .chreg_off = 0x10000, 466 .setup_irq = fsl_edma3_irq_init, 467 }; 468 469 static struct fsl_edma_drvdata imx8ulp_data = { 470 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK | 471 FSL_EDMA_DRV_EDMA3, 472 .chreg_space_sz = 0x10000, 473 .chreg_off = 0x10000, 474 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 475 .mux_skip = 0x10000, 476 .setup_irq = fsl_edma3_irq_init, 477 }; 478 479 static struct fsl_edma_drvdata imx93_data3 = { 480 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 481 .chreg_space_sz = 0x10000, 482 .chreg_off = 0x10000, 483 .setup_irq = fsl_edma3_irq_init, 484 }; 485 486 static struct fsl_edma_drvdata imx93_data4 = { 487 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, 488 .chreg_space_sz = 0x8000, 489 .chreg_off = 0x10000, 490 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 491 .mux_skip = 0x8000, 492 .setup_irq = fsl_edma3_irq_init, 493 }; 494 495 static struct fsl_edma_drvdata imx95_data5 = { 496 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 | 497 FSL_EDMA_DRV_TCD64, 498 .chreg_space_sz = 0x8000, 499 .chreg_off = 0x10000, 500 .mux_off = 0x200, 501 .mux_skip = sizeof(u32), 502 .setup_irq = fsl_edma3_irq_init, 503 }; 504 505 static const struct fsl_edma_drvdata s32g2_data = { 506 .dmamuxs = DMAMUX_NR, 507 .chreg_space_sz = EDMA_TCD, 508 .chreg_off = 0x4000, 509 .flags = FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MUX_SWAP, 510 .setup_irq = fsl_edma3_or_irq_init, 511 }; 512 513 static const struct of_device_id fsl_edma_dt_ids[] = { 514 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 515 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 516 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 517 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 518 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data}, 519 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 520 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 521 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5}, 522 { .compatible = "nxp,s32g2-edma", .data = &s32g2_data}, 523 { /* sentinel */ } 524 }; 525 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 526 527 static void fsl_edma3_detach_pd(struct fsl_edma_engine *fsl_edma) 528 { 529 struct fsl_edma_chan *fsl_chan; 530 int i; 531 532 for (i = 0; i < fsl_edma->n_chans; i++) { 533 if (fsl_edma->chan_masked & BIT(i)) 534 continue; 535 fsl_chan = &fsl_edma->chans[i]; 536 if (fsl_chan->pd_dev_link) 537 device_link_del(fsl_chan->pd_dev_link); 538 if (fsl_chan->pd_dev) { 539 dev_pm_domain_detach(fsl_chan->pd_dev, false); 540 pm_runtime_dont_use_autosuspend(fsl_chan->pd_dev); 541 pm_runtime_set_suspended(fsl_chan->pd_dev); 542 } 543 } 544 } 545 546 static void devm_fsl_edma3_detach_pd(void *data) 547 { 548 fsl_edma3_detach_pd(data); 549 } 550 551 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 552 { 553 struct fsl_edma_chan *fsl_chan; 554 struct device *pd_chan; 555 struct device *dev; 556 int i; 557 558 dev = &pdev->dev; 559 560 for (i = 0; i < fsl_edma->n_chans; i++) { 561 if (fsl_edma->chan_masked & BIT(i)) 562 continue; 563 564 fsl_chan = &fsl_edma->chans[i]; 565 566 pd_chan = dev_pm_domain_attach_by_id(dev, i); 567 if (IS_ERR_OR_NULL(pd_chan)) { 568 dev_err(dev, "Failed attach pd %d\n", i); 569 goto detach; 570 } 571 572 fsl_chan->pd_dev_link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 573 DL_FLAG_PM_RUNTIME | 574 DL_FLAG_RPM_ACTIVE); 575 if (!fsl_chan->pd_dev_link) { 576 dev_err(dev, "Failed to add device_link to %d\n", i); 577 dev_pm_domain_detach(pd_chan, false); 578 goto detach; 579 } 580 581 fsl_chan->pd_dev = pd_chan; 582 583 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 584 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 585 pm_runtime_set_active(fsl_chan->pd_dev); 586 } 587 588 return 0; 589 590 detach: 591 fsl_edma3_detach_pd(fsl_edma); 592 return -EINVAL; 593 } 594 595 static int fsl_edma_probe(struct platform_device *pdev) 596 { 597 struct device_node *np = pdev->dev.of_node; 598 struct fsl_edma_engine *fsl_edma; 599 const struct fsl_edma_drvdata *drvdata = NULL; 600 u32 chan_mask[2] = {0, 0}; 601 char clk_name[36]; 602 struct edma_regs *regs; 603 int chans; 604 int ret, i; 605 606 drvdata = device_get_match_data(&pdev->dev); 607 if (!drvdata) { 608 dev_err(&pdev->dev, "unable to find driver data\n"); 609 return -EINVAL; 610 } 611 612 ret = of_property_read_u32(np, "dma-channels", &chans); 613 if (ret) { 614 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 615 return ret; 616 } 617 618 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 619 GFP_KERNEL); 620 if (!fsl_edma) 621 return -ENOMEM; 622 623 fsl_edma->drvdata = drvdata; 624 fsl_edma->n_chans = chans; 625 mutex_init(&fsl_edma->fsl_edma_mutex); 626 627 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 628 if (IS_ERR(fsl_edma->membase)) 629 return PTR_ERR(fsl_edma->membase); 630 631 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 632 fsl_edma_setup_regs(fsl_edma); 633 regs = &fsl_edma->regs; 634 } 635 636 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 637 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 638 if (IS_ERR(fsl_edma->dmaclk)) { 639 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 640 return PTR_ERR(fsl_edma->dmaclk); 641 } 642 } 643 644 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 645 646 if (ret > 0) { 647 fsl_edma->chan_masked = chan_mask[1]; 648 fsl_edma->chan_masked <<= 32; 649 fsl_edma->chan_masked |= chan_mask[0]; 650 } 651 652 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 653 char clkname[32]; 654 655 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 656 1 + i); 657 if (IS_ERR(fsl_edma->muxbase[i])) { 658 /* on error: disable all previously enabled clks */ 659 fsl_disable_clocks(fsl_edma, i); 660 return PTR_ERR(fsl_edma->muxbase[i]); 661 } 662 663 sprintf(clkname, "dmamux%d", i); 664 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 665 if (IS_ERR(fsl_edma->muxclk[i])) { 666 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 667 /* on error: disable all previously enabled clks */ 668 return PTR_ERR(fsl_edma->muxclk[i]); 669 } 670 } 671 672 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 673 674 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 675 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 676 if (ret) 677 return ret; 678 ret = devm_add_action_or_reset(&pdev->dev, devm_fsl_edma3_detach_pd, fsl_edma); 679 if (ret) 680 return ret; 681 } 682 683 if (drvdata->flags & FSL_EDMA_DRV_TCD64) 684 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 685 686 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 687 for (i = 0; i < fsl_edma->n_chans; i++) { 688 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 689 int len; 690 691 if (fsl_edma->chan_masked & BIT(i)) 692 continue; 693 694 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 695 dev_name(&pdev->dev), i); 696 697 fsl_chan->edma = fsl_edma; 698 fsl_chan->pm_state = RUNNING; 699 fsl_chan->srcid = 0; 700 fsl_chan->dma_dir = DMA_NONE; 701 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 702 703 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 704 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 705 fsl_chan->tcd = fsl_edma->membase 706 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 707 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; 708 709 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 710 snprintf(clk_name, sizeof(clk_name), "ch%02d", i); 711 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, 712 (const char *)clk_name); 713 714 if (IS_ERR(fsl_chan->clk)) 715 return PTR_ERR(fsl_chan->clk); 716 } 717 fsl_chan->pdev = pdev; 718 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 719 720 edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr); 721 fsl_edma_chan_mux(fsl_chan, 0, false); 722 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) 723 clk_disable_unprepare(fsl_chan->clk); 724 } 725 726 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 727 if (ret) 728 return ret; 729 730 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 731 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 732 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 733 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 734 735 fsl_edma->dma_dev.dev = &pdev->dev; 736 fsl_edma->dma_dev.device_alloc_chan_resources 737 = fsl_edma_alloc_chan_resources; 738 fsl_edma->dma_dev.device_free_chan_resources 739 = fsl_edma_free_chan_resources; 740 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 741 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 742 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 743 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 744 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 745 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 746 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 747 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 748 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 749 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 750 751 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 752 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 753 754 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 755 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 756 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 757 } 758 759 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 760 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 761 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 762 763 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 764 DMAENGINE_ALIGN_64_BYTES : 765 DMAENGINE_ALIGN_32_BYTES; 766 767 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 768 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 769 FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK)); 770 771 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 772 773 platform_set_drvdata(pdev, fsl_edma); 774 775 ret = dma_async_device_register(&fsl_edma->dma_dev); 776 if (ret) { 777 dev_err(&pdev->dev, 778 "Can't register Freescale eDMA engine. (%d)\n", ret); 779 return ret; 780 } 781 782 ret = of_dma_controller_register(np, 783 drvdata->dmamuxs ? fsl_edma_xlate : fsl_edma3_xlate, 784 fsl_edma); 785 if (ret) { 786 dev_err(&pdev->dev, 787 "Can't register Freescale eDMA of_dma. (%d)\n", ret); 788 dma_async_device_unregister(&fsl_edma->dma_dev); 789 return ret; 790 } 791 792 /* enable round robin arbitration */ 793 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 794 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 795 796 return 0; 797 } 798 799 static void fsl_edma_remove(struct platform_device *pdev) 800 { 801 struct device_node *np = pdev->dev.of_node; 802 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 803 804 fsl_edma_irq_exit(pdev, fsl_edma); 805 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 806 of_dma_controller_free(np); 807 dma_async_device_unregister(&fsl_edma->dma_dev); 808 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); 809 } 810 811 static int fsl_edma_suspend_late(struct device *dev) 812 { 813 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 814 struct fsl_edma_chan *fsl_chan; 815 unsigned long flags; 816 int i; 817 818 for (i = 0; i < fsl_edma->n_chans; i++) { 819 fsl_chan = &fsl_edma->chans[i]; 820 if (fsl_edma->chan_masked & BIT(i)) 821 continue; 822 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 823 /* Make sure chan is idle or will force disable. */ 824 if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) { 825 dev_warn(dev, "WARN: There is non-idle channel."); 826 fsl_edma_disable_request(fsl_chan); 827 fsl_edma_chan_mux(fsl_chan, 0, false); 828 } 829 830 fsl_chan->pm_state = SUSPENDED; 831 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 832 } 833 834 return 0; 835 } 836 837 static int fsl_edma_resume_early(struct device *dev) 838 { 839 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 840 struct fsl_edma_chan *fsl_chan; 841 struct edma_regs *regs = &fsl_edma->regs; 842 int i; 843 844 for (i = 0; i < fsl_edma->n_chans; i++) { 845 fsl_chan = &fsl_edma->chans[i]; 846 if (fsl_edma->chan_masked & BIT(i)) 847 continue; 848 fsl_chan->pm_state = RUNNING; 849 edma_write_tcdreg(fsl_chan, 0, csr); 850 if (fsl_chan->srcid != 0) 851 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true); 852 } 853 854 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 855 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 856 857 return 0; 858 } 859 860 /* 861 * eDMA provides the service to others, so it should be suspend late 862 * and resume early. When eDMA suspend, all of the clients should stop 863 * the DMA data transmission and let the channel idle. 864 */ 865 static const struct dev_pm_ops fsl_edma_pm_ops = { 866 .suspend_late = fsl_edma_suspend_late, 867 .resume_early = fsl_edma_resume_early, 868 }; 869 870 static struct platform_driver fsl_edma_driver = { 871 .driver = { 872 .name = "fsl-edma", 873 .of_match_table = fsl_edma_dt_ids, 874 .pm = &fsl_edma_pm_ops, 875 }, 876 .probe = fsl_edma_probe, 877 .remove = fsl_edma_remove, 878 }; 879 880 static int __init fsl_edma_init(void) 881 { 882 return platform_driver_register(&fsl_edma_driver); 883 } 884 subsys_initcall(fsl_edma_init); 885 886 static void __exit fsl_edma_exit(void) 887 { 888 platform_driver_unregister(&fsl_edma_driver); 889 } 890 module_exit(fsl_edma_exit); 891 892 MODULE_ALIAS("platform:fsl-edma"); 893 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 894 MODULE_LICENSE("GPL v2"); 895