1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * Copyright 2024 NXP 7 * 8 * Driver for the Freescale eDMA engine with flexible channel multiplexing 9 * capability for DMA request sources. The eDMA block can be found on some 10 * Vybrid, Layerscape and S32G SoCs. 11 */ 12 13 #include <dt-bindings/dma/fsl-edma.h> 14 #include <linux/bitfield.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_dma.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/pm_domain.h> 23 #include <linux/property.h> 24 25 #include "fsl-edma-common.h" 26 27 static void fsl_edma_synchronize(struct dma_chan *chan) 28 { 29 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 30 31 vchan_synchronize(&fsl_chan->vchan); 32 } 33 34 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 35 { 36 struct fsl_edma_engine *fsl_edma = dev_id; 37 unsigned int intr, ch; 38 struct edma_regs *regs = &fsl_edma->regs; 39 40 intr = edma_readl(fsl_edma, regs->intl); 41 if (!intr) 42 return IRQ_NONE; 43 44 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 45 if (intr & (0x1 << ch)) { 46 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 47 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 48 } 49 } 50 return IRQ_HANDLED; 51 } 52 53 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 54 { 55 struct fsl_edma_chan *fsl_chan = dev_id; 56 unsigned int intr; 57 58 intr = edma_readl_chreg(fsl_chan, ch_int); 59 if (!intr) 60 return IRQ_HANDLED; 61 62 edma_writel_chreg(fsl_chan, 1, ch_int); 63 64 fsl_edma_tx_chan_handler(fsl_chan); 65 66 return IRQ_HANDLED; 67 } 68 69 static irqreturn_t fsl_edma2_tx_handler(int irq, void *devi_id) 70 { 71 struct fsl_edma_chan *fsl_chan = devi_id; 72 73 return fsl_edma_tx_handler(irq, fsl_chan->edma); 74 } 75 76 static irqreturn_t fsl_edma3_or_tx_handler(int irq, void *dev_id, 77 u8 start, u8 end) 78 { 79 struct fsl_edma_engine *fsl_edma = dev_id; 80 struct fsl_edma_chan *chan; 81 int i; 82 83 end = min(end, fsl_edma->n_chans); 84 85 for (i = start; i < end; i++) { 86 chan = &fsl_edma->chans[i]; 87 88 fsl_edma3_tx_handler(irq, chan); 89 } 90 91 return IRQ_HANDLED; 92 } 93 94 static irqreturn_t fsl_edma3_tx_0_15_handler(int irq, void *dev_id) 95 { 96 return fsl_edma3_or_tx_handler(irq, dev_id, 0, 16); 97 } 98 99 static irqreturn_t fsl_edma3_tx_16_31_handler(int irq, void *dev_id) 100 { 101 return fsl_edma3_or_tx_handler(irq, dev_id, 16, 32); 102 } 103 104 static irqreturn_t fsl_edma3_or_err_handler(int irq, void *dev_id) 105 { 106 struct fsl_edma_engine *fsl_edma = dev_id; 107 struct edma_regs *regs = &fsl_edma->regs; 108 unsigned int err, ch, ch_es; 109 struct fsl_edma_chan *chan; 110 111 err = edma_readl(fsl_edma, regs->es); 112 if (!(err & EDMA_V3_MP_ES_VLD)) 113 return IRQ_NONE; 114 115 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 116 chan = &fsl_edma->chans[ch]; 117 118 ch_es = edma_readl_chreg(chan, ch_es); 119 if (!(ch_es & EDMA_V3_CH_ES_ERR)) 120 continue; 121 122 edma_writel_chreg(chan, EDMA_V3_CH_ES_ERR, ch_es); 123 fsl_edma_disable_request(chan); 124 fsl_edma->chans[ch].status = DMA_ERROR; 125 } 126 127 return IRQ_HANDLED; 128 } 129 130 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 131 { 132 struct fsl_edma_engine *fsl_edma = dev_id; 133 unsigned int err, ch; 134 struct edma_regs *regs = &fsl_edma->regs; 135 136 err = edma_readl(fsl_edma, regs->errl); 137 if (!err) 138 return IRQ_NONE; 139 140 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 141 if (err & (0x1 << ch)) { 142 fsl_edma_disable_request(&fsl_edma->chans[ch]); 143 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 144 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 145 } 146 } 147 return IRQ_HANDLED; 148 } 149 150 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 151 { 152 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 153 return IRQ_HANDLED; 154 155 return fsl_edma_err_handler(irq, dev_id); 156 } 157 158 static bool fsl_edma_srcid_in_use(struct fsl_edma_engine *fsl_edma, u32 srcid) 159 { 160 struct fsl_edma_chan *fsl_chan; 161 int i; 162 163 for (i = 0; i < fsl_edma->n_chans; i++) { 164 fsl_chan = &fsl_edma->chans[i]; 165 166 if (fsl_chan->srcid && srcid == fsl_chan->srcid) { 167 dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!\n"); 168 return true; 169 } 170 } 171 return false; 172 } 173 174 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 175 struct of_dma *ofdma) 176 { 177 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 178 struct dma_chan *chan, *_chan; 179 struct fsl_edma_chan *fsl_chan; 180 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 181 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 182 183 if (dma_spec->args_count != 2) 184 return NULL; 185 186 guard(mutex)(&fsl_edma->fsl_edma_mutex); 187 188 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 189 if (chan->client_count) 190 continue; 191 192 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[1])) 193 return NULL; 194 195 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 196 chan = dma_get_slave_channel(chan); 197 if (chan) { 198 chan->device->privatecnt++; 199 fsl_chan = to_fsl_edma_chan(chan); 200 fsl_chan->srcid = dma_spec->args[1]; 201 202 if (!fsl_chan->srcid) { 203 dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n", 204 fsl_chan->srcid); 205 return NULL; 206 } 207 208 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, 209 true); 210 return chan; 211 } 212 } 213 } 214 return NULL; 215 } 216 217 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 218 struct of_dma *ofdma) 219 { 220 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 221 struct dma_chan *chan, *_chan; 222 struct fsl_edma_chan *fsl_chan; 223 bool b_chmux; 224 int i; 225 226 if (dma_spec->args_count != 3) 227 return NULL; 228 229 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 230 231 guard(mutex)(&fsl_edma->fsl_edma_mutex); 232 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 233 device_node) { 234 235 if (chan->client_count) 236 continue; 237 238 fsl_chan = to_fsl_edma_chan(chan); 239 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[0])) 240 return NULL; 241 i = fsl_chan - fsl_edma->chans; 242 243 fsl_chan->priority = dma_spec->args[1]; 244 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; 245 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; 246 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; 247 248 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) 249 continue; 250 251 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) 252 continue; 253 254 if (!b_chmux && i == dma_spec->args[0]) { 255 chan = dma_get_slave_channel(chan); 256 chan->device->privatecnt++; 257 return chan; 258 } else if (b_chmux && !fsl_chan->srcid) { 259 /* if controller support channel mux, choose a free channel */ 260 chan = dma_get_slave_channel(chan); 261 chan->device->privatecnt++; 262 fsl_chan->srcid = dma_spec->args[0]; 263 return chan; 264 } 265 } 266 return NULL; 267 } 268 269 static int 270 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 271 { 272 int ret; 273 274 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 275 276 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 277 if (fsl_edma->txirq < 0) 278 return fsl_edma->txirq; 279 280 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 281 if (fsl_edma->errirq < 0) 282 return fsl_edma->errirq; 283 284 if (fsl_edma->txirq == fsl_edma->errirq) { 285 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 286 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 287 if (ret) { 288 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 289 return ret; 290 } 291 } else { 292 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 293 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 294 if (ret) { 295 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 296 return ret; 297 } 298 299 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 300 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 301 if (ret) { 302 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 303 return ret; 304 } 305 } 306 307 return 0; 308 } 309 310 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 311 { 312 int i; 313 314 for (i = 0; i < fsl_edma->n_chans; i++) { 315 316 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 317 318 if (fsl_edma->chan_masked & BIT(i)) 319 continue; 320 321 /* request channel irq */ 322 fsl_chan->txirq = platform_get_irq(pdev, i); 323 if (fsl_chan->txirq < 0) 324 return -EINVAL; 325 326 fsl_chan->irq_handler = fsl_edma3_tx_handler; 327 } 328 329 return 0; 330 } 331 332 static int fsl_edma3_or_irq_init(struct platform_device *pdev, 333 struct fsl_edma_engine *fsl_edma) 334 { 335 int ret; 336 337 fsl_edma->txirq = platform_get_irq_byname(pdev, "tx-0-15"); 338 if (fsl_edma->txirq < 0) 339 return fsl_edma->txirq; 340 341 fsl_edma->txirq_16_31 = platform_get_irq_byname(pdev, "tx-16-31"); 342 if (fsl_edma->txirq_16_31 < 0) 343 return fsl_edma->txirq_16_31; 344 345 fsl_edma->errirq = platform_get_irq_byname(pdev, "err"); 346 if (fsl_edma->errirq < 0) 347 return fsl_edma->errirq; 348 349 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 350 fsl_edma3_tx_0_15_handler, 0, "eDMA tx0_15", 351 fsl_edma); 352 if (ret) 353 return dev_err_probe(&pdev->dev, ret, 354 "Can't register eDMA tx0_15 IRQ.\n"); 355 356 if (fsl_edma->n_chans > 16) { 357 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq_16_31, 358 fsl_edma3_tx_16_31_handler, 0, 359 "eDMA tx16_31", fsl_edma); 360 if (ret) 361 return dev_err_probe(&pdev->dev, ret, 362 "Can't register eDMA tx16_31 IRQ.\n"); 363 } 364 365 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 366 fsl_edma3_or_err_handler, 0, "eDMA err", 367 fsl_edma); 368 if (ret) 369 return dev_err_probe(&pdev->dev, ret, 370 "Can't register eDMA err IRQ.\n"); 371 372 return 0; 373 } 374 375 static int 376 fsl_edma2_irq_init(struct platform_device *pdev, 377 struct fsl_edma_engine *fsl_edma) 378 { 379 int i, ret, irq; 380 int count; 381 382 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 383 384 count = platform_irq_count(pdev); 385 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 386 if (count <= 2) { 387 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 388 return -EINVAL; 389 } 390 /* 391 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 392 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 393 * For now, just simply request irq without IRQF_SHARED flag, since 16 394 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 395 */ 396 for (i = 0; i < count; i++) { 397 irq = platform_get_irq(pdev, i); 398 ret = 0; 399 if (irq < 0) 400 return -ENXIO; 401 402 /* The last IRQ is for eDMA err */ 403 if (i == count - 1) { 404 fsl_edma->errirq = irq; 405 ret = devm_request_irq(&pdev->dev, irq, 406 fsl_edma_err_handler, 407 0, "eDMA2-ERR", fsl_edma); 408 } else { 409 fsl_edma->chans[i].txirq = irq; 410 fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler; 411 } 412 413 if (ret) 414 return ret; 415 } 416 417 return 0; 418 } 419 420 static void fsl_edma_irq_exit( 421 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 422 { 423 if (fsl_edma->txirq == fsl_edma->errirq) { 424 if (fsl_edma->txirq >= 0) 425 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 426 } else { 427 if (fsl_edma->txirq >= 0) 428 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 429 if (fsl_edma->errirq >= 0) 430 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 431 } 432 } 433 434 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 435 { 436 int i; 437 438 for (i = 0; i < nr_clocks; i++) 439 clk_disable_unprepare(fsl_edma->muxclk[i]); 440 } 441 442 static struct fsl_edma_drvdata vf610_data = { 443 .dmamuxs = DMAMUX_NR, 444 .flags = FSL_EDMA_DRV_WRAP_IO, 445 .chreg_off = EDMA_TCD, 446 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 447 .setup_irq = fsl_edma_irq_init, 448 }; 449 450 static struct fsl_edma_drvdata ls1028a_data = { 451 .dmamuxs = DMAMUX_NR, 452 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 453 .chreg_off = EDMA_TCD, 454 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 455 .setup_irq = fsl_edma_irq_init, 456 }; 457 458 static struct fsl_edma_drvdata imx7ulp_data = { 459 .dmamuxs = 1, 460 .chreg_off = EDMA_TCD, 461 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 462 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 463 .setup_irq = fsl_edma2_irq_init, 464 }; 465 466 static struct fsl_edma_drvdata imx8qm_data = { 467 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE, 468 .chreg_space_sz = 0x10000, 469 .chreg_off = 0x10000, 470 .setup_irq = fsl_edma3_irq_init, 471 }; 472 473 static struct fsl_edma_drvdata imx8ulp_data = { 474 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK | 475 FSL_EDMA_DRV_EDMA3, 476 .chreg_space_sz = 0x10000, 477 .chreg_off = 0x10000, 478 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 479 .mux_skip = 0x10000, 480 .setup_irq = fsl_edma3_irq_init, 481 }; 482 483 static struct fsl_edma_drvdata imx93_data3 = { 484 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 485 .chreg_space_sz = 0x10000, 486 .chreg_off = 0x10000, 487 .setup_irq = fsl_edma3_irq_init, 488 }; 489 490 static struct fsl_edma_drvdata imx93_data4 = { 491 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, 492 .chreg_space_sz = 0x8000, 493 .chreg_off = 0x10000, 494 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 495 .mux_skip = 0x8000, 496 .setup_irq = fsl_edma3_irq_init, 497 }; 498 499 static struct fsl_edma_drvdata imx95_data5 = { 500 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 | 501 FSL_EDMA_DRV_TCD64, 502 .chreg_space_sz = 0x8000, 503 .chreg_off = 0x10000, 504 .mux_off = 0x200, 505 .mux_skip = sizeof(u32), 506 .setup_irq = fsl_edma3_irq_init, 507 }; 508 509 static const struct fsl_edma_drvdata s32g2_data = { 510 .dmamuxs = DMAMUX_NR, 511 .chreg_space_sz = EDMA_TCD, 512 .chreg_off = 0x4000, 513 .flags = FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MUX_SWAP, 514 .setup_irq = fsl_edma3_or_irq_init, 515 }; 516 517 static const struct of_device_id fsl_edma_dt_ids[] = { 518 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 519 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 520 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 521 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 522 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data}, 523 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 524 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 525 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5}, 526 { .compatible = "nxp,s32g2-edma", .data = &s32g2_data}, 527 { /* sentinel */ } 528 }; 529 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 530 531 static void fsl_edma3_detach_pd(struct fsl_edma_engine *fsl_edma) 532 { 533 struct fsl_edma_chan *fsl_chan; 534 int i; 535 536 for (i = 0; i < fsl_edma->n_chans; i++) { 537 if (fsl_edma->chan_masked & BIT(i)) 538 continue; 539 fsl_chan = &fsl_edma->chans[i]; 540 if (fsl_chan->pd_dev_link) 541 device_link_del(fsl_chan->pd_dev_link); 542 if (fsl_chan->pd_dev) { 543 dev_pm_domain_detach(fsl_chan->pd_dev, false); 544 pm_runtime_dont_use_autosuspend(fsl_chan->pd_dev); 545 pm_runtime_set_suspended(fsl_chan->pd_dev); 546 } 547 } 548 } 549 550 static void devm_fsl_edma3_detach_pd(void *data) 551 { 552 fsl_edma3_detach_pd(data); 553 } 554 555 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 556 { 557 struct fsl_edma_chan *fsl_chan; 558 struct device *pd_chan; 559 struct device *dev; 560 int i; 561 562 dev = &pdev->dev; 563 564 for (i = 0; i < fsl_edma->n_chans; i++) { 565 if (fsl_edma->chan_masked & BIT(i)) 566 continue; 567 568 fsl_chan = &fsl_edma->chans[i]; 569 570 pd_chan = dev_pm_domain_attach_by_id(dev, i); 571 if (IS_ERR_OR_NULL(pd_chan)) { 572 dev_err(dev, "Failed attach pd %d\n", i); 573 goto detach; 574 } 575 576 fsl_chan->pd_dev_link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 577 DL_FLAG_PM_RUNTIME | 578 DL_FLAG_RPM_ACTIVE); 579 if (!fsl_chan->pd_dev_link) { 580 dev_err(dev, "Failed to add device_link to %d\n", i); 581 dev_pm_domain_detach(pd_chan, false); 582 goto detach; 583 } 584 585 fsl_chan->pd_dev = pd_chan; 586 587 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 588 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 589 pm_runtime_set_active(fsl_chan->pd_dev); 590 } 591 592 return 0; 593 594 detach: 595 fsl_edma3_detach_pd(fsl_edma); 596 return -EINVAL; 597 } 598 599 static int fsl_edma_probe(struct platform_device *pdev) 600 { 601 struct device_node *np = pdev->dev.of_node; 602 struct fsl_edma_engine *fsl_edma; 603 const struct fsl_edma_drvdata *drvdata = NULL; 604 u32 chan_mask[2] = {0, 0}; 605 char clk_name[36]; 606 struct edma_regs *regs; 607 int chans; 608 int ret, i; 609 610 drvdata = device_get_match_data(&pdev->dev); 611 if (!drvdata) { 612 dev_err(&pdev->dev, "unable to find driver data\n"); 613 return -EINVAL; 614 } 615 616 ret = of_property_read_u32(np, "dma-channels", &chans); 617 if (ret) { 618 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 619 return ret; 620 } 621 622 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 623 GFP_KERNEL); 624 if (!fsl_edma) 625 return -ENOMEM; 626 627 fsl_edma->errirq = -EINVAL; 628 fsl_edma->txirq = -EINVAL; 629 fsl_edma->drvdata = drvdata; 630 fsl_edma->n_chans = chans; 631 mutex_init(&fsl_edma->fsl_edma_mutex); 632 633 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 634 if (IS_ERR(fsl_edma->membase)) 635 return PTR_ERR(fsl_edma->membase); 636 637 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 638 fsl_edma_setup_regs(fsl_edma); 639 regs = &fsl_edma->regs; 640 } 641 642 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 643 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 644 if (IS_ERR(fsl_edma->dmaclk)) { 645 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 646 return PTR_ERR(fsl_edma->dmaclk); 647 } 648 } 649 650 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 651 652 if (ret > 0) { 653 fsl_edma->chan_masked = chan_mask[1]; 654 fsl_edma->chan_masked <<= 32; 655 fsl_edma->chan_masked |= chan_mask[0]; 656 } 657 658 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 659 char clkname[32]; 660 661 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 662 1 + i); 663 if (IS_ERR(fsl_edma->muxbase[i])) { 664 /* on error: disable all previously enabled clks */ 665 fsl_disable_clocks(fsl_edma, i); 666 return PTR_ERR(fsl_edma->muxbase[i]); 667 } 668 669 sprintf(clkname, "dmamux%d", i); 670 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 671 if (IS_ERR(fsl_edma->muxclk[i])) { 672 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 673 /* on error: disable all previously enabled clks */ 674 return PTR_ERR(fsl_edma->muxclk[i]); 675 } 676 } 677 678 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 679 680 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 681 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 682 if (ret) 683 return ret; 684 ret = devm_add_action_or_reset(&pdev->dev, devm_fsl_edma3_detach_pd, fsl_edma); 685 if (ret) 686 return ret; 687 } 688 689 if (drvdata->flags & FSL_EDMA_DRV_TCD64) 690 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 691 692 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 693 for (i = 0; i < fsl_edma->n_chans; i++) { 694 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 695 int len; 696 697 if (fsl_edma->chan_masked & BIT(i)) 698 continue; 699 700 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 701 dev_name(&pdev->dev), i); 702 703 fsl_chan->edma = fsl_edma; 704 fsl_chan->pm_state = RUNNING; 705 fsl_chan->srcid = 0; 706 fsl_chan->dma_dir = DMA_NONE; 707 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 708 709 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 710 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 711 fsl_chan->tcd = fsl_edma->membase 712 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 713 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; 714 715 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 716 snprintf(clk_name, sizeof(clk_name), "ch%02d", i); 717 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, 718 (const char *)clk_name); 719 720 if (IS_ERR(fsl_chan->clk)) 721 return PTR_ERR(fsl_chan->clk); 722 } 723 fsl_chan->pdev = pdev; 724 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 725 726 edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr); 727 fsl_edma_chan_mux(fsl_chan, 0, false); 728 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) 729 clk_disable_unprepare(fsl_chan->clk); 730 } 731 732 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 733 if (ret) 734 return ret; 735 736 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 737 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 738 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 739 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 740 741 fsl_edma->dma_dev.dev = &pdev->dev; 742 fsl_edma->dma_dev.device_alloc_chan_resources 743 = fsl_edma_alloc_chan_resources; 744 fsl_edma->dma_dev.device_free_chan_resources 745 = fsl_edma_free_chan_resources; 746 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 747 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 748 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 749 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 750 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 751 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 752 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 753 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 754 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 755 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 756 757 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 758 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 759 760 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 761 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 762 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 763 } 764 765 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 766 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 767 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 768 769 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 770 DMAENGINE_ALIGN_64_BYTES : 771 DMAENGINE_ALIGN_32_BYTES; 772 773 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 774 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 775 FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK)); 776 777 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 778 779 platform_set_drvdata(pdev, fsl_edma); 780 781 ret = dma_async_device_register(&fsl_edma->dma_dev); 782 if (ret) { 783 dev_err(&pdev->dev, 784 "Can't register Freescale eDMA engine. (%d)\n", ret); 785 return ret; 786 } 787 788 ret = of_dma_controller_register(np, 789 drvdata->dmamuxs ? fsl_edma_xlate : fsl_edma3_xlate, 790 fsl_edma); 791 if (ret) { 792 dev_err(&pdev->dev, 793 "Can't register Freescale eDMA of_dma. (%d)\n", ret); 794 dma_async_device_unregister(&fsl_edma->dma_dev); 795 return ret; 796 } 797 798 /* enable round robin arbitration */ 799 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 800 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 801 802 return 0; 803 } 804 805 static void fsl_edma_remove(struct platform_device *pdev) 806 { 807 struct device_node *np = pdev->dev.of_node; 808 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 809 810 fsl_edma_irq_exit(pdev, fsl_edma); 811 of_dma_controller_free(np); 812 dma_async_device_unregister(&fsl_edma->dma_dev); 813 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 814 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); 815 } 816 817 static int fsl_edma_suspend_late(struct device *dev) 818 { 819 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 820 struct fsl_edma_chan *fsl_chan; 821 unsigned long flags; 822 int i; 823 824 for (i = 0; i < fsl_edma->n_chans; i++) { 825 fsl_chan = &fsl_edma->chans[i]; 826 if (fsl_edma->chan_masked & BIT(i)) 827 continue; 828 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 829 /* Make sure chan is idle or will force disable. */ 830 if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) { 831 dev_warn(dev, "WARN: There is non-idle channel.\n"); 832 fsl_edma_disable_request(fsl_chan); 833 fsl_edma_chan_mux(fsl_chan, 0, false); 834 } 835 836 fsl_chan->pm_state = SUSPENDED; 837 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 838 } 839 840 return 0; 841 } 842 843 static int fsl_edma_resume_early(struct device *dev) 844 { 845 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 846 struct fsl_edma_chan *fsl_chan; 847 struct edma_regs *regs = &fsl_edma->regs; 848 int i; 849 850 for (i = 0; i < fsl_edma->n_chans; i++) { 851 fsl_chan = &fsl_edma->chans[i]; 852 if (fsl_edma->chan_masked & BIT(i)) 853 continue; 854 fsl_chan->pm_state = RUNNING; 855 edma_write_tcdreg(fsl_chan, 0, csr); 856 if (fsl_chan->srcid != 0) 857 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true); 858 } 859 860 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 861 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 862 863 return 0; 864 } 865 866 /* 867 * eDMA provides the service to others, so it should be suspend late 868 * and resume early. When eDMA suspend, all of the clients should stop 869 * the DMA data transmission and let the channel idle. 870 */ 871 static const struct dev_pm_ops fsl_edma_pm_ops = { 872 .suspend_late = fsl_edma_suspend_late, 873 .resume_early = fsl_edma_resume_early, 874 }; 875 876 static struct platform_driver fsl_edma_driver = { 877 .driver = { 878 .name = "fsl-edma", 879 .of_match_table = fsl_edma_dt_ids, 880 .pm = &fsl_edma_pm_ops, 881 }, 882 .probe = fsl_edma_probe, 883 .remove = fsl_edma_remove, 884 }; 885 886 static int __init fsl_edma_init(void) 887 { 888 return platform_driver_register(&fsl_edma_driver); 889 } 890 subsys_initcall(fsl_edma_init); 891 892 static void __exit fsl_edma_exit(void) 893 { 894 platform_driver_unregister(&fsl_edma_driver); 895 } 896 module_exit(fsl_edma_exit); 897 898 MODULE_ALIAS("platform:fsl-edma"); 899 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 900 MODULE_LICENSE("GPL v2"); 901