1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * 7 * Driver for the Freescale eDMA engine with flexible channel multiplexing 8 * capability for DMA request sources. The eDMA block can be found on some 9 * Vybrid and Layerscape SoCs. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/clk.h> 15 #include <linux/of.h> 16 #include <linux/of_dma.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/pm_domain.h> 20 #include <linux/property.h> 21 22 #include "fsl-edma-common.h" 23 24 #define ARGS_RX BIT(0) 25 #define ARGS_REMOTE BIT(1) 26 #define ARGS_MULTI_FIFO BIT(2) 27 28 static void fsl_edma_synchronize(struct dma_chan *chan) 29 { 30 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 31 32 vchan_synchronize(&fsl_chan->vchan); 33 } 34 35 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 36 { 37 struct fsl_edma_engine *fsl_edma = dev_id; 38 unsigned int intr, ch; 39 struct edma_regs *regs = &fsl_edma->regs; 40 41 intr = edma_readl(fsl_edma, regs->intl); 42 if (!intr) 43 return IRQ_NONE; 44 45 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 46 if (intr & (0x1 << ch)) { 47 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 48 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 49 } 50 } 51 return IRQ_HANDLED; 52 } 53 54 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 55 { 56 struct fsl_edma_chan *fsl_chan = dev_id; 57 unsigned int intr; 58 59 intr = edma_readl_chreg(fsl_chan, ch_int); 60 if (!intr) 61 return IRQ_HANDLED; 62 63 edma_writel_chreg(fsl_chan, 1, ch_int); 64 65 fsl_edma_tx_chan_handler(fsl_chan); 66 67 return IRQ_HANDLED; 68 } 69 70 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 71 { 72 struct fsl_edma_engine *fsl_edma = dev_id; 73 unsigned int err, ch; 74 struct edma_regs *regs = &fsl_edma->regs; 75 76 err = edma_readl(fsl_edma, regs->errl); 77 if (!err) 78 return IRQ_NONE; 79 80 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 81 if (err & (0x1 << ch)) { 82 fsl_edma_disable_request(&fsl_edma->chans[ch]); 83 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 84 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 85 } 86 } 87 return IRQ_HANDLED; 88 } 89 90 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 91 { 92 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 93 return IRQ_HANDLED; 94 95 return fsl_edma_err_handler(irq, dev_id); 96 } 97 98 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 99 struct of_dma *ofdma) 100 { 101 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 102 struct dma_chan *chan, *_chan; 103 struct fsl_edma_chan *fsl_chan; 104 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 105 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 106 107 if (dma_spec->args_count != 2) 108 return NULL; 109 110 mutex_lock(&fsl_edma->fsl_edma_mutex); 111 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 112 if (chan->client_count) 113 continue; 114 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 115 chan = dma_get_slave_channel(chan); 116 if (chan) { 117 chan->device->privatecnt++; 118 fsl_chan = to_fsl_edma_chan(chan); 119 fsl_chan->slave_id = dma_spec->args[1]; 120 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, 121 true); 122 mutex_unlock(&fsl_edma->fsl_edma_mutex); 123 return chan; 124 } 125 } 126 } 127 mutex_unlock(&fsl_edma->fsl_edma_mutex); 128 return NULL; 129 } 130 131 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 132 struct of_dma *ofdma) 133 { 134 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 135 struct dma_chan *chan, *_chan; 136 struct fsl_edma_chan *fsl_chan; 137 bool b_chmux; 138 int i; 139 140 if (dma_spec->args_count != 3) 141 return NULL; 142 143 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 144 145 mutex_lock(&fsl_edma->fsl_edma_mutex); 146 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 147 device_node) { 148 149 if (chan->client_count) 150 continue; 151 152 fsl_chan = to_fsl_edma_chan(chan); 153 i = fsl_chan - fsl_edma->chans; 154 155 fsl_chan->priority = dma_spec->args[1]; 156 fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; 157 fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; 158 fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; 159 160 if (!b_chmux && i == dma_spec->args[0]) { 161 chan = dma_get_slave_channel(chan); 162 chan->device->privatecnt++; 163 mutex_unlock(&fsl_edma->fsl_edma_mutex); 164 return chan; 165 } else if (b_chmux && !fsl_chan->srcid) { 166 /* if controller support channel mux, choose a free channel */ 167 chan = dma_get_slave_channel(chan); 168 chan->device->privatecnt++; 169 fsl_chan->srcid = dma_spec->args[0]; 170 mutex_unlock(&fsl_edma->fsl_edma_mutex); 171 return chan; 172 } 173 } 174 mutex_unlock(&fsl_edma->fsl_edma_mutex); 175 return NULL; 176 } 177 178 static int 179 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 180 { 181 int ret; 182 183 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 184 185 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 186 if (fsl_edma->txirq < 0) 187 return fsl_edma->txirq; 188 189 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 190 if (fsl_edma->errirq < 0) 191 return fsl_edma->errirq; 192 193 if (fsl_edma->txirq == fsl_edma->errirq) { 194 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 195 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 196 if (ret) { 197 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 198 return ret; 199 } 200 } else { 201 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 202 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 203 if (ret) { 204 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 205 return ret; 206 } 207 208 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 209 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 210 if (ret) { 211 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 212 return ret; 213 } 214 } 215 216 return 0; 217 } 218 219 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 220 { 221 int ret; 222 int i; 223 224 for (i = 0; i < fsl_edma->n_chans; i++) { 225 226 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 227 228 if (fsl_edma->chan_masked & BIT(i)) 229 continue; 230 231 /* request channel irq */ 232 fsl_chan->txirq = platform_get_irq(pdev, i); 233 if (fsl_chan->txirq < 0) 234 return -EINVAL; 235 236 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, 237 fsl_edma3_tx_handler, IRQF_SHARED, 238 fsl_chan->chan_name, fsl_chan); 239 if (ret) { 240 dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i); 241 return -EINVAL; 242 } 243 } 244 245 return 0; 246 } 247 248 static int 249 fsl_edma2_irq_init(struct platform_device *pdev, 250 struct fsl_edma_engine *fsl_edma) 251 { 252 int i, ret, irq; 253 int count; 254 255 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 256 257 count = platform_irq_count(pdev); 258 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 259 if (count <= 2) { 260 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 261 return -EINVAL; 262 } 263 /* 264 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 265 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 266 * For now, just simply request irq without IRQF_SHARED flag, since 16 267 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 268 */ 269 for (i = 0; i < count; i++) { 270 irq = platform_get_irq(pdev, i); 271 if (irq < 0) 272 return -ENXIO; 273 274 /* The last IRQ is for eDMA err */ 275 if (i == count - 1) 276 ret = devm_request_irq(&pdev->dev, irq, 277 fsl_edma_err_handler, 278 0, "eDMA2-ERR", fsl_edma); 279 else 280 ret = devm_request_irq(&pdev->dev, irq, 281 fsl_edma_tx_handler, 0, 282 fsl_edma->chans[i].chan_name, 283 fsl_edma); 284 if (ret) 285 return ret; 286 } 287 288 return 0; 289 } 290 291 static void fsl_edma_irq_exit( 292 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 293 { 294 if (fsl_edma->txirq == fsl_edma->errirq) { 295 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 296 } else { 297 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 298 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 299 } 300 } 301 302 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 303 { 304 int i; 305 306 for (i = 0; i < nr_clocks; i++) 307 clk_disable_unprepare(fsl_edma->muxclk[i]); 308 } 309 310 static struct fsl_edma_drvdata vf610_data = { 311 .dmamuxs = DMAMUX_NR, 312 .flags = FSL_EDMA_DRV_WRAP_IO, 313 .chreg_off = EDMA_TCD, 314 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 315 .setup_irq = fsl_edma_irq_init, 316 }; 317 318 static struct fsl_edma_drvdata ls1028a_data = { 319 .dmamuxs = DMAMUX_NR, 320 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 321 .chreg_off = EDMA_TCD, 322 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 323 .setup_irq = fsl_edma_irq_init, 324 }; 325 326 static struct fsl_edma_drvdata imx7ulp_data = { 327 .dmamuxs = 1, 328 .chreg_off = EDMA_TCD, 329 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 330 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 331 .setup_irq = fsl_edma2_irq_init, 332 }; 333 334 static struct fsl_edma_drvdata imx8qm_data = { 335 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 336 .chreg_space_sz = 0x10000, 337 .chreg_off = 0x10000, 338 .setup_irq = fsl_edma3_irq_init, 339 }; 340 341 static struct fsl_edma_drvdata imx8qm_audio_data = { 342 .flags = FSL_EDMA_DRV_QUIRK_SWAPPED | FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 343 .chreg_space_sz = 0x10000, 344 .chreg_off = 0x10000, 345 .setup_irq = fsl_edma3_irq_init, 346 }; 347 348 static struct fsl_edma_drvdata imx93_data3 = { 349 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 350 .chreg_space_sz = 0x10000, 351 .chreg_off = 0x10000, 352 .setup_irq = fsl_edma3_irq_init, 353 }; 354 355 static struct fsl_edma_drvdata imx93_data4 = { 356 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, 357 .chreg_space_sz = 0x8000, 358 .chreg_off = 0x10000, 359 .setup_irq = fsl_edma3_irq_init, 360 }; 361 362 static const struct of_device_id fsl_edma_dt_ids[] = { 363 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 364 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 365 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 366 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 367 { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data}, 368 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 369 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 370 { /* sentinel */ } 371 }; 372 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 373 374 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 375 { 376 struct fsl_edma_chan *fsl_chan; 377 struct device_link *link; 378 struct device *pd_chan; 379 struct device *dev; 380 int i; 381 382 dev = &pdev->dev; 383 384 for (i = 0; i < fsl_edma->n_chans; i++) { 385 if (fsl_edma->chan_masked & BIT(i)) 386 continue; 387 388 fsl_chan = &fsl_edma->chans[i]; 389 390 pd_chan = dev_pm_domain_attach_by_id(dev, i); 391 if (IS_ERR_OR_NULL(pd_chan)) { 392 dev_err(dev, "Failed attach pd %d\n", i); 393 return -EINVAL; 394 } 395 396 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 397 DL_FLAG_PM_RUNTIME | 398 DL_FLAG_RPM_ACTIVE); 399 if (!link) { 400 dev_err(dev, "Failed to add device_link to %d\n", i); 401 return -EINVAL; 402 } 403 404 fsl_chan->pd_dev = pd_chan; 405 406 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 407 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 408 pm_runtime_set_active(fsl_chan->pd_dev); 409 } 410 411 return 0; 412 } 413 414 static int fsl_edma_probe(struct platform_device *pdev) 415 { 416 struct device_node *np = pdev->dev.of_node; 417 struct fsl_edma_engine *fsl_edma; 418 const struct fsl_edma_drvdata *drvdata = NULL; 419 u32 chan_mask[2] = {0, 0}; 420 struct edma_regs *regs; 421 int chans; 422 int ret, i; 423 424 drvdata = device_get_match_data(&pdev->dev); 425 if (!drvdata) { 426 dev_err(&pdev->dev, "unable to find driver data\n"); 427 return -EINVAL; 428 } 429 430 ret = of_property_read_u32(np, "dma-channels", &chans); 431 if (ret) { 432 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 433 return ret; 434 } 435 436 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 437 GFP_KERNEL); 438 if (!fsl_edma) 439 return -ENOMEM; 440 441 fsl_edma->drvdata = drvdata; 442 fsl_edma->n_chans = chans; 443 mutex_init(&fsl_edma->fsl_edma_mutex); 444 445 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 446 if (IS_ERR(fsl_edma->membase)) 447 return PTR_ERR(fsl_edma->membase); 448 449 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 450 fsl_edma_setup_regs(fsl_edma); 451 regs = &fsl_edma->regs; 452 } 453 454 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 455 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 456 if (IS_ERR(fsl_edma->dmaclk)) { 457 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 458 return PTR_ERR(fsl_edma->dmaclk); 459 } 460 } 461 462 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 463 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp"); 464 if (IS_ERR(fsl_edma->chclk)) { 465 dev_err(&pdev->dev, "Missing MP block clock.\n"); 466 return PTR_ERR(fsl_edma->chclk); 467 } 468 } 469 470 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 471 472 if (ret > 0) { 473 fsl_edma->chan_masked = chan_mask[1]; 474 fsl_edma->chan_masked <<= 32; 475 fsl_edma->chan_masked |= chan_mask[0]; 476 } 477 478 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 479 char clkname[32]; 480 481 /* eDMAv3 mux register move to TCD area if ch_mux exist */ 482 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) 483 break; 484 485 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 486 1 + i); 487 if (IS_ERR(fsl_edma->muxbase[i])) { 488 /* on error: disable all previously enabled clks */ 489 fsl_disable_clocks(fsl_edma, i); 490 return PTR_ERR(fsl_edma->muxbase[i]); 491 } 492 493 sprintf(clkname, "dmamux%d", i); 494 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 495 if (IS_ERR(fsl_edma->muxclk[i])) { 496 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 497 /* on error: disable all previously enabled clks */ 498 return PTR_ERR(fsl_edma->muxclk[i]); 499 } 500 } 501 502 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 503 504 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 505 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 506 if (ret) 507 return ret; 508 } 509 510 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 511 for (i = 0; i < fsl_edma->n_chans; i++) { 512 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 513 int len; 514 515 if (fsl_edma->chan_masked & BIT(i)) 516 continue; 517 518 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 519 dev_name(&pdev->dev), i); 520 521 fsl_chan->edma = fsl_edma; 522 fsl_chan->pm_state = RUNNING; 523 fsl_chan->slave_id = 0; 524 fsl_chan->idle = true; 525 fsl_chan->dma_dir = DMA_NONE; 526 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 527 528 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 529 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 530 fsl_chan->tcd = fsl_edma->membase 531 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 532 533 fsl_chan->pdev = pdev; 534 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 535 536 edma_write_tcdreg(fsl_chan, 0, csr); 537 fsl_edma_chan_mux(fsl_chan, 0, false); 538 } 539 540 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 541 if (ret) 542 return ret; 543 544 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 545 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 546 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 547 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 548 549 fsl_edma->dma_dev.dev = &pdev->dev; 550 fsl_edma->dma_dev.device_alloc_chan_resources 551 = fsl_edma_alloc_chan_resources; 552 fsl_edma->dma_dev.device_free_chan_resources 553 = fsl_edma_free_chan_resources; 554 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 555 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 556 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 557 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 558 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 559 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 560 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 561 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 562 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 563 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 564 565 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 566 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 567 568 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 569 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 570 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 571 } 572 573 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 574 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 575 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 576 577 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 578 DMAENGINE_ALIGN_64_BYTES : 579 DMAENGINE_ALIGN_32_BYTES; 580 581 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 582 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff); 583 584 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 585 586 platform_set_drvdata(pdev, fsl_edma); 587 588 ret = dma_async_device_register(&fsl_edma->dma_dev); 589 if (ret) { 590 dev_err(&pdev->dev, 591 "Can't register Freescale eDMA engine. (%d)\n", ret); 592 return ret; 593 } 594 595 ret = of_dma_controller_register(np, 596 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate, 597 fsl_edma); 598 if (ret) { 599 dev_err(&pdev->dev, 600 "Can't register Freescale eDMA of_dma. (%d)\n", ret); 601 dma_async_device_unregister(&fsl_edma->dma_dev); 602 return ret; 603 } 604 605 /* enable round robin arbitration */ 606 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 607 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 608 609 return 0; 610 } 611 612 static void fsl_edma_remove(struct platform_device *pdev) 613 { 614 struct device_node *np = pdev->dev.of_node; 615 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 616 617 fsl_edma_irq_exit(pdev, fsl_edma); 618 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 619 of_dma_controller_free(np); 620 dma_async_device_unregister(&fsl_edma->dma_dev); 621 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); 622 } 623 624 static int fsl_edma_suspend_late(struct device *dev) 625 { 626 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 627 struct fsl_edma_chan *fsl_chan; 628 unsigned long flags; 629 int i; 630 631 for (i = 0; i < fsl_edma->n_chans; i++) { 632 fsl_chan = &fsl_edma->chans[i]; 633 if (fsl_edma->chan_masked & BIT(i)) 634 continue; 635 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 636 /* Make sure chan is idle or will force disable. */ 637 if (unlikely(!fsl_chan->idle)) { 638 dev_warn(dev, "WARN: There is non-idle channel."); 639 fsl_edma_disable_request(fsl_chan); 640 fsl_edma_chan_mux(fsl_chan, 0, false); 641 } 642 643 fsl_chan->pm_state = SUSPENDED; 644 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 645 } 646 647 return 0; 648 } 649 650 static int fsl_edma_resume_early(struct device *dev) 651 { 652 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 653 struct fsl_edma_chan *fsl_chan; 654 struct edma_regs *regs = &fsl_edma->regs; 655 int i; 656 657 for (i = 0; i < fsl_edma->n_chans; i++) { 658 fsl_chan = &fsl_edma->chans[i]; 659 if (fsl_edma->chan_masked & BIT(i)) 660 continue; 661 fsl_chan->pm_state = RUNNING; 662 edma_write_tcdreg(fsl_chan, 0, csr); 663 if (fsl_chan->slave_id != 0) 664 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); 665 } 666 667 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 668 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 669 670 return 0; 671 } 672 673 /* 674 * eDMA provides the service to others, so it should be suspend late 675 * and resume early. When eDMA suspend, all of the clients should stop 676 * the DMA data transmission and let the channel idle. 677 */ 678 static const struct dev_pm_ops fsl_edma_pm_ops = { 679 .suspend_late = fsl_edma_suspend_late, 680 .resume_early = fsl_edma_resume_early, 681 }; 682 683 static struct platform_driver fsl_edma_driver = { 684 .driver = { 685 .name = "fsl-edma", 686 .of_match_table = fsl_edma_dt_ids, 687 .pm = &fsl_edma_pm_ops, 688 }, 689 .probe = fsl_edma_probe, 690 .remove_new = fsl_edma_remove, 691 }; 692 693 static int __init fsl_edma_init(void) 694 { 695 return platform_driver_register(&fsl_edma_driver); 696 } 697 subsys_initcall(fsl_edma_init); 698 699 static void __exit fsl_edma_exit(void) 700 { 701 platform_driver_unregister(&fsl_edma_driver); 702 } 703 module_exit(fsl_edma_exit); 704 705 MODULE_ALIAS("platform:fsl-edma"); 706 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 707 MODULE_LICENSE("GPL v2"); 708