1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * Copyright 2024 NXP 7 * 8 * Driver for the Freescale eDMA engine with flexible channel multiplexing 9 * capability for DMA request sources. The eDMA block can be found on some 10 * Vybrid, Layerscape and S32G SoCs. 11 */ 12 13 #include <dt-bindings/dma/fsl-edma.h> 14 #include <linux/bitfield.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_dma.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/pm_domain.h> 23 #include <linux/property.h> 24 25 #include "fsl-edma-common.h" 26 27 static void fsl_edma_synchronize(struct dma_chan *chan) 28 { 29 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 30 31 vchan_synchronize(&fsl_chan->vchan); 32 } 33 34 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 35 { 36 struct fsl_edma_engine *fsl_edma = dev_id; 37 unsigned int intr, ch; 38 struct edma_regs *regs = &fsl_edma->regs; 39 40 intr = edma_readl(fsl_edma, regs->intl); 41 if (!intr) 42 return IRQ_NONE; 43 44 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 45 if (intr & (0x1 << ch)) { 46 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 47 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 48 } 49 } 50 return IRQ_HANDLED; 51 } 52 53 static void fsl_edma3_err_check(struct fsl_edma_chan *fsl_chan) 54 { 55 unsigned int ch_err; 56 u32 val; 57 58 scoped_guard(spinlock, &fsl_chan->vchan.lock) { 59 ch_err = edma_readl_chreg(fsl_chan, ch_es); 60 if (!(ch_err & EDMA_V3_CH_ERR)) 61 return; 62 63 edma_writel_chreg(fsl_chan, EDMA_V3_CH_ERR, ch_es); 64 val = edma_readl_chreg(fsl_chan, ch_csr); 65 val &= ~EDMA_V3_CH_CSR_ERQ; 66 edma_writel_chreg(fsl_chan, val, ch_csr); 67 } 68 69 /* Ignore this interrupt since channel has been disabled already */ 70 if (!fsl_chan->edesc) 71 return; 72 73 if (ch_err & EDMA_V3_CH_ERR_DBE) 74 dev_err(&fsl_chan->pdev->dev, "Destination Bus Error interrupt.\n"); 75 76 if (ch_err & EDMA_V3_CH_ERR_SBE) 77 dev_err(&fsl_chan->pdev->dev, "Source Bus Error interrupt.\n"); 78 79 if (ch_err & EDMA_V3_CH_ERR_SGE) 80 dev_err(&fsl_chan->pdev->dev, "Scatter/Gather Configuration Error interrupt.\n"); 81 82 if (ch_err & EDMA_V3_CH_ERR_NCE) 83 dev_err(&fsl_chan->pdev->dev, "NBYTES/CITER Configuration Error interrupt.\n"); 84 85 if (ch_err & EDMA_V3_CH_ERR_DOE) 86 dev_err(&fsl_chan->pdev->dev, "Destination Offset Error interrupt.\n"); 87 88 if (ch_err & EDMA_V3_CH_ERR_DAE) 89 dev_err(&fsl_chan->pdev->dev, "Destination Address Error interrupt.\n"); 90 91 if (ch_err & EDMA_V3_CH_ERR_SOE) 92 dev_err(&fsl_chan->pdev->dev, "Source Offset Error interrupt.\n"); 93 94 if (ch_err & EDMA_V3_CH_ERR_SAE) 95 dev_err(&fsl_chan->pdev->dev, "Source Address Error interrupt.\n"); 96 97 if (ch_err & EDMA_V3_CH_ERR_ECX) 98 dev_err(&fsl_chan->pdev->dev, "Transfer Canceled interrupt.\n"); 99 100 if (ch_err & EDMA_V3_CH_ERR_UCE) 101 dev_err(&fsl_chan->pdev->dev, "Uncorrectable TCD error during channel execution interrupt.\n"); 102 103 fsl_chan->status = DMA_ERROR; 104 } 105 106 static irqreturn_t fsl_edma3_err_handler_per_chan(int irq, void *dev_id) 107 { 108 struct fsl_edma_chan *fsl_chan = dev_id; 109 110 fsl_edma3_err_check(fsl_chan); 111 112 return IRQ_HANDLED; 113 } 114 115 static irqreturn_t fsl_edma3_err_handler_shared(int irq, void *dev_id) 116 { 117 struct fsl_edma_engine *fsl_edma = dev_id; 118 unsigned int ch; 119 120 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 121 if (fsl_edma->chan_masked & BIT(ch)) 122 continue; 123 124 fsl_edma3_err_check(&fsl_edma->chans[ch]); 125 } 126 127 return IRQ_HANDLED; 128 } 129 130 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 131 { 132 struct fsl_edma_chan *fsl_chan = dev_id; 133 unsigned int intr; 134 135 intr = edma_readl_chreg(fsl_chan, ch_int); 136 if (!intr) 137 return IRQ_NONE; 138 139 edma_writel_chreg(fsl_chan, 1, ch_int); 140 141 fsl_edma_tx_chan_handler(fsl_chan); 142 143 return IRQ_HANDLED; 144 } 145 146 static irqreturn_t fsl_edma2_tx_handler(int irq, void *devi_id) 147 { 148 struct fsl_edma_chan *fsl_chan = devi_id; 149 150 return fsl_edma_tx_handler(irq, fsl_chan->edma); 151 } 152 153 static irqreturn_t fsl_edma3_or_tx_handler(int irq, void *dev_id, 154 u8 start, u8 end) 155 { 156 struct fsl_edma_engine *fsl_edma = dev_id; 157 struct fsl_edma_chan *chan; 158 int i; 159 160 end = min(end, fsl_edma->n_chans); 161 162 for (i = start; i < end; i++) { 163 chan = &fsl_edma->chans[i]; 164 165 fsl_edma3_tx_handler(irq, chan); 166 } 167 168 return IRQ_HANDLED; 169 } 170 171 static irqreturn_t fsl_edma3_tx_0_15_handler(int irq, void *dev_id) 172 { 173 return fsl_edma3_or_tx_handler(irq, dev_id, 0, 16); 174 } 175 176 static irqreturn_t fsl_edma3_tx_16_31_handler(int irq, void *dev_id) 177 { 178 return fsl_edma3_or_tx_handler(irq, dev_id, 16, 32); 179 } 180 181 static irqreturn_t fsl_edma3_or_err_handler(int irq, void *dev_id) 182 { 183 struct fsl_edma_engine *fsl_edma = dev_id; 184 struct edma_regs *regs = &fsl_edma->regs; 185 unsigned int err, ch, ch_es; 186 struct fsl_edma_chan *chan; 187 188 err = edma_readl(fsl_edma, regs->es); 189 if (!(err & EDMA_V3_MP_ES_VLD)) 190 return IRQ_NONE; 191 192 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 193 chan = &fsl_edma->chans[ch]; 194 195 ch_es = edma_readl_chreg(chan, ch_es); 196 if (!(ch_es & EDMA_V3_CH_ES_ERR)) 197 continue; 198 199 edma_writel_chreg(chan, EDMA_V3_CH_ES_ERR, ch_es); 200 fsl_edma_disable_request(chan); 201 fsl_edma->chans[ch].status = DMA_ERROR; 202 } 203 204 return IRQ_HANDLED; 205 } 206 207 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 208 { 209 struct fsl_edma_engine *fsl_edma = dev_id; 210 unsigned int err, ch; 211 struct edma_regs *regs = &fsl_edma->regs; 212 213 err = edma_readl(fsl_edma, regs->errl); 214 if (!err) 215 return IRQ_NONE; 216 217 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 218 if (err & (0x1 << ch)) { 219 fsl_edma_disable_request(&fsl_edma->chans[ch]); 220 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 221 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 222 } 223 } 224 return IRQ_HANDLED; 225 } 226 227 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 228 { 229 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 230 return IRQ_HANDLED; 231 232 return fsl_edma_err_handler(irq, dev_id); 233 } 234 235 static bool fsl_edma_srcid_in_use(struct fsl_edma_engine *fsl_edma, u32 srcid) 236 { 237 struct fsl_edma_chan *fsl_chan; 238 int i; 239 240 for (i = 0; i < fsl_edma->n_chans; i++) { 241 fsl_chan = &fsl_edma->chans[i]; 242 243 if (fsl_chan->srcid && srcid == fsl_chan->srcid) { 244 dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!\n"); 245 return true; 246 } 247 } 248 return false; 249 } 250 251 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 252 struct of_dma *ofdma) 253 { 254 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 255 struct dma_chan *chan, *_chan; 256 struct fsl_edma_chan *fsl_chan; 257 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 258 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 259 260 if (dma_spec->args_count != 2) 261 return NULL; 262 263 guard(mutex)(&fsl_edma->fsl_edma_mutex); 264 265 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 266 if (chan->client_count) 267 continue; 268 269 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[1])) 270 return NULL; 271 272 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 273 chan = dma_get_slave_channel(chan); 274 if (chan) { 275 chan->device->privatecnt++; 276 fsl_chan = to_fsl_edma_chan(chan); 277 fsl_chan->srcid = dma_spec->args[1]; 278 279 if (!fsl_chan->srcid) { 280 dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n", 281 fsl_chan->srcid); 282 return NULL; 283 } 284 285 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, 286 true); 287 return chan; 288 } 289 } 290 } 291 return NULL; 292 } 293 294 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 295 struct of_dma *ofdma) 296 { 297 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 298 struct dma_chan *chan, *_chan; 299 struct fsl_edma_chan *fsl_chan; 300 bool b_chmux; 301 int i; 302 303 if (dma_spec->args_count != 3) 304 return NULL; 305 306 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 307 308 guard(mutex)(&fsl_edma->fsl_edma_mutex); 309 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 310 device_node) { 311 312 if (chan->client_count) 313 continue; 314 315 fsl_chan = to_fsl_edma_chan(chan); 316 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[0])) 317 return NULL; 318 i = fsl_chan - fsl_edma->chans; 319 320 if (!b_chmux && i != dma_spec->args[0]) 321 continue; 322 323 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) 324 continue; 325 326 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) 327 continue; 328 329 fsl_chan->srcid = dma_spec->args[0]; 330 fsl_chan->priority = dma_spec->args[1]; 331 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; 332 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; 333 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; 334 335 chan = dma_get_slave_channel(chan); 336 chan->device->privatecnt++; 337 return chan; 338 } 339 return NULL; 340 } 341 342 static int 343 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 344 { 345 int ret; 346 347 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 348 349 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 350 if (fsl_edma->txirq < 0) 351 return fsl_edma->txirq; 352 353 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 354 if (fsl_edma->errirq < 0) 355 return fsl_edma->errirq; 356 357 if (fsl_edma->txirq == fsl_edma->errirq) { 358 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 359 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 360 if (ret) { 361 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 362 return ret; 363 } 364 } else { 365 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 366 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 367 if (ret) { 368 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 369 return ret; 370 } 371 372 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 373 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 374 if (ret) { 375 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 376 return ret; 377 } 378 } 379 380 return 0; 381 } 382 383 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 384 { 385 char *errirq_name; 386 int i, ret; 387 388 for (i = 0; i < fsl_edma->n_chans; i++) { 389 390 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 391 392 if (fsl_edma->chan_masked & BIT(i)) 393 continue; 394 395 /* request channel irq */ 396 fsl_chan->txirq = platform_get_irq(pdev, i); 397 if (fsl_chan->txirq < 0) 398 return -EINVAL; 399 400 fsl_chan->irq_handler = fsl_edma3_tx_handler; 401 402 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_ERRIRQ_SHARE)) { 403 fsl_chan->errirq = fsl_chan->txirq; 404 fsl_chan->errirq_handler = fsl_edma3_err_handler_per_chan; 405 } 406 } 407 408 /* All channel err use one irq number */ 409 if (fsl_edma->drvdata->flags & FSL_EDMA_DRV_ERRIRQ_SHARE) { 410 /* last one is error irq */ 411 fsl_edma->errirq = platform_get_irq_optional(pdev, fsl_edma->n_chans); 412 if (fsl_edma->errirq < 0) 413 return 0; /* dts miss err irq, treat as no err irq case */ 414 415 errirq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s-err", 416 dev_name(&pdev->dev)); 417 if (!errirq_name) 418 return -ENOMEM; 419 420 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, fsl_edma3_err_handler_shared, 421 0, errirq_name, fsl_edma); 422 if (ret) 423 return dev_err_probe(&pdev->dev, ret, "Can't register eDMA err IRQ.\n"); 424 } 425 426 return 0; 427 } 428 429 static int fsl_edma3_or_irq_init(struct platform_device *pdev, 430 struct fsl_edma_engine *fsl_edma) 431 { 432 int ret; 433 434 fsl_edma->txirq = platform_get_irq_byname(pdev, "tx-0-15"); 435 if (fsl_edma->txirq < 0) 436 return fsl_edma->txirq; 437 438 fsl_edma->txirq_16_31 = platform_get_irq_byname(pdev, "tx-16-31"); 439 if (fsl_edma->txirq_16_31 < 0) 440 return fsl_edma->txirq_16_31; 441 442 fsl_edma->errirq = platform_get_irq_byname(pdev, "err"); 443 if (fsl_edma->errirq < 0) 444 return fsl_edma->errirq; 445 446 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 447 fsl_edma3_tx_0_15_handler, 0, "eDMA tx0_15", 448 fsl_edma); 449 if (ret) 450 return dev_err_probe(&pdev->dev, ret, 451 "Can't register eDMA tx0_15 IRQ.\n"); 452 453 if (fsl_edma->n_chans > 16) { 454 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq_16_31, 455 fsl_edma3_tx_16_31_handler, 0, 456 "eDMA tx16_31", fsl_edma); 457 if (ret) 458 return dev_err_probe(&pdev->dev, ret, 459 "Can't register eDMA tx16_31 IRQ.\n"); 460 } 461 462 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 463 fsl_edma3_or_err_handler, 0, "eDMA err", 464 fsl_edma); 465 if (ret) 466 return dev_err_probe(&pdev->dev, ret, 467 "Can't register eDMA err IRQ.\n"); 468 469 return 0; 470 } 471 472 static int 473 fsl_edma2_irq_init(struct platform_device *pdev, 474 struct fsl_edma_engine *fsl_edma) 475 { 476 int i, ret, irq; 477 int count; 478 479 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 480 481 count = platform_irq_count(pdev); 482 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 483 if (count <= 2) { 484 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 485 return -EINVAL; 486 } 487 /* 488 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 489 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 490 * For now, just simply request irq without IRQF_SHARED flag, since 16 491 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 492 */ 493 for (i = 0; i < count; i++) { 494 irq = platform_get_irq(pdev, i); 495 ret = 0; 496 if (irq < 0) 497 return -ENXIO; 498 499 /* The last IRQ is for eDMA err */ 500 if (i == count - 1) { 501 fsl_edma->errirq = irq; 502 ret = devm_request_irq(&pdev->dev, irq, 503 fsl_edma_err_handler, 504 0, "eDMA2-ERR", fsl_edma); 505 } else { 506 fsl_edma->chans[i].txirq = irq; 507 fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler; 508 } 509 510 if (ret) 511 return ret; 512 } 513 514 return 0; 515 } 516 517 static void fsl_edma_irq_exit( 518 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 519 { 520 if (fsl_edma->txirq == fsl_edma->errirq) { 521 if (fsl_edma->txirq >= 0) 522 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 523 } else { 524 if (fsl_edma->txirq >= 0) 525 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 526 if (fsl_edma->errirq >= 0) 527 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 528 } 529 } 530 531 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 532 { 533 int i; 534 535 for (i = 0; i < nr_clocks; i++) 536 clk_disable_unprepare(fsl_edma->muxclk[i]); 537 } 538 539 static struct fsl_edma_drvdata vf610_data = { 540 .dmamuxs = DMAMUX_NR, 541 .flags = FSL_EDMA_DRV_WRAP_IO, 542 .chreg_off = EDMA_TCD, 543 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 544 .setup_irq = fsl_edma_irq_init, 545 }; 546 547 static struct fsl_edma_drvdata ls1028a_data = { 548 .dmamuxs = DMAMUX_NR, 549 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 550 .chreg_off = EDMA_TCD, 551 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 552 .setup_irq = fsl_edma_irq_init, 553 }; 554 555 static struct fsl_edma_drvdata imx7ulp_data = { 556 .dmamuxs = 1, 557 .chreg_off = EDMA_TCD, 558 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 559 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 560 .setup_irq = fsl_edma2_irq_init, 561 }; 562 563 static struct fsl_edma_drvdata imx8qm_data = { 564 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE 565 | FSL_EDMA_DRV_ERRIRQ_SHARE, 566 .chreg_space_sz = 0x10000, 567 .chreg_off = 0x10000, 568 .setup_irq = fsl_edma3_irq_init, 569 }; 570 571 static struct fsl_edma_drvdata imx8ulp_data = { 572 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK | 573 FSL_EDMA_DRV_EDMA3, 574 .chreg_space_sz = 0x10000, 575 .chreg_off = 0x10000, 576 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 577 .mux_skip = 0x10000, 578 .setup_irq = fsl_edma3_irq_init, 579 }; 580 581 static struct fsl_edma_drvdata imx93_data3 = { 582 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_ERRIRQ_SHARE, 583 .chreg_space_sz = 0x10000, 584 .chreg_off = 0x10000, 585 .setup_irq = fsl_edma3_irq_init, 586 }; 587 588 static struct fsl_edma_drvdata imx93_data4 = { 589 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 590 | FSL_EDMA_DRV_ERRIRQ_SHARE, 591 .chreg_space_sz = 0x8000, 592 .chreg_off = 0x10000, 593 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 594 .mux_skip = 0x8000, 595 .setup_irq = fsl_edma3_irq_init, 596 }; 597 598 static struct fsl_edma_drvdata imx95_data5 = { 599 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 | 600 FSL_EDMA_DRV_TCD64 | FSL_EDMA_DRV_ERRIRQ_SHARE, 601 .chreg_space_sz = 0x8000, 602 .chreg_off = 0x10000, 603 .mux_off = 0x200, 604 .mux_skip = sizeof(u32), 605 .setup_irq = fsl_edma3_irq_init, 606 }; 607 608 static const struct fsl_edma_drvdata s32g2_data = { 609 .dmamuxs = DMAMUX_NR, 610 .chreg_space_sz = EDMA_TCD, 611 .chreg_off = 0x4000, 612 .flags = FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MUX_SWAP, 613 .setup_irq = fsl_edma3_or_irq_init, 614 }; 615 616 static const struct of_device_id fsl_edma_dt_ids[] = { 617 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 618 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 619 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 620 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 621 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data}, 622 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 623 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 624 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5}, 625 { .compatible = "nxp,s32g2-edma", .data = &s32g2_data}, 626 { /* sentinel */ } 627 }; 628 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 629 630 static void fsl_edma3_detach_pd(struct fsl_edma_engine *fsl_edma) 631 { 632 struct fsl_edma_chan *fsl_chan; 633 int i; 634 635 for (i = 0; i < fsl_edma->n_chans; i++) { 636 if (fsl_edma->chan_masked & BIT(i)) 637 continue; 638 fsl_chan = &fsl_edma->chans[i]; 639 if (fsl_chan->pd_dev_link) 640 device_link_del(fsl_chan->pd_dev_link); 641 if (fsl_chan->pd_dev) { 642 dev_pm_domain_detach(fsl_chan->pd_dev, false); 643 pm_runtime_dont_use_autosuspend(fsl_chan->pd_dev); 644 pm_runtime_set_suspended(fsl_chan->pd_dev); 645 } 646 } 647 } 648 649 static void devm_fsl_edma3_detach_pd(void *data) 650 { 651 fsl_edma3_detach_pd(data); 652 } 653 654 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 655 { 656 struct fsl_edma_chan *fsl_chan; 657 struct device *pd_chan; 658 struct device *dev; 659 int i; 660 661 dev = &pdev->dev; 662 663 for (i = 0; i < fsl_edma->n_chans; i++) { 664 if (fsl_edma->chan_masked & BIT(i)) 665 continue; 666 667 fsl_chan = &fsl_edma->chans[i]; 668 669 pd_chan = dev_pm_domain_attach_by_id(dev, i); 670 if (IS_ERR_OR_NULL(pd_chan)) { 671 dev_err(dev, "Failed attach pd %d\n", i); 672 goto detach; 673 } 674 675 fsl_chan->pd_dev_link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 676 DL_FLAG_PM_RUNTIME | 677 DL_FLAG_RPM_ACTIVE); 678 if (!fsl_chan->pd_dev_link) { 679 dev_err(dev, "Failed to add device_link to %d\n", i); 680 dev_pm_domain_detach(pd_chan, false); 681 goto detach; 682 } 683 684 fsl_chan->pd_dev = pd_chan; 685 686 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 687 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 688 pm_runtime_set_active(fsl_chan->pd_dev); 689 } 690 691 return 0; 692 693 detach: 694 fsl_edma3_detach_pd(fsl_edma); 695 return -EINVAL; 696 } 697 698 static int fsl_edma_probe(struct platform_device *pdev) 699 { 700 struct device_node *np = pdev->dev.of_node; 701 struct fsl_edma_engine *fsl_edma; 702 const struct fsl_edma_drvdata *drvdata = NULL; 703 u32 chan_mask[2] = {0, 0}; 704 char clk_name[36]; 705 struct edma_regs *regs; 706 int chans; 707 int ret, i; 708 709 drvdata = device_get_match_data(&pdev->dev); 710 if (!drvdata) 711 return dev_err_probe(&pdev->dev, -EINVAL, 712 "unable to find driver data\n"); 713 714 ret = of_property_read_u32(np, "dma-channels", &chans); 715 if (ret) 716 return dev_err_probe(&pdev->dev, ret, 717 "Can't get dma-channels.\n"); 718 719 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 720 GFP_KERNEL); 721 if (!fsl_edma) 722 return -ENOMEM; 723 724 fsl_edma->errirq = -EINVAL; 725 fsl_edma->txirq = -EINVAL; 726 fsl_edma->drvdata = drvdata; 727 fsl_edma->n_chans = chans; 728 mutex_init(&fsl_edma->fsl_edma_mutex); 729 730 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 731 if (IS_ERR(fsl_edma->membase)) 732 return PTR_ERR(fsl_edma->membase); 733 734 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 735 fsl_edma_setup_regs(fsl_edma); 736 regs = &fsl_edma->regs; 737 } 738 739 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 740 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 741 if (IS_ERR(fsl_edma->dmaclk)) 742 return dev_err_probe(&pdev->dev, 743 PTR_ERR(fsl_edma->dmaclk), 744 "Missing DMA block clock.\n"); 745 } 746 747 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 748 749 if (ret > 0) { 750 fsl_edma->chan_masked = chan_mask[1]; 751 fsl_edma->chan_masked <<= 32; 752 fsl_edma->chan_masked |= chan_mask[0]; 753 } 754 755 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 756 char clkname[32]; 757 758 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 759 1 + i); 760 if (IS_ERR(fsl_edma->muxbase[i])) { 761 /* on error: disable all previously enabled clks */ 762 fsl_disable_clocks(fsl_edma, i); 763 return PTR_ERR(fsl_edma->muxbase[i]); 764 } 765 766 sprintf(clkname, "dmamux%d", i); 767 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 768 if (IS_ERR(fsl_edma->muxclk[i])) 769 return dev_err_probe(&pdev->dev, 770 PTR_ERR(fsl_edma->muxclk[i]), 771 "Missing DMAMUX block clock.\n"); 772 } 773 774 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 775 776 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 777 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 778 if (ret) 779 return ret; 780 ret = devm_add_action_or_reset(&pdev->dev, devm_fsl_edma3_detach_pd, fsl_edma); 781 if (ret) 782 return ret; 783 } 784 785 if (drvdata->flags & FSL_EDMA_DRV_TCD64) 786 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 787 788 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 789 for (i = 0; i < fsl_edma->n_chans; i++) { 790 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 791 int len; 792 793 if (fsl_edma->chan_masked & BIT(i)) 794 continue; 795 796 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 797 dev_name(&pdev->dev), i); 798 799 snprintf(fsl_chan->errirq_name, sizeof(fsl_chan->errirq_name), 800 "%s-CH%02d-err", dev_name(&pdev->dev), i); 801 802 fsl_chan->edma = fsl_edma; 803 fsl_chan->pm_state = RUNNING; 804 fsl_chan->srcid = 0; 805 fsl_chan->dma_dir = DMA_NONE; 806 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 807 808 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 809 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 810 fsl_chan->tcd = fsl_edma->membase 811 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 812 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; 813 814 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 815 snprintf(clk_name, sizeof(clk_name), "ch%02d", i); 816 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, 817 (const char *)clk_name); 818 819 if (IS_ERR(fsl_chan->clk)) 820 return PTR_ERR(fsl_chan->clk); 821 } 822 fsl_chan->pdev = pdev; 823 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 824 825 edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr); 826 fsl_edma_chan_mux(fsl_chan, 0, false); 827 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) 828 clk_disable_unprepare(fsl_chan->clk); 829 } 830 831 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 832 if (ret) 833 return ret; 834 835 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 836 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 837 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 838 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 839 840 fsl_edma->dma_dev.dev = &pdev->dev; 841 fsl_edma->dma_dev.device_alloc_chan_resources 842 = fsl_edma_alloc_chan_resources; 843 fsl_edma->dma_dev.device_free_chan_resources 844 = fsl_edma_free_chan_resources; 845 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 846 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 847 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 848 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 849 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 850 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 851 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 852 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 853 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 854 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 855 856 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 857 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 858 859 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 860 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 861 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 862 } 863 864 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 865 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 866 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 867 868 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 869 DMAENGINE_ALIGN_64_BYTES : 870 DMAENGINE_ALIGN_32_BYTES; 871 872 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 873 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 874 FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK)); 875 876 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 877 878 platform_set_drvdata(pdev, fsl_edma); 879 880 ret = dmaenginem_async_device_register(&fsl_edma->dma_dev); 881 if (ret) 882 return dev_err_probe(&pdev->dev, ret, 883 "Can't register Freescale eDMA engine.\n"); 884 885 ret = devm_of_dma_controller_register(&pdev->dev, np, 886 drvdata->dmamuxs ? fsl_edma_xlate : fsl_edma3_xlate, 887 fsl_edma); 888 if (ret) 889 return dev_err_probe(&pdev->dev, ret, 890 "Can't register Freescale eDMA of_dma.\n"); 891 892 /* enable round robin arbitration */ 893 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 894 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 895 896 return 0; 897 } 898 899 static void fsl_edma_remove(struct platform_device *pdev) 900 { 901 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 902 903 fsl_edma_irq_exit(pdev, fsl_edma); 904 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 905 } 906 907 static int fsl_edma_suspend_late(struct device *dev) 908 { 909 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 910 struct fsl_edma_chan *fsl_chan; 911 unsigned long flags; 912 int i; 913 914 for (i = 0; i < fsl_edma->n_chans; i++) { 915 fsl_chan = &fsl_edma->chans[i]; 916 if (fsl_edma->chan_masked & BIT(i)) 917 continue; 918 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 919 /* Make sure chan is idle or will force disable. */ 920 if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) { 921 dev_warn(dev, "WARN: There is non-idle channel.\n"); 922 fsl_edma_disable_request(fsl_chan); 923 fsl_edma_chan_mux(fsl_chan, 0, false); 924 } 925 926 fsl_chan->pm_state = SUSPENDED; 927 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 928 } 929 930 return 0; 931 } 932 933 static int fsl_edma_resume_early(struct device *dev) 934 { 935 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 936 struct fsl_edma_chan *fsl_chan; 937 struct edma_regs *regs = &fsl_edma->regs; 938 int i; 939 940 for (i = 0; i < fsl_edma->n_chans; i++) { 941 fsl_chan = &fsl_edma->chans[i]; 942 if (fsl_edma->chan_masked & BIT(i)) 943 continue; 944 fsl_chan->pm_state = RUNNING; 945 edma_write_tcdreg(fsl_chan, 0, csr); 946 if (fsl_chan->srcid != 0) 947 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true); 948 } 949 950 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 951 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 952 953 return 0; 954 } 955 956 /* 957 * eDMA provides the service to others, so it should be suspend late 958 * and resume early. When eDMA suspend, all of the clients should stop 959 * the DMA data transmission and let the channel idle. 960 */ 961 static const struct dev_pm_ops fsl_edma_pm_ops = { 962 .suspend_late = fsl_edma_suspend_late, 963 .resume_early = fsl_edma_resume_early, 964 }; 965 966 static struct platform_driver fsl_edma_driver = { 967 .driver = { 968 .name = "fsl-edma", 969 .of_match_table = fsl_edma_dt_ids, 970 .pm = &fsl_edma_pm_ops, 971 }, 972 .probe = fsl_edma_probe, 973 .remove = fsl_edma_remove, 974 }; 975 976 static int __init fsl_edma_init(void) 977 { 978 return platform_driver_register(&fsl_edma_driver); 979 } 980 subsys_initcall(fsl_edma_init); 981 982 static void __exit fsl_edma_exit(void) 983 { 984 platform_driver_unregister(&fsl_edma_driver); 985 } 986 module_exit(fsl_edma_exit); 987 988 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 989 MODULE_LICENSE("GPL v2"); 990