1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * 7 * Driver for the Freescale eDMA engine with flexible channel multiplexing 8 * capability for DMA request sources. The eDMA block can be found on some 9 * Vybrid and Layerscape SoCs. 10 */ 11 12 #include <dt-bindings/dma/fsl-edma.h> 13 #include <linux/bitfield.h> 14 #include <linux/module.h> 15 #include <linux/interrupt.h> 16 #include <linux/clk.h> 17 #include <linux/of.h> 18 #include <linux/of_dma.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/pm_domain.h> 22 #include <linux/property.h> 23 24 #include "fsl-edma-common.h" 25 26 static void fsl_edma_synchronize(struct dma_chan *chan) 27 { 28 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 29 30 vchan_synchronize(&fsl_chan->vchan); 31 } 32 33 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 34 { 35 struct fsl_edma_engine *fsl_edma = dev_id; 36 unsigned int intr, ch; 37 struct edma_regs *regs = &fsl_edma->regs; 38 39 intr = edma_readl(fsl_edma, regs->intl); 40 if (!intr) 41 return IRQ_NONE; 42 43 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 44 if (intr & (0x1 << ch)) { 45 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 46 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 47 } 48 } 49 return IRQ_HANDLED; 50 } 51 52 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 53 { 54 struct fsl_edma_chan *fsl_chan = dev_id; 55 unsigned int intr; 56 57 intr = edma_readl_chreg(fsl_chan, ch_int); 58 if (!intr) 59 return IRQ_HANDLED; 60 61 edma_writel_chreg(fsl_chan, 1, ch_int); 62 63 fsl_edma_tx_chan_handler(fsl_chan); 64 65 return IRQ_HANDLED; 66 } 67 68 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 69 { 70 struct fsl_edma_engine *fsl_edma = dev_id; 71 unsigned int err, ch; 72 struct edma_regs *regs = &fsl_edma->regs; 73 74 err = edma_readl(fsl_edma, regs->errl); 75 if (!err) 76 return IRQ_NONE; 77 78 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 79 if (err & (0x1 << ch)) { 80 fsl_edma_disable_request(&fsl_edma->chans[ch]); 81 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 82 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 83 } 84 } 85 return IRQ_HANDLED; 86 } 87 88 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 89 { 90 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 91 return IRQ_HANDLED; 92 93 return fsl_edma_err_handler(irq, dev_id); 94 } 95 96 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 97 struct of_dma *ofdma) 98 { 99 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 100 struct dma_chan *chan, *_chan; 101 struct fsl_edma_chan *fsl_chan; 102 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 103 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 104 105 if (dma_spec->args_count != 2) 106 return NULL; 107 108 guard(mutex)(&fsl_edma->fsl_edma_mutex); 109 110 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 111 if (chan->client_count) 112 continue; 113 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 114 chan = dma_get_slave_channel(chan); 115 if (chan) { 116 chan->device->privatecnt++; 117 fsl_chan = to_fsl_edma_chan(chan); 118 fsl_chan->srcid = dma_spec->args[1]; 119 120 if (!fsl_chan->srcid) { 121 dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n", 122 fsl_chan->srcid); 123 return NULL; 124 } 125 126 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, 127 true); 128 return chan; 129 } 130 } 131 } 132 return NULL; 133 } 134 135 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 136 struct of_dma *ofdma) 137 { 138 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 139 struct dma_chan *chan, *_chan; 140 struct fsl_edma_chan *fsl_chan; 141 bool b_chmux; 142 int i; 143 144 if (dma_spec->args_count != 3) 145 return NULL; 146 147 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 148 149 mutex_lock(&fsl_edma->fsl_edma_mutex); 150 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 151 device_node) { 152 153 if (chan->client_count) 154 continue; 155 156 fsl_chan = to_fsl_edma_chan(chan); 157 i = fsl_chan - fsl_edma->chans; 158 159 fsl_chan->priority = dma_spec->args[1]; 160 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; 161 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; 162 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; 163 164 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) 165 continue; 166 167 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) 168 continue; 169 170 if (!b_chmux && i == dma_spec->args[0]) { 171 chan = dma_get_slave_channel(chan); 172 chan->device->privatecnt++; 173 mutex_unlock(&fsl_edma->fsl_edma_mutex); 174 return chan; 175 } else if (b_chmux && !fsl_chan->srcid) { 176 /* if controller support channel mux, choose a free channel */ 177 chan = dma_get_slave_channel(chan); 178 chan->device->privatecnt++; 179 fsl_chan->srcid = dma_spec->args[0]; 180 mutex_unlock(&fsl_edma->fsl_edma_mutex); 181 return chan; 182 } 183 } 184 mutex_unlock(&fsl_edma->fsl_edma_mutex); 185 return NULL; 186 } 187 188 static int 189 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 190 { 191 int ret; 192 193 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 194 195 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 196 if (fsl_edma->txirq < 0) 197 return fsl_edma->txirq; 198 199 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 200 if (fsl_edma->errirq < 0) 201 return fsl_edma->errirq; 202 203 if (fsl_edma->txirq == fsl_edma->errirq) { 204 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 205 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 206 if (ret) { 207 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 208 return ret; 209 } 210 } else { 211 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 212 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 213 if (ret) { 214 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 215 return ret; 216 } 217 218 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 219 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 220 if (ret) { 221 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 222 return ret; 223 } 224 } 225 226 return 0; 227 } 228 229 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 230 { 231 int ret; 232 int i; 233 234 for (i = 0; i < fsl_edma->n_chans; i++) { 235 236 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 237 238 if (fsl_edma->chan_masked & BIT(i)) 239 continue; 240 241 /* request channel irq */ 242 fsl_chan->txirq = platform_get_irq(pdev, i); 243 if (fsl_chan->txirq < 0) 244 return -EINVAL; 245 246 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, 247 fsl_edma3_tx_handler, IRQF_SHARED, 248 fsl_chan->chan_name, fsl_chan); 249 if (ret) { 250 dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i); 251 return -EINVAL; 252 } 253 } 254 255 return 0; 256 } 257 258 static int 259 fsl_edma2_irq_init(struct platform_device *pdev, 260 struct fsl_edma_engine *fsl_edma) 261 { 262 int i, ret, irq; 263 int count; 264 265 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 266 267 count = platform_irq_count(pdev); 268 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 269 if (count <= 2) { 270 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 271 return -EINVAL; 272 } 273 /* 274 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 275 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 276 * For now, just simply request irq without IRQF_SHARED flag, since 16 277 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 278 */ 279 for (i = 0; i < count; i++) { 280 irq = platform_get_irq(pdev, i); 281 if (irq < 0) 282 return -ENXIO; 283 284 /* The last IRQ is for eDMA err */ 285 if (i == count - 1) 286 ret = devm_request_irq(&pdev->dev, irq, 287 fsl_edma_err_handler, 288 0, "eDMA2-ERR", fsl_edma); 289 else 290 ret = devm_request_irq(&pdev->dev, irq, 291 fsl_edma_tx_handler, 0, 292 fsl_edma->chans[i].chan_name, 293 fsl_edma); 294 if (ret) 295 return ret; 296 } 297 298 return 0; 299 } 300 301 static void fsl_edma_irq_exit( 302 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 303 { 304 if (fsl_edma->txirq == fsl_edma->errirq) { 305 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 306 } else { 307 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 308 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 309 } 310 } 311 312 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 313 { 314 int i; 315 316 for (i = 0; i < nr_clocks; i++) 317 clk_disable_unprepare(fsl_edma->muxclk[i]); 318 } 319 320 static struct fsl_edma_drvdata vf610_data = { 321 .dmamuxs = DMAMUX_NR, 322 .flags = FSL_EDMA_DRV_WRAP_IO, 323 .chreg_off = EDMA_TCD, 324 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 325 .setup_irq = fsl_edma_irq_init, 326 }; 327 328 static struct fsl_edma_drvdata ls1028a_data = { 329 .dmamuxs = DMAMUX_NR, 330 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 331 .chreg_off = EDMA_TCD, 332 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 333 .setup_irq = fsl_edma_irq_init, 334 }; 335 336 static struct fsl_edma_drvdata imx7ulp_data = { 337 .dmamuxs = 1, 338 .chreg_off = EDMA_TCD, 339 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 340 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 341 .setup_irq = fsl_edma2_irq_init, 342 }; 343 344 static struct fsl_edma_drvdata imx8qm_data = { 345 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 346 .chreg_space_sz = 0x10000, 347 .chreg_off = 0x10000, 348 .setup_irq = fsl_edma3_irq_init, 349 }; 350 351 static struct fsl_edma_drvdata imx8ulp_data = { 352 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK | 353 FSL_EDMA_DRV_EDMA3, 354 .chreg_space_sz = 0x10000, 355 .chreg_off = 0x10000, 356 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 357 .mux_skip = 0x10000, 358 .setup_irq = fsl_edma3_irq_init, 359 }; 360 361 static struct fsl_edma_drvdata imx93_data3 = { 362 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 363 .chreg_space_sz = 0x10000, 364 .chreg_off = 0x10000, 365 .setup_irq = fsl_edma3_irq_init, 366 }; 367 368 static struct fsl_edma_drvdata imx93_data4 = { 369 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, 370 .chreg_space_sz = 0x8000, 371 .chreg_off = 0x10000, 372 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 373 .mux_skip = 0x8000, 374 .setup_irq = fsl_edma3_irq_init, 375 }; 376 377 static struct fsl_edma_drvdata imx95_data5 = { 378 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 | 379 FSL_EDMA_DRV_TCD64, 380 .chreg_space_sz = 0x8000, 381 .chreg_off = 0x10000, 382 .mux_off = 0x200, 383 .mux_skip = sizeof(u32), 384 .setup_irq = fsl_edma3_irq_init, 385 }; 386 387 static const struct of_device_id fsl_edma_dt_ids[] = { 388 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 389 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 390 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 391 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 392 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data}, 393 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 394 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 395 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5}, 396 { /* sentinel */ } 397 }; 398 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 399 400 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 401 { 402 struct fsl_edma_chan *fsl_chan; 403 struct device_link *link; 404 struct device *pd_chan; 405 struct device *dev; 406 int i; 407 408 dev = &pdev->dev; 409 410 for (i = 0; i < fsl_edma->n_chans; i++) { 411 if (fsl_edma->chan_masked & BIT(i)) 412 continue; 413 414 fsl_chan = &fsl_edma->chans[i]; 415 416 pd_chan = dev_pm_domain_attach_by_id(dev, i); 417 if (IS_ERR_OR_NULL(pd_chan)) { 418 dev_err(dev, "Failed attach pd %d\n", i); 419 return -EINVAL; 420 } 421 422 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 423 DL_FLAG_PM_RUNTIME | 424 DL_FLAG_RPM_ACTIVE); 425 if (!link) { 426 dev_err(dev, "Failed to add device_link to %d\n", i); 427 return -EINVAL; 428 } 429 430 fsl_chan->pd_dev = pd_chan; 431 432 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 433 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 434 pm_runtime_set_active(fsl_chan->pd_dev); 435 } 436 437 return 0; 438 } 439 440 static int fsl_edma_probe(struct platform_device *pdev) 441 { 442 struct device_node *np = pdev->dev.of_node; 443 struct fsl_edma_engine *fsl_edma; 444 const struct fsl_edma_drvdata *drvdata = NULL; 445 u32 chan_mask[2] = {0, 0}; 446 char clk_name[36]; 447 struct edma_regs *regs; 448 int chans; 449 int ret, i; 450 451 drvdata = device_get_match_data(&pdev->dev); 452 if (!drvdata) { 453 dev_err(&pdev->dev, "unable to find driver data\n"); 454 return -EINVAL; 455 } 456 457 ret = of_property_read_u32(np, "dma-channels", &chans); 458 if (ret) { 459 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 460 return ret; 461 } 462 463 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 464 GFP_KERNEL); 465 if (!fsl_edma) 466 return -ENOMEM; 467 468 fsl_edma->drvdata = drvdata; 469 fsl_edma->n_chans = chans; 470 mutex_init(&fsl_edma->fsl_edma_mutex); 471 472 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 473 if (IS_ERR(fsl_edma->membase)) 474 return PTR_ERR(fsl_edma->membase); 475 476 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 477 fsl_edma_setup_regs(fsl_edma); 478 regs = &fsl_edma->regs; 479 } 480 481 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 482 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 483 if (IS_ERR(fsl_edma->dmaclk)) { 484 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 485 return PTR_ERR(fsl_edma->dmaclk); 486 } 487 } 488 489 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 490 491 if (ret > 0) { 492 fsl_edma->chan_masked = chan_mask[1]; 493 fsl_edma->chan_masked <<= 32; 494 fsl_edma->chan_masked |= chan_mask[0]; 495 } 496 497 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 498 char clkname[32]; 499 500 /* eDMAv3 mux register move to TCD area if ch_mux exist */ 501 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) 502 break; 503 504 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 505 1 + i); 506 if (IS_ERR(fsl_edma->muxbase[i])) { 507 /* on error: disable all previously enabled clks */ 508 fsl_disable_clocks(fsl_edma, i); 509 return PTR_ERR(fsl_edma->muxbase[i]); 510 } 511 512 sprintf(clkname, "dmamux%d", i); 513 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 514 if (IS_ERR(fsl_edma->muxclk[i])) { 515 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 516 /* on error: disable all previously enabled clks */ 517 return PTR_ERR(fsl_edma->muxclk[i]); 518 } 519 } 520 521 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 522 523 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 524 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 525 if (ret) 526 return ret; 527 } 528 529 if (drvdata->flags & FSL_EDMA_DRV_TCD64) 530 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 531 532 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 533 for (i = 0; i < fsl_edma->n_chans; i++) { 534 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 535 int len; 536 537 if (fsl_edma->chan_masked & BIT(i)) 538 continue; 539 540 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 541 dev_name(&pdev->dev), i); 542 543 fsl_chan->edma = fsl_edma; 544 fsl_chan->pm_state = RUNNING; 545 fsl_chan->srcid = 0; 546 fsl_chan->idle = true; 547 fsl_chan->dma_dir = DMA_NONE; 548 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 549 550 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 551 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 552 fsl_chan->tcd = fsl_edma->membase 553 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 554 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; 555 556 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 557 snprintf(clk_name, sizeof(clk_name), "ch%02d", i); 558 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, 559 (const char *)clk_name); 560 561 if (IS_ERR(fsl_chan->clk)) 562 return PTR_ERR(fsl_chan->clk); 563 } 564 fsl_chan->pdev = pdev; 565 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 566 567 edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr); 568 fsl_edma_chan_mux(fsl_chan, 0, false); 569 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) 570 clk_disable_unprepare(fsl_chan->clk); 571 } 572 573 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 574 if (ret) 575 return ret; 576 577 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 578 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 579 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 580 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 581 582 fsl_edma->dma_dev.dev = &pdev->dev; 583 fsl_edma->dma_dev.device_alloc_chan_resources 584 = fsl_edma_alloc_chan_resources; 585 fsl_edma->dma_dev.device_free_chan_resources 586 = fsl_edma_free_chan_resources; 587 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 588 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 589 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 590 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 591 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 592 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 593 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 594 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 595 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 596 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 597 598 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 599 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 600 601 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 602 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 603 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 604 } 605 606 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 607 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 608 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 609 610 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 611 DMAENGINE_ALIGN_64_BYTES : 612 DMAENGINE_ALIGN_32_BYTES; 613 614 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 615 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 616 FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK)); 617 618 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 619 620 platform_set_drvdata(pdev, fsl_edma); 621 622 ret = dma_async_device_register(&fsl_edma->dma_dev); 623 if (ret) { 624 dev_err(&pdev->dev, 625 "Can't register Freescale eDMA engine. (%d)\n", ret); 626 return ret; 627 } 628 629 ret = of_dma_controller_register(np, 630 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate, 631 fsl_edma); 632 if (ret) { 633 dev_err(&pdev->dev, 634 "Can't register Freescale eDMA of_dma. (%d)\n", ret); 635 dma_async_device_unregister(&fsl_edma->dma_dev); 636 return ret; 637 } 638 639 /* enable round robin arbitration */ 640 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 641 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 642 643 return 0; 644 } 645 646 static void fsl_edma_remove(struct platform_device *pdev) 647 { 648 struct device_node *np = pdev->dev.of_node; 649 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 650 651 fsl_edma_irq_exit(pdev, fsl_edma); 652 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 653 of_dma_controller_free(np); 654 dma_async_device_unregister(&fsl_edma->dma_dev); 655 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); 656 } 657 658 static int fsl_edma_suspend_late(struct device *dev) 659 { 660 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 661 struct fsl_edma_chan *fsl_chan; 662 unsigned long flags; 663 int i; 664 665 for (i = 0; i < fsl_edma->n_chans; i++) { 666 fsl_chan = &fsl_edma->chans[i]; 667 if (fsl_edma->chan_masked & BIT(i)) 668 continue; 669 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 670 /* Make sure chan is idle or will force disable. */ 671 if (unlikely(!fsl_chan->idle)) { 672 dev_warn(dev, "WARN: There is non-idle channel."); 673 fsl_edma_disable_request(fsl_chan); 674 fsl_edma_chan_mux(fsl_chan, 0, false); 675 } 676 677 fsl_chan->pm_state = SUSPENDED; 678 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 679 } 680 681 return 0; 682 } 683 684 static int fsl_edma_resume_early(struct device *dev) 685 { 686 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 687 struct fsl_edma_chan *fsl_chan; 688 struct edma_regs *regs = &fsl_edma->regs; 689 int i; 690 691 for (i = 0; i < fsl_edma->n_chans; i++) { 692 fsl_chan = &fsl_edma->chans[i]; 693 if (fsl_edma->chan_masked & BIT(i)) 694 continue; 695 fsl_chan->pm_state = RUNNING; 696 edma_write_tcdreg(fsl_chan, 0, csr); 697 if (fsl_chan->srcid != 0) 698 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true); 699 } 700 701 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 702 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 703 704 return 0; 705 } 706 707 /* 708 * eDMA provides the service to others, so it should be suspend late 709 * and resume early. When eDMA suspend, all of the clients should stop 710 * the DMA data transmission and let the channel idle. 711 */ 712 static const struct dev_pm_ops fsl_edma_pm_ops = { 713 .suspend_late = fsl_edma_suspend_late, 714 .resume_early = fsl_edma_resume_early, 715 }; 716 717 static struct platform_driver fsl_edma_driver = { 718 .driver = { 719 .name = "fsl-edma", 720 .of_match_table = fsl_edma_dt_ids, 721 .pm = &fsl_edma_pm_ops, 722 }, 723 .probe = fsl_edma_probe, 724 .remove_new = fsl_edma_remove, 725 }; 726 727 static int __init fsl_edma_init(void) 728 { 729 return platform_driver_register(&fsl_edma_driver); 730 } 731 subsys_initcall(fsl_edma_init); 732 733 static void __exit fsl_edma_exit(void) 734 { 735 platform_driver_unregister(&fsl_edma_driver); 736 } 737 module_exit(fsl_edma_exit); 738 739 MODULE_ALIAS("platform:fsl-edma"); 740 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 741 MODULE_LICENSE("GPL v2"); 742