1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> 5 6 #include <linux/dmapool.h> 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 10 #include "fsl-edma-common.h" 11 12 #define EDMA_CR 0x00 13 #define EDMA_ES 0x04 14 #define EDMA_ERQ 0x0C 15 #define EDMA_EEI 0x14 16 #define EDMA_SERQ 0x1B 17 #define EDMA_CERQ 0x1A 18 #define EDMA_SEEI 0x19 19 #define EDMA_CEEI 0x18 20 #define EDMA_CINT 0x1F 21 #define EDMA_CERR 0x1E 22 #define EDMA_SSRT 0x1D 23 #define EDMA_CDNE 0x1C 24 #define EDMA_INTR 0x24 25 #define EDMA_ERR 0x2C 26 27 #define EDMA64_ERQH 0x08 28 #define EDMA64_EEIH 0x10 29 #define EDMA64_SERQ 0x18 30 #define EDMA64_CERQ 0x19 31 #define EDMA64_SEEI 0x1a 32 #define EDMA64_CEEI 0x1b 33 #define EDMA64_CINT 0x1c 34 #define EDMA64_CERR 0x1d 35 #define EDMA64_SSRT 0x1e 36 #define EDMA64_CDNE 0x1f 37 #define EDMA64_INTH 0x20 38 #define EDMA64_INTL 0x24 39 #define EDMA64_ERRH 0x28 40 #define EDMA64_ERRL 0x2c 41 42 #define EDMA_TCD 0x1000 43 44 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) 45 { 46 struct edma_regs *regs = &fsl_chan->edma->regs; 47 u32 ch = fsl_chan->vchan.chan.chan_id; 48 49 if (fsl_chan->edma->version == v1) { 50 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); 51 edma_writeb(fsl_chan->edma, ch, regs->serq); 52 } else { 53 /* ColdFire is big endian, and accesses natively 54 * big endian I/O peripherals 55 */ 56 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); 57 iowrite8(ch, regs->serq); 58 } 59 } 60 61 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) 62 { 63 struct edma_regs *regs = &fsl_chan->edma->regs; 64 u32 ch = fsl_chan->vchan.chan.chan_id; 65 66 if (fsl_chan->edma->version == v1) { 67 edma_writeb(fsl_chan->edma, ch, regs->cerq); 68 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); 69 } else { 70 /* ColdFire is big endian, and accesses natively 71 * big endian I/O peripherals 72 */ 73 iowrite8(ch, regs->cerq); 74 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); 75 } 76 } 77 EXPORT_SYMBOL_GPL(fsl_edma_disable_request); 78 79 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 80 unsigned int slot, bool enable) 81 { 82 u32 ch = fsl_chan->vchan.chan.chan_id; 83 void __iomem *muxaddr; 84 unsigned int chans_per_mux, ch_off; 85 86 chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR; 87 ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; 88 muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; 89 slot = EDMAMUX_CHCFG_SOURCE(slot); 90 91 if (enable) 92 iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off); 93 else 94 iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off); 95 } 96 EXPORT_SYMBOL_GPL(fsl_edma_chan_mux); 97 98 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) 99 { 100 switch (addr_width) { 101 case 1: 102 return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; 103 case 2: 104 return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; 105 case 4: 106 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 107 case 8: 108 return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; 109 default: 110 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 111 } 112 } 113 114 void fsl_edma_free_desc(struct virt_dma_desc *vdesc) 115 { 116 struct fsl_edma_desc *fsl_desc; 117 int i; 118 119 fsl_desc = to_fsl_edma_desc(vdesc); 120 for (i = 0; i < fsl_desc->n_tcds; i++) 121 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, 122 fsl_desc->tcd[i].ptcd); 123 kfree(fsl_desc); 124 } 125 EXPORT_SYMBOL_GPL(fsl_edma_free_desc); 126 127 int fsl_edma_terminate_all(struct dma_chan *chan) 128 { 129 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 130 unsigned long flags; 131 LIST_HEAD(head); 132 133 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 134 fsl_edma_disable_request(fsl_chan); 135 fsl_chan->edesc = NULL; 136 fsl_chan->idle = true; 137 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 138 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 139 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 140 return 0; 141 } 142 EXPORT_SYMBOL_GPL(fsl_edma_terminate_all); 143 144 int fsl_edma_pause(struct dma_chan *chan) 145 { 146 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 147 unsigned long flags; 148 149 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 150 if (fsl_chan->edesc) { 151 fsl_edma_disable_request(fsl_chan); 152 fsl_chan->status = DMA_PAUSED; 153 fsl_chan->idle = true; 154 } 155 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 156 return 0; 157 } 158 EXPORT_SYMBOL_GPL(fsl_edma_pause); 159 160 int fsl_edma_resume(struct dma_chan *chan) 161 { 162 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 163 unsigned long flags; 164 165 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 166 if (fsl_chan->edesc) { 167 fsl_edma_enable_request(fsl_chan); 168 fsl_chan->status = DMA_IN_PROGRESS; 169 fsl_chan->idle = false; 170 } 171 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 172 return 0; 173 } 174 EXPORT_SYMBOL_GPL(fsl_edma_resume); 175 176 int fsl_edma_slave_config(struct dma_chan *chan, 177 struct dma_slave_config *cfg) 178 { 179 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 180 181 fsl_chan->fsc.dir = cfg->direction; 182 if (cfg->direction == DMA_DEV_TO_MEM) { 183 fsl_chan->fsc.dev_addr = cfg->src_addr; 184 fsl_chan->fsc.addr_width = cfg->src_addr_width; 185 fsl_chan->fsc.burst = cfg->src_maxburst; 186 fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->src_addr_width); 187 } else if (cfg->direction == DMA_MEM_TO_DEV) { 188 fsl_chan->fsc.dev_addr = cfg->dst_addr; 189 fsl_chan->fsc.addr_width = cfg->dst_addr_width; 190 fsl_chan->fsc.burst = cfg->dst_maxburst; 191 fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->dst_addr_width); 192 } else 193 return -EINVAL; 194 195 return 0; 196 } 197 EXPORT_SYMBOL_GPL(fsl_edma_slave_config); 198 199 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, 200 struct virt_dma_desc *vdesc, bool in_progress) 201 { 202 struct fsl_edma_desc *edesc = fsl_chan->edesc; 203 struct edma_regs *regs = &fsl_chan->edma->regs; 204 u32 ch = fsl_chan->vchan.chan.chan_id; 205 enum dma_transfer_direction dir = fsl_chan->fsc.dir; 206 dma_addr_t cur_addr, dma_addr; 207 size_t len, size; 208 int i; 209 210 /* calculate the total size in this desc */ 211 for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) 212 len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 213 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 214 215 if (!in_progress) 216 return len; 217 218 if (dir == DMA_MEM_TO_DEV) 219 cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr); 220 else 221 cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr); 222 223 /* figure out the finished and calculate the residue */ 224 for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { 225 size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 226 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 227 if (dir == DMA_MEM_TO_DEV) 228 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); 229 else 230 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); 231 232 len -= size; 233 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { 234 len += dma_addr + size - cur_addr; 235 break; 236 } 237 } 238 239 return len; 240 } 241 242 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 243 dma_cookie_t cookie, struct dma_tx_state *txstate) 244 { 245 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 246 struct virt_dma_desc *vdesc; 247 enum dma_status status; 248 unsigned long flags; 249 250 status = dma_cookie_status(chan, cookie, txstate); 251 if (status == DMA_COMPLETE) 252 return status; 253 254 if (!txstate) 255 return fsl_chan->status; 256 257 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 258 vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); 259 if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) 260 txstate->residue = 261 fsl_edma_desc_residue(fsl_chan, vdesc, true); 262 else if (vdesc) 263 txstate->residue = 264 fsl_edma_desc_residue(fsl_chan, vdesc, false); 265 else 266 txstate->residue = 0; 267 268 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 269 270 return fsl_chan->status; 271 } 272 EXPORT_SYMBOL_GPL(fsl_edma_tx_status); 273 274 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, 275 struct fsl_edma_hw_tcd *tcd) 276 { 277 struct fsl_edma_engine *edma = fsl_chan->edma; 278 struct edma_regs *regs = &fsl_chan->edma->regs; 279 u32 ch = fsl_chan->vchan.chan.chan_id; 280 281 /* 282 * TCD parameters are stored in struct fsl_edma_hw_tcd in little 283 * endian format. However, we need to load the TCD registers in 284 * big- or little-endian obeying the eDMA engine model endian. 285 */ 286 edma_writew(edma, 0, ®s->tcd[ch].csr); 287 edma_writel(edma, le32_to_cpu(tcd->saddr), ®s->tcd[ch].saddr); 288 edma_writel(edma, le32_to_cpu(tcd->daddr), ®s->tcd[ch].daddr); 289 290 edma_writew(edma, le16_to_cpu(tcd->attr), ®s->tcd[ch].attr); 291 edma_writew(edma, le16_to_cpu(tcd->soff), ®s->tcd[ch].soff); 292 293 edma_writel(edma, le32_to_cpu(tcd->nbytes), ®s->tcd[ch].nbytes); 294 edma_writel(edma, le32_to_cpu(tcd->slast), ®s->tcd[ch].slast); 295 296 edma_writew(edma, le16_to_cpu(tcd->citer), ®s->tcd[ch].citer); 297 edma_writew(edma, le16_to_cpu(tcd->biter), ®s->tcd[ch].biter); 298 edma_writew(edma, le16_to_cpu(tcd->doff), ®s->tcd[ch].doff); 299 300 edma_writel(edma, le32_to_cpu(tcd->dlast_sga), 301 ®s->tcd[ch].dlast_sga); 302 303 edma_writew(edma, le16_to_cpu(tcd->csr), ®s->tcd[ch].csr); 304 } 305 306 static inline 307 void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, 308 u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, 309 u16 biter, u16 doff, u32 dlast_sga, bool major_int, 310 bool disable_req, bool enable_sg) 311 { 312 u16 csr = 0; 313 314 /* 315 * eDMA hardware SGs require the TCDs to be stored in little 316 * endian format irrespective of the register endian model. 317 * So we put the value in little endian in memory, waiting 318 * for fsl_edma_set_tcd_regs doing the swap. 319 */ 320 tcd->saddr = cpu_to_le32(src); 321 tcd->daddr = cpu_to_le32(dst); 322 323 tcd->attr = cpu_to_le16(attr); 324 325 tcd->soff = cpu_to_le16(soff); 326 327 tcd->nbytes = cpu_to_le32(nbytes); 328 tcd->slast = cpu_to_le32(slast); 329 330 tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); 331 tcd->doff = cpu_to_le16(doff); 332 333 tcd->dlast_sga = cpu_to_le32(dlast_sga); 334 335 tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); 336 if (major_int) 337 csr |= EDMA_TCD_CSR_INT_MAJOR; 338 339 if (disable_req) 340 csr |= EDMA_TCD_CSR_D_REQ; 341 342 if (enable_sg) 343 csr |= EDMA_TCD_CSR_E_SG; 344 345 tcd->csr = cpu_to_le16(csr); 346 } 347 348 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, 349 int sg_len) 350 { 351 struct fsl_edma_desc *fsl_desc; 352 int i; 353 354 fsl_desc = kzalloc(sizeof(*fsl_desc) + 355 sizeof(struct fsl_edma_sw_tcd) * 356 sg_len, GFP_NOWAIT); 357 if (!fsl_desc) 358 return NULL; 359 360 fsl_desc->echan = fsl_chan; 361 fsl_desc->n_tcds = sg_len; 362 for (i = 0; i < sg_len; i++) { 363 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, 364 GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); 365 if (!fsl_desc->tcd[i].vtcd) 366 goto err; 367 } 368 return fsl_desc; 369 370 err: 371 while (--i >= 0) 372 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, 373 fsl_desc->tcd[i].ptcd); 374 kfree(fsl_desc); 375 return NULL; 376 } 377 378 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 379 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 380 size_t period_len, enum dma_transfer_direction direction, 381 unsigned long flags) 382 { 383 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 384 struct fsl_edma_desc *fsl_desc; 385 dma_addr_t dma_buf_next; 386 int sg_len, i; 387 u32 src_addr, dst_addr, last_sg, nbytes; 388 u16 soff, doff, iter; 389 390 if (!is_slave_direction(fsl_chan->fsc.dir)) 391 return NULL; 392 393 sg_len = buf_len / period_len; 394 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 395 if (!fsl_desc) 396 return NULL; 397 fsl_desc->iscyclic = true; 398 399 dma_buf_next = dma_addr; 400 nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; 401 iter = period_len / nbytes; 402 403 for (i = 0; i < sg_len; i++) { 404 if (dma_buf_next >= dma_addr + buf_len) 405 dma_buf_next = dma_addr; 406 407 /* get next sg's physical address */ 408 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 409 410 if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { 411 src_addr = dma_buf_next; 412 dst_addr = fsl_chan->fsc.dev_addr; 413 soff = fsl_chan->fsc.addr_width; 414 doff = 0; 415 } else { 416 src_addr = fsl_chan->fsc.dev_addr; 417 dst_addr = dma_buf_next; 418 soff = 0; 419 doff = fsl_chan->fsc.addr_width; 420 } 421 422 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr, 423 fsl_chan->fsc.attr, soff, nbytes, 0, iter, 424 iter, doff, last_sg, true, false, true); 425 dma_buf_next += period_len; 426 } 427 428 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 429 } 430 EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic); 431 432 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 433 struct dma_chan *chan, struct scatterlist *sgl, 434 unsigned int sg_len, enum dma_transfer_direction direction, 435 unsigned long flags, void *context) 436 { 437 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 438 struct fsl_edma_desc *fsl_desc; 439 struct scatterlist *sg; 440 u32 src_addr, dst_addr, last_sg, nbytes; 441 u16 soff, doff, iter; 442 int i; 443 444 if (!is_slave_direction(fsl_chan->fsc.dir)) 445 return NULL; 446 447 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 448 if (!fsl_desc) 449 return NULL; 450 fsl_desc->iscyclic = false; 451 452 nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; 453 for_each_sg(sgl, sg, sg_len, i) { 454 /* get next sg's physical address */ 455 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 456 457 if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { 458 src_addr = sg_dma_address(sg); 459 dst_addr = fsl_chan->fsc.dev_addr; 460 soff = fsl_chan->fsc.addr_width; 461 doff = 0; 462 } else { 463 src_addr = fsl_chan->fsc.dev_addr; 464 dst_addr = sg_dma_address(sg); 465 soff = 0; 466 doff = fsl_chan->fsc.addr_width; 467 } 468 469 iter = sg_dma_len(sg) / nbytes; 470 if (i < sg_len - 1) { 471 last_sg = fsl_desc->tcd[(i + 1)].ptcd; 472 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 473 dst_addr, fsl_chan->fsc.attr, soff, 474 nbytes, 0, iter, iter, doff, last_sg, 475 false, false, true); 476 } else { 477 last_sg = 0; 478 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 479 dst_addr, fsl_chan->fsc.attr, soff, 480 nbytes, 0, iter, iter, doff, last_sg, 481 true, true, false); 482 } 483 } 484 485 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 486 } 487 EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg); 488 489 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) 490 { 491 struct virt_dma_desc *vdesc; 492 493 vdesc = vchan_next_desc(&fsl_chan->vchan); 494 if (!vdesc) 495 return; 496 fsl_chan->edesc = to_fsl_edma_desc(vdesc); 497 fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); 498 fsl_edma_enable_request(fsl_chan); 499 fsl_chan->status = DMA_IN_PROGRESS; 500 fsl_chan->idle = false; 501 } 502 EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc); 503 504 void fsl_edma_issue_pending(struct dma_chan *chan) 505 { 506 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 507 unsigned long flags; 508 509 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 510 511 if (unlikely(fsl_chan->pm_state != RUNNING)) { 512 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 513 /* cannot submit due to suspend */ 514 return; 515 } 516 517 if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) 518 fsl_edma_xfer_desc(fsl_chan); 519 520 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 521 } 522 EXPORT_SYMBOL_GPL(fsl_edma_issue_pending); 523 524 int fsl_edma_alloc_chan_resources(struct dma_chan *chan) 525 { 526 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 527 528 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, 529 sizeof(struct fsl_edma_hw_tcd), 530 32, 0); 531 return 0; 532 } 533 EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources); 534 535 void fsl_edma_free_chan_resources(struct dma_chan *chan) 536 { 537 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 538 unsigned long flags; 539 LIST_HEAD(head); 540 541 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 542 fsl_edma_disable_request(fsl_chan); 543 fsl_edma_chan_mux(fsl_chan, 0, false); 544 fsl_chan->edesc = NULL; 545 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 546 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 547 548 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 549 dma_pool_destroy(fsl_chan->tcd_pool); 550 fsl_chan->tcd_pool = NULL; 551 } 552 EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources); 553 554 void fsl_edma_cleanup_vchan(struct dma_device *dmadev) 555 { 556 struct fsl_edma_chan *chan, *_chan; 557 558 list_for_each_entry_safe(chan, _chan, 559 &dmadev->channels, vchan.chan.device_node) { 560 list_del(&chan->vchan.chan.device_node); 561 tasklet_kill(&chan->vchan.task); 562 } 563 } 564 EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan); 565 566 /* 567 * On the 32 channels Vybrid/mpc577x edma version (here called "v1"), 568 * register offsets are different compared to ColdFire mcf5441x 64 channels 569 * edma (here called "v2"). 570 * 571 * This function sets up register offsets as per proper declared version 572 * so must be called in xxx_edma_probe() just after setting the 573 * edma "version" and "membase" appropriately. 574 */ 575 void fsl_edma_setup_regs(struct fsl_edma_engine *edma) 576 { 577 edma->regs.cr = edma->membase + EDMA_CR; 578 edma->regs.es = edma->membase + EDMA_ES; 579 edma->regs.erql = edma->membase + EDMA_ERQ; 580 edma->regs.eeil = edma->membase + EDMA_EEI; 581 582 edma->regs.serq = edma->membase + ((edma->version == v1) ? 583 EDMA_SERQ : EDMA64_SERQ); 584 edma->regs.cerq = edma->membase + ((edma->version == v1) ? 585 EDMA_CERQ : EDMA64_CERQ); 586 edma->regs.seei = edma->membase + ((edma->version == v1) ? 587 EDMA_SEEI : EDMA64_SEEI); 588 edma->regs.ceei = edma->membase + ((edma->version == v1) ? 589 EDMA_CEEI : EDMA64_CEEI); 590 edma->regs.cint = edma->membase + ((edma->version == v1) ? 591 EDMA_CINT : EDMA64_CINT); 592 edma->regs.cerr = edma->membase + ((edma->version == v1) ? 593 EDMA_CERR : EDMA64_CERR); 594 edma->regs.ssrt = edma->membase + ((edma->version == v1) ? 595 EDMA_SSRT : EDMA64_SSRT); 596 edma->regs.cdne = edma->membase + ((edma->version == v1) ? 597 EDMA_CDNE : EDMA64_CDNE); 598 edma->regs.intl = edma->membase + ((edma->version == v1) ? 599 EDMA_INTR : EDMA64_INTL); 600 edma->regs.errl = edma->membase + ((edma->version == v1) ? 601 EDMA_ERR : EDMA64_ERRL); 602 603 if (edma->version == v2) { 604 edma->regs.erqh = edma->membase + EDMA64_ERQH; 605 edma->regs.eeih = edma->membase + EDMA64_EEIH; 606 edma->regs.errh = edma->membase + EDMA64_ERRH; 607 edma->regs.inth = edma->membase + EDMA64_INTH; 608 } 609 610 edma->regs.tcd = edma->membase + EDMA_TCD; 611 } 612 EXPORT_SYMBOL_GPL(fsl_edma_setup_regs); 613 614 MODULE_LICENSE("GPL v2"); 615