1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> 5 6 #include <linux/clk.h> 7 #include <linux/dmapool.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/pm_domain.h> 13 14 #include "fsl-edma-common.h" 15 16 #define EDMA_CR 0x00 17 #define EDMA_ES 0x04 18 #define EDMA_ERQ 0x0C 19 #define EDMA_EEI 0x14 20 #define EDMA_SERQ 0x1B 21 #define EDMA_CERQ 0x1A 22 #define EDMA_SEEI 0x19 23 #define EDMA_CEEI 0x18 24 #define EDMA_CINT 0x1F 25 #define EDMA_CERR 0x1E 26 #define EDMA_SSRT 0x1D 27 #define EDMA_CDNE 0x1C 28 #define EDMA_INTR 0x24 29 #define EDMA_ERR 0x2C 30 31 #define EDMA64_ERQH 0x08 32 #define EDMA64_EEIH 0x10 33 #define EDMA64_SERQ 0x18 34 #define EDMA64_CERQ 0x19 35 #define EDMA64_SEEI 0x1a 36 #define EDMA64_CEEI 0x1b 37 #define EDMA64_CINT 0x1c 38 #define EDMA64_CERR 0x1d 39 #define EDMA64_SSRT 0x1e 40 #define EDMA64_CDNE 0x1f 41 #define EDMA64_INTH 0x20 42 #define EDMA64_INTL 0x24 43 #define EDMA64_ERRH 0x28 44 #define EDMA64_ERRL 0x2c 45 46 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan) 47 { 48 spin_lock(&fsl_chan->vchan.lock); 49 50 if (!fsl_chan->edesc) { 51 /* terminate_all called before */ 52 spin_unlock(&fsl_chan->vchan.lock); 53 return; 54 } 55 56 if (!fsl_chan->edesc->iscyclic) { 57 list_del(&fsl_chan->edesc->vdesc.node); 58 vchan_cookie_complete(&fsl_chan->edesc->vdesc); 59 fsl_chan->edesc = NULL; 60 fsl_chan->status = DMA_COMPLETE; 61 fsl_chan->idle = true; 62 } else { 63 vchan_cyclic_callback(&fsl_chan->edesc->vdesc); 64 } 65 66 if (!fsl_chan->edesc) 67 fsl_edma_xfer_desc(fsl_chan); 68 69 spin_unlock(&fsl_chan->vchan.lock); 70 } 71 72 static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan) 73 { 74 u32 val, flags; 75 76 flags = fsl_edma_drvflags(fsl_chan); 77 val = edma_readl_chreg(fsl_chan, ch_sbr); 78 /* Remote/local swapped wrongly on iMX8 QM Audio edma */ 79 if (flags & FSL_EDMA_DRV_QUIRK_SWAPPED) { 80 if (!fsl_chan->is_rxchan) 81 val |= EDMA_V3_CH_SBR_RD; 82 else 83 val |= EDMA_V3_CH_SBR_WR; 84 } else { 85 if (fsl_chan->is_rxchan) 86 val |= EDMA_V3_CH_SBR_RD; 87 else 88 val |= EDMA_V3_CH_SBR_WR; 89 } 90 91 if (fsl_chan->is_remote) 92 val &= ~(EDMA_V3_CH_SBR_RD | EDMA_V3_CH_SBR_WR); 93 94 edma_writel_chreg(fsl_chan, val, ch_sbr); 95 96 if (flags & FSL_EDMA_DRV_HAS_CHMUX) { 97 /* 98 * ch_mux: With the exception of 0, attempts to write a value 99 * already in use will be forced to 0. 100 */ 101 if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr)) 102 edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr); 103 } 104 105 val = edma_readl_chreg(fsl_chan, ch_csr); 106 val |= EDMA_V3_CH_CSR_ERQ; 107 edma_writel_chreg(fsl_chan, val, ch_csr); 108 } 109 110 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) 111 { 112 struct edma_regs *regs = &fsl_chan->edma->regs; 113 u32 ch = fsl_chan->vchan.chan.chan_id; 114 115 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) 116 return fsl_edma3_enable_request(fsl_chan); 117 118 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { 119 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); 120 edma_writeb(fsl_chan->edma, ch, regs->serq); 121 } else { 122 /* ColdFire is big endian, and accesses natively 123 * big endian I/O peripherals 124 */ 125 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); 126 iowrite8(ch, regs->serq); 127 } 128 } 129 130 static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan) 131 { 132 u32 val = edma_readl_chreg(fsl_chan, ch_csr); 133 u32 flags; 134 135 flags = fsl_edma_drvflags(fsl_chan); 136 137 if (flags & FSL_EDMA_DRV_HAS_CHMUX) 138 edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr); 139 140 val &= ~EDMA_V3_CH_CSR_ERQ; 141 edma_writel_chreg(fsl_chan, val, ch_csr); 142 } 143 144 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) 145 { 146 struct edma_regs *regs = &fsl_chan->edma->regs; 147 u32 ch = fsl_chan->vchan.chan.chan_id; 148 149 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) 150 return fsl_edma3_disable_request(fsl_chan); 151 152 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { 153 edma_writeb(fsl_chan->edma, ch, regs->cerq); 154 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); 155 } else { 156 /* ColdFire is big endian, and accesses natively 157 * big endian I/O peripherals 158 */ 159 iowrite8(ch, regs->cerq); 160 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); 161 } 162 } 163 164 static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr, 165 u32 off, u32 slot, bool enable) 166 { 167 u8 val8; 168 169 if (enable) 170 val8 = EDMAMUX_CHCFG_ENBL | slot; 171 else 172 val8 = EDMAMUX_CHCFG_DIS; 173 174 iowrite8(val8, addr + off); 175 } 176 177 static void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *addr, 178 u32 off, u32 slot, bool enable) 179 { 180 u32 val; 181 182 if (enable) 183 val = EDMAMUX_CHCFG_ENBL << 24 | slot; 184 else 185 val = EDMAMUX_CHCFG_DIS; 186 187 iowrite32(val, addr + off * 4); 188 } 189 190 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 191 unsigned int slot, bool enable) 192 { 193 u32 ch = fsl_chan->vchan.chan.chan_id; 194 void __iomem *muxaddr; 195 unsigned int chans_per_mux, ch_off; 196 int endian_diff[4] = {3, 1, -1, -3}; 197 u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; 198 199 if (!dmamux_nr) 200 return; 201 202 chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; 203 ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; 204 205 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_MUX_SWAP) 206 ch_off += endian_diff[ch_off % 4]; 207 208 muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; 209 slot = EDMAMUX_CHCFG_SOURCE(slot); 210 211 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_CONFIG32) 212 mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable); 213 else 214 mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable); 215 } 216 217 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) 218 { 219 u32 val; 220 221 if (addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 222 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 223 224 val = ffs(addr_width) - 1; 225 return val | (val << 8); 226 } 227 228 void fsl_edma_free_desc(struct virt_dma_desc *vdesc) 229 { 230 struct fsl_edma_desc *fsl_desc; 231 int i; 232 233 fsl_desc = to_fsl_edma_desc(vdesc); 234 for (i = 0; i < fsl_desc->n_tcds; i++) 235 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, 236 fsl_desc->tcd[i].ptcd); 237 kfree(fsl_desc); 238 } 239 240 int fsl_edma_terminate_all(struct dma_chan *chan) 241 { 242 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 243 unsigned long flags; 244 LIST_HEAD(head); 245 246 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 247 fsl_edma_disable_request(fsl_chan); 248 fsl_chan->edesc = NULL; 249 fsl_chan->idle = true; 250 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 251 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 252 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 253 254 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_PD) 255 pm_runtime_allow(fsl_chan->pd_dev); 256 257 return 0; 258 } 259 260 int fsl_edma_pause(struct dma_chan *chan) 261 { 262 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 263 unsigned long flags; 264 265 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 266 if (fsl_chan->edesc) { 267 fsl_edma_disable_request(fsl_chan); 268 fsl_chan->status = DMA_PAUSED; 269 fsl_chan->idle = true; 270 } 271 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 272 return 0; 273 } 274 275 int fsl_edma_resume(struct dma_chan *chan) 276 { 277 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 278 unsigned long flags; 279 280 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 281 if (fsl_chan->edesc) { 282 fsl_edma_enable_request(fsl_chan); 283 fsl_chan->status = DMA_IN_PROGRESS; 284 fsl_chan->idle = false; 285 } 286 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 287 return 0; 288 } 289 290 static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan) 291 { 292 if (fsl_chan->dma_dir != DMA_NONE) 293 dma_unmap_resource(fsl_chan->vchan.chan.device->dev, 294 fsl_chan->dma_dev_addr, 295 fsl_chan->dma_dev_size, 296 fsl_chan->dma_dir, 0); 297 fsl_chan->dma_dir = DMA_NONE; 298 } 299 300 static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan, 301 enum dma_transfer_direction dir) 302 { 303 struct device *dev = fsl_chan->vchan.chan.device->dev; 304 enum dma_data_direction dma_dir; 305 phys_addr_t addr = 0; 306 u32 size = 0; 307 308 switch (dir) { 309 case DMA_MEM_TO_DEV: 310 dma_dir = DMA_FROM_DEVICE; 311 addr = fsl_chan->cfg.dst_addr; 312 size = fsl_chan->cfg.dst_maxburst; 313 break; 314 case DMA_DEV_TO_MEM: 315 dma_dir = DMA_TO_DEVICE; 316 addr = fsl_chan->cfg.src_addr; 317 size = fsl_chan->cfg.src_maxburst; 318 break; 319 default: 320 dma_dir = DMA_NONE; 321 break; 322 } 323 324 /* Already mapped for this config? */ 325 if (fsl_chan->dma_dir == dma_dir) 326 return true; 327 328 fsl_edma_unprep_slave_dma(fsl_chan); 329 330 fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0); 331 if (dma_mapping_error(dev, fsl_chan->dma_dev_addr)) 332 return false; 333 fsl_chan->dma_dev_size = size; 334 fsl_chan->dma_dir = dma_dir; 335 336 return true; 337 } 338 339 int fsl_edma_slave_config(struct dma_chan *chan, 340 struct dma_slave_config *cfg) 341 { 342 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 343 344 memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg)); 345 fsl_edma_unprep_slave_dma(fsl_chan); 346 347 return 0; 348 } 349 350 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, 351 struct virt_dma_desc *vdesc, bool in_progress) 352 { 353 struct fsl_edma_desc *edesc = fsl_chan->edesc; 354 enum dma_transfer_direction dir = edesc->dirn; 355 dma_addr_t cur_addr, dma_addr, old_addr; 356 size_t len, size; 357 u32 nbytes = 0; 358 int i; 359 360 /* calculate the total size in this desc */ 361 for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) { 362 nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes); 363 if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE)) 364 nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes); 365 len += nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter); 366 } 367 368 if (!in_progress) 369 return len; 370 371 /* 64bit read is not atomic, need read retry when high 32bit changed */ 372 do { 373 if (dir == DMA_MEM_TO_DEV) { 374 old_addr = edma_read_tcdreg(fsl_chan, saddr); 375 cur_addr = edma_read_tcdreg(fsl_chan, saddr); 376 } else { 377 old_addr = edma_read_tcdreg(fsl_chan, daddr); 378 cur_addr = edma_read_tcdreg(fsl_chan, daddr); 379 } 380 } while (upper_32_bits(cur_addr) != upper_32_bits(old_addr)); 381 382 /* figure out the finished and calculate the residue */ 383 for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { 384 nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes); 385 if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE)) 386 nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes); 387 388 size = nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter); 389 390 if (dir == DMA_MEM_TO_DEV) 391 dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, saddr); 392 else 393 dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, daddr); 394 395 len -= size; 396 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { 397 len += dma_addr + size - cur_addr; 398 break; 399 } 400 } 401 402 return len; 403 } 404 405 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 406 dma_cookie_t cookie, struct dma_tx_state *txstate) 407 { 408 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 409 struct virt_dma_desc *vdesc; 410 enum dma_status status; 411 unsigned long flags; 412 413 status = dma_cookie_status(chan, cookie, txstate); 414 if (status == DMA_COMPLETE) 415 return status; 416 417 if (!txstate) 418 return fsl_chan->status; 419 420 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 421 vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); 422 if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) 423 txstate->residue = 424 fsl_edma_desc_residue(fsl_chan, vdesc, true); 425 else if (vdesc) 426 txstate->residue = 427 fsl_edma_desc_residue(fsl_chan, vdesc, false); 428 else 429 txstate->residue = 0; 430 431 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 432 433 return fsl_chan->status; 434 } 435 436 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, void *tcd) 437 { 438 u16 csr = 0; 439 440 /* 441 * TCD parameters are stored in struct fsl_edma_hw_tcd in little 442 * endian format. However, we need to load the TCD registers in 443 * big- or little-endian obeying the eDMA engine model endian, 444 * and this is performed from specific edma_write functions 445 */ 446 edma_write_tcdreg(fsl_chan, 0, csr); 447 448 edma_cp_tcd_to_reg(fsl_chan, tcd, saddr); 449 edma_cp_tcd_to_reg(fsl_chan, tcd, daddr); 450 451 edma_cp_tcd_to_reg(fsl_chan, tcd, attr); 452 edma_cp_tcd_to_reg(fsl_chan, tcd, soff); 453 454 edma_cp_tcd_to_reg(fsl_chan, tcd, nbytes); 455 edma_cp_tcd_to_reg(fsl_chan, tcd, slast); 456 457 edma_cp_tcd_to_reg(fsl_chan, tcd, citer); 458 edma_cp_tcd_to_reg(fsl_chan, tcd, biter); 459 edma_cp_tcd_to_reg(fsl_chan, tcd, doff); 460 461 edma_cp_tcd_to_reg(fsl_chan, tcd, dlast_sga); 462 463 csr = fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr); 464 465 if (fsl_chan->is_sw) { 466 csr |= EDMA_TCD_CSR_START; 467 fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr); 468 } 469 470 /* 471 * Must clear CHn_CSR[DONE] bit before enable TCDn_CSR[ESG] at EDMAv3 472 * eDMAv4 have not such requirement. 473 * Change MLINK need clear CHn_CSR[DONE] for both eDMAv3 and eDMAv4. 474 */ 475 if (((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_SG) && 476 (csr & EDMA_TCD_CSR_E_SG)) || 477 ((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_LINK) && 478 (csr & EDMA_TCD_CSR_E_LINK))) 479 edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr); 480 481 482 edma_cp_tcd_to_reg(fsl_chan, tcd, csr); 483 } 484 485 static inline 486 void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan, 487 struct fsl_edma_hw_tcd *tcd, dma_addr_t src, dma_addr_t dst, 488 u16 attr, u16 soff, u32 nbytes, dma_addr_t slast, u16 citer, 489 u16 biter, u16 doff, dma_addr_t dlast_sga, bool major_int, 490 bool disable_req, bool enable_sg) 491 { 492 struct dma_slave_config *cfg = &fsl_chan->cfg; 493 u16 csr = 0; 494 u32 burst; 495 496 /* 497 * eDMA hardware SGs require the TCDs to be stored in little 498 * endian format irrespective of the register endian model. 499 * So we put the value in little endian in memory, waiting 500 * for fsl_edma_set_tcd_regs doing the swap. 501 */ 502 fsl_edma_set_tcd_to_le(fsl_chan, tcd, src, saddr); 503 fsl_edma_set_tcd_to_le(fsl_chan, tcd, dst, daddr); 504 505 fsl_edma_set_tcd_to_le(fsl_chan, tcd, attr, attr); 506 507 fsl_edma_set_tcd_to_le(fsl_chan, tcd, soff, soff); 508 509 if (fsl_chan->is_multi_fifo) { 510 /* set mloff to support multiple fifo */ 511 burst = cfg->direction == DMA_DEV_TO_MEM ? 512 cfg->src_maxburst : cfg->dst_maxburst; 513 nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4)); 514 /* enable DMLOE/SMLOE */ 515 if (cfg->direction == DMA_MEM_TO_DEV) { 516 nbytes |= EDMA_V3_TCD_NBYTES_DMLOE; 517 nbytes &= ~EDMA_V3_TCD_NBYTES_SMLOE; 518 } else { 519 nbytes |= EDMA_V3_TCD_NBYTES_SMLOE; 520 nbytes &= ~EDMA_V3_TCD_NBYTES_DMLOE; 521 } 522 } 523 524 fsl_edma_set_tcd_to_le(fsl_chan, tcd, nbytes, nbytes); 525 fsl_edma_set_tcd_to_le(fsl_chan, tcd, slast, slast); 526 527 fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_CITER_CITER(citer), citer); 528 fsl_edma_set_tcd_to_le(fsl_chan, tcd, doff, doff); 529 530 fsl_edma_set_tcd_to_le(fsl_chan, tcd, dlast_sga, dlast_sga); 531 532 fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_BITER_BITER(biter), biter); 533 534 if (major_int) 535 csr |= EDMA_TCD_CSR_INT_MAJOR; 536 537 if (disable_req) 538 csr |= EDMA_TCD_CSR_D_REQ; 539 540 if (enable_sg) 541 csr |= EDMA_TCD_CSR_E_SG; 542 543 if (fsl_chan->is_rxchan) 544 csr |= EDMA_TCD_CSR_ACTIVE; 545 546 if (fsl_chan->is_sw) 547 csr |= EDMA_TCD_CSR_START; 548 549 fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr); 550 } 551 552 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, 553 int sg_len) 554 { 555 struct fsl_edma_desc *fsl_desc; 556 int i; 557 558 fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT); 559 if (!fsl_desc) 560 return NULL; 561 562 fsl_desc->echan = fsl_chan; 563 fsl_desc->n_tcds = sg_len; 564 for (i = 0; i < sg_len; i++) { 565 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, 566 GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); 567 if (!fsl_desc->tcd[i].vtcd) 568 goto err; 569 } 570 return fsl_desc; 571 572 err: 573 while (--i >= 0) 574 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, 575 fsl_desc->tcd[i].ptcd); 576 kfree(fsl_desc); 577 return NULL; 578 } 579 580 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 581 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 582 size_t period_len, enum dma_transfer_direction direction, 583 unsigned long flags) 584 { 585 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 586 struct fsl_edma_desc *fsl_desc; 587 dma_addr_t dma_buf_next; 588 bool major_int = true; 589 int sg_len, i; 590 dma_addr_t src_addr, dst_addr, last_sg; 591 u16 soff, doff, iter; 592 u32 nbytes; 593 594 if (!is_slave_direction(direction)) 595 return NULL; 596 597 if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) 598 return NULL; 599 600 sg_len = buf_len / period_len; 601 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 602 if (!fsl_desc) 603 return NULL; 604 fsl_desc->iscyclic = true; 605 fsl_desc->dirn = direction; 606 607 dma_buf_next = dma_addr; 608 if (direction == DMA_MEM_TO_DEV) { 609 fsl_chan->attr = 610 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); 611 nbytes = fsl_chan->cfg.dst_addr_width * 612 fsl_chan->cfg.dst_maxburst; 613 } else { 614 fsl_chan->attr = 615 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); 616 nbytes = fsl_chan->cfg.src_addr_width * 617 fsl_chan->cfg.src_maxburst; 618 } 619 620 iter = period_len / nbytes; 621 622 for (i = 0; i < sg_len; i++) { 623 if (dma_buf_next >= dma_addr + buf_len) 624 dma_buf_next = dma_addr; 625 626 /* get next sg's physical address */ 627 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 628 629 if (direction == DMA_MEM_TO_DEV) { 630 src_addr = dma_buf_next; 631 dst_addr = fsl_chan->dma_dev_addr; 632 soff = fsl_chan->cfg.dst_addr_width; 633 doff = fsl_chan->is_multi_fifo ? 4 : 0; 634 } else if (direction == DMA_DEV_TO_MEM) { 635 src_addr = fsl_chan->dma_dev_addr; 636 dst_addr = dma_buf_next; 637 soff = fsl_chan->is_multi_fifo ? 4 : 0; 638 doff = fsl_chan->cfg.src_addr_width; 639 } else { 640 /* DMA_DEV_TO_DEV */ 641 src_addr = fsl_chan->cfg.src_addr; 642 dst_addr = fsl_chan->cfg.dst_addr; 643 soff = doff = 0; 644 major_int = false; 645 } 646 647 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, dst_addr, 648 fsl_chan->attr, soff, nbytes, 0, iter, 649 iter, doff, last_sg, major_int, false, true); 650 dma_buf_next += period_len; 651 } 652 653 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 654 } 655 656 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 657 struct dma_chan *chan, struct scatterlist *sgl, 658 unsigned int sg_len, enum dma_transfer_direction direction, 659 unsigned long flags, void *context) 660 { 661 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 662 struct fsl_edma_desc *fsl_desc; 663 struct scatterlist *sg; 664 dma_addr_t src_addr, dst_addr, last_sg; 665 u16 soff, doff, iter; 666 u32 nbytes; 667 int i; 668 669 if (!is_slave_direction(direction)) 670 return NULL; 671 672 if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) 673 return NULL; 674 675 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 676 if (!fsl_desc) 677 return NULL; 678 fsl_desc->iscyclic = false; 679 fsl_desc->dirn = direction; 680 681 if (direction == DMA_MEM_TO_DEV) { 682 fsl_chan->attr = 683 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); 684 nbytes = fsl_chan->cfg.dst_addr_width * 685 fsl_chan->cfg.dst_maxburst; 686 } else { 687 fsl_chan->attr = 688 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); 689 nbytes = fsl_chan->cfg.src_addr_width * 690 fsl_chan->cfg.src_maxburst; 691 } 692 693 for_each_sg(sgl, sg, sg_len, i) { 694 if (direction == DMA_MEM_TO_DEV) { 695 src_addr = sg_dma_address(sg); 696 dst_addr = fsl_chan->dma_dev_addr; 697 soff = fsl_chan->cfg.dst_addr_width; 698 doff = 0; 699 } else if (direction == DMA_DEV_TO_MEM) { 700 src_addr = fsl_chan->dma_dev_addr; 701 dst_addr = sg_dma_address(sg); 702 soff = 0; 703 doff = fsl_chan->cfg.src_addr_width; 704 } else { 705 /* DMA_DEV_TO_DEV */ 706 src_addr = fsl_chan->cfg.src_addr; 707 dst_addr = fsl_chan->cfg.dst_addr; 708 soff = 0; 709 doff = 0; 710 } 711 712 /* 713 * Choose the suitable burst length if sg_dma_len is not 714 * multiple of burst length so that the whole transfer length is 715 * multiple of minor loop(burst length). 716 */ 717 if (sg_dma_len(sg) % nbytes) { 718 u32 width = (direction == DMA_DEV_TO_MEM) ? doff : soff; 719 u32 burst = (direction == DMA_DEV_TO_MEM) ? 720 fsl_chan->cfg.src_maxburst : 721 fsl_chan->cfg.dst_maxburst; 722 int j; 723 724 for (j = burst; j > 1; j--) { 725 if (!(sg_dma_len(sg) % (j * width))) { 726 nbytes = j * width; 727 break; 728 } 729 } 730 /* Set burst size as 1 if there's no suitable one */ 731 if (j == 1) 732 nbytes = width; 733 } 734 iter = sg_dma_len(sg) / nbytes; 735 if (i < sg_len - 1) { 736 last_sg = fsl_desc->tcd[(i + 1)].ptcd; 737 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, 738 dst_addr, fsl_chan->attr, soff, 739 nbytes, 0, iter, iter, doff, last_sg, 740 false, false, true); 741 } else { 742 last_sg = 0; 743 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, 744 dst_addr, fsl_chan->attr, soff, 745 nbytes, 0, iter, iter, doff, last_sg, 746 true, true, false); 747 } 748 } 749 750 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 751 } 752 753 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan, 754 dma_addr_t dma_dst, dma_addr_t dma_src, 755 size_t len, unsigned long flags) 756 { 757 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 758 struct fsl_edma_desc *fsl_desc; 759 760 fsl_desc = fsl_edma_alloc_desc(fsl_chan, 1); 761 if (!fsl_desc) 762 return NULL; 763 fsl_desc->iscyclic = false; 764 765 fsl_chan->is_sw = true; 766 767 /* To match with copy_align and max_seg_size so 1 tcd is enough */ 768 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst, 769 fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES), 770 32, len, 0, 1, 1, 32, 0, true, true, false); 771 772 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 773 } 774 775 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) 776 { 777 struct virt_dma_desc *vdesc; 778 779 lockdep_assert_held(&fsl_chan->vchan.lock); 780 781 vdesc = vchan_next_desc(&fsl_chan->vchan); 782 if (!vdesc) 783 return; 784 fsl_chan->edesc = to_fsl_edma_desc(vdesc); 785 fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); 786 fsl_edma_enable_request(fsl_chan); 787 fsl_chan->status = DMA_IN_PROGRESS; 788 fsl_chan->idle = false; 789 } 790 791 void fsl_edma_issue_pending(struct dma_chan *chan) 792 { 793 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 794 unsigned long flags; 795 796 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 797 798 if (unlikely(fsl_chan->pm_state != RUNNING)) { 799 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 800 /* cannot submit due to suspend */ 801 return; 802 } 803 804 if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) 805 fsl_edma_xfer_desc(fsl_chan); 806 807 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 808 } 809 810 int fsl_edma_alloc_chan_resources(struct dma_chan *chan) 811 { 812 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 813 814 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) 815 clk_prepare_enable(fsl_chan->clk); 816 817 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, 818 fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ? 819 sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd), 820 32, 0); 821 return 0; 822 } 823 824 void fsl_edma_free_chan_resources(struct dma_chan *chan) 825 { 826 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 827 struct fsl_edma_engine *edma = fsl_chan->edma; 828 unsigned long flags; 829 LIST_HEAD(head); 830 831 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 832 fsl_edma_disable_request(fsl_chan); 833 if (edma->drvdata->dmamuxs) 834 fsl_edma_chan_mux(fsl_chan, 0, false); 835 fsl_chan->edesc = NULL; 836 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 837 fsl_edma_unprep_slave_dma(fsl_chan); 838 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 839 840 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 841 dma_pool_destroy(fsl_chan->tcd_pool); 842 fsl_chan->tcd_pool = NULL; 843 fsl_chan->is_sw = false; 844 fsl_chan->srcid = 0; 845 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) 846 clk_disable_unprepare(fsl_chan->clk); 847 } 848 849 void fsl_edma_cleanup_vchan(struct dma_device *dmadev) 850 { 851 struct fsl_edma_chan *chan, *_chan; 852 853 list_for_each_entry_safe(chan, _chan, 854 &dmadev->channels, vchan.chan.device_node) { 855 list_del(&chan->vchan.chan.device_node); 856 tasklet_kill(&chan->vchan.task); 857 } 858 } 859 860 /* 861 * On the 32 channels Vybrid/mpc577x edma version, register offsets are 862 * different compared to ColdFire mcf5441x 64 channels edma. 863 * 864 * This function sets up register offsets as per proper declared version 865 * so must be called in xxx_edma_probe() just after setting the 866 * edma "version" and "membase" appropriately. 867 */ 868 void fsl_edma_setup_regs(struct fsl_edma_engine *edma) 869 { 870 bool is64 = !!(edma->drvdata->flags & FSL_EDMA_DRV_EDMA64); 871 872 edma->regs.cr = edma->membase + EDMA_CR; 873 edma->regs.es = edma->membase + EDMA_ES; 874 edma->regs.erql = edma->membase + EDMA_ERQ; 875 edma->regs.eeil = edma->membase + EDMA_EEI; 876 877 edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); 878 edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); 879 edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); 880 edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); 881 edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); 882 edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); 883 edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); 884 edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); 885 edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); 886 edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); 887 888 if (is64) { 889 edma->regs.erqh = edma->membase + EDMA64_ERQH; 890 edma->regs.eeih = edma->membase + EDMA64_EEIH; 891 edma->regs.errh = edma->membase + EDMA64_ERRH; 892 edma->regs.inth = edma->membase + EDMA64_INTH; 893 } 894 } 895 896 MODULE_LICENSE("GPL v2"); 897