1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> 5 6 #include <linux/cleanup.h> 7 #include <linux/clk.h> 8 #include <linux/dmapool.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/pm_domain.h> 14 15 #include "fsl-edma-common.h" 16 17 #define EDMA_CR 0x00 18 #define EDMA_ES 0x04 19 #define EDMA_ERQ 0x0C 20 #define EDMA_EEI 0x14 21 #define EDMA_SERQ 0x1B 22 #define EDMA_CERQ 0x1A 23 #define EDMA_SEEI 0x19 24 #define EDMA_CEEI 0x18 25 #define EDMA_CINT 0x1F 26 #define EDMA_CERR 0x1E 27 #define EDMA_SSRT 0x1D 28 #define EDMA_CDNE 0x1C 29 #define EDMA_INTR 0x24 30 #define EDMA_ERR 0x2C 31 32 #define EDMA64_ERQH 0x08 33 #define EDMA64_EEIH 0x10 34 #define EDMA64_SERQ 0x18 35 #define EDMA64_CERQ 0x19 36 #define EDMA64_SEEI 0x1a 37 #define EDMA64_CEEI 0x1b 38 #define EDMA64_CINT 0x1c 39 #define EDMA64_CERR 0x1d 40 #define EDMA64_SSRT 0x1e 41 #define EDMA64_CDNE 0x1f 42 #define EDMA64_INTH 0x20 43 #define EDMA64_INTL 0x24 44 #define EDMA64_ERRH 0x28 45 #define EDMA64_ERRL 0x2c 46 47 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan) 48 { 49 spin_lock(&fsl_chan->vchan.lock); 50 51 if (!fsl_chan->edesc) { 52 /* terminate_all called before */ 53 spin_unlock(&fsl_chan->vchan.lock); 54 return; 55 } 56 57 if (!fsl_chan->edesc->iscyclic) { 58 list_del(&fsl_chan->edesc->vdesc.node); 59 vchan_cookie_complete(&fsl_chan->edesc->vdesc); 60 fsl_chan->edesc = NULL; 61 fsl_chan->status = DMA_COMPLETE; 62 fsl_chan->idle = true; 63 } else { 64 vchan_cyclic_callback(&fsl_chan->edesc->vdesc); 65 } 66 67 if (!fsl_chan->edesc) 68 fsl_edma_xfer_desc(fsl_chan); 69 70 spin_unlock(&fsl_chan->vchan.lock); 71 } 72 73 static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan) 74 { 75 u32 val, flags; 76 77 flags = fsl_edma_drvflags(fsl_chan); 78 val = edma_readl_chreg(fsl_chan, ch_sbr); 79 /* Remote/local swapped wrongly on iMX8 QM Audio edma */ 80 if (flags & FSL_EDMA_DRV_QUIRK_SWAPPED) { 81 if (!fsl_chan->is_rxchan) 82 val |= EDMA_V3_CH_SBR_RD; 83 else 84 val |= EDMA_V3_CH_SBR_WR; 85 } else { 86 if (fsl_chan->is_rxchan) 87 val |= EDMA_V3_CH_SBR_RD; 88 else 89 val |= EDMA_V3_CH_SBR_WR; 90 } 91 92 if (fsl_chan->is_remote) 93 val &= ~(EDMA_V3_CH_SBR_RD | EDMA_V3_CH_SBR_WR); 94 95 edma_writel_chreg(fsl_chan, val, ch_sbr); 96 97 if (flags & FSL_EDMA_DRV_HAS_CHMUX) { 98 /* 99 * ch_mux: With the exception of 0, attempts to write a value 100 * already in use will be forced to 0. 101 */ 102 if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr)) 103 edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr); 104 } 105 106 val = edma_readl_chreg(fsl_chan, ch_csr); 107 val |= EDMA_V3_CH_CSR_ERQ; 108 edma_writel_chreg(fsl_chan, val, ch_csr); 109 } 110 111 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) 112 { 113 struct edma_regs *regs = &fsl_chan->edma->regs; 114 u32 ch = fsl_chan->vchan.chan.chan_id; 115 116 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) 117 return fsl_edma3_enable_request(fsl_chan); 118 119 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { 120 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); 121 edma_writeb(fsl_chan->edma, ch, regs->serq); 122 } else { 123 /* ColdFire is big endian, and accesses natively 124 * big endian I/O peripherals 125 */ 126 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); 127 iowrite8(ch, regs->serq); 128 } 129 } 130 131 static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan) 132 { 133 u32 val = edma_readl_chreg(fsl_chan, ch_csr); 134 u32 flags; 135 136 flags = fsl_edma_drvflags(fsl_chan); 137 138 if (flags & FSL_EDMA_DRV_HAS_CHMUX) 139 edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr); 140 141 val &= ~EDMA_V3_CH_CSR_ERQ; 142 edma_writel_chreg(fsl_chan, val, ch_csr); 143 } 144 145 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) 146 { 147 struct edma_regs *regs = &fsl_chan->edma->regs; 148 u32 ch = fsl_chan->vchan.chan.chan_id; 149 150 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) 151 return fsl_edma3_disable_request(fsl_chan); 152 153 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { 154 edma_writeb(fsl_chan->edma, ch, regs->cerq); 155 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); 156 } else { 157 /* ColdFire is big endian, and accesses natively 158 * big endian I/O peripherals 159 */ 160 iowrite8(ch, regs->cerq); 161 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); 162 } 163 } 164 165 static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr, 166 u32 off, u32 slot, bool enable) 167 { 168 u8 val8; 169 170 if (enable) 171 val8 = EDMAMUX_CHCFG_ENBL | slot; 172 else 173 val8 = EDMAMUX_CHCFG_DIS; 174 175 iowrite8(val8, addr + off); 176 } 177 178 static void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *addr, 179 u32 off, u32 slot, bool enable) 180 { 181 u32 val; 182 183 if (enable) 184 val = EDMAMUX_CHCFG_ENBL << 24 | slot; 185 else 186 val = EDMAMUX_CHCFG_DIS; 187 188 iowrite32(val, addr + off * 4); 189 } 190 191 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 192 unsigned int slot, bool enable) 193 { 194 u32 ch = fsl_chan->vchan.chan.chan_id; 195 void __iomem *muxaddr; 196 unsigned int chans_per_mux, ch_off; 197 int endian_diff[4] = {3, 1, -1, -3}; 198 u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; 199 200 if (!dmamux_nr) 201 return; 202 203 chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; 204 ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; 205 206 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_MUX_SWAP) 207 ch_off += endian_diff[ch_off % 4]; 208 209 muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; 210 slot = EDMAMUX_CHCFG_SOURCE(slot); 211 212 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_CONFIG32) 213 mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable); 214 else 215 mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable); 216 } 217 218 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) 219 { 220 u32 val; 221 222 if (addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 223 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 224 225 val = ffs(addr_width) - 1; 226 return val | (val << 8); 227 } 228 229 void fsl_edma_free_desc(struct virt_dma_desc *vdesc) 230 { 231 struct fsl_edma_desc *fsl_desc; 232 int i; 233 234 fsl_desc = to_fsl_edma_desc(vdesc); 235 for (i = 0; i < fsl_desc->n_tcds; i++) 236 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, 237 fsl_desc->tcd[i].ptcd); 238 kfree(fsl_desc); 239 } 240 241 int fsl_edma_terminate_all(struct dma_chan *chan) 242 { 243 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 244 unsigned long flags; 245 LIST_HEAD(head); 246 247 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 248 fsl_edma_disable_request(fsl_chan); 249 fsl_chan->edesc = NULL; 250 fsl_chan->idle = true; 251 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 252 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 253 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 254 255 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_PD) 256 pm_runtime_allow(fsl_chan->pd_dev); 257 258 return 0; 259 } 260 261 int fsl_edma_pause(struct dma_chan *chan) 262 { 263 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 264 unsigned long flags; 265 266 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 267 if (fsl_chan->edesc) { 268 fsl_edma_disable_request(fsl_chan); 269 fsl_chan->status = DMA_PAUSED; 270 fsl_chan->idle = true; 271 } 272 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 273 return 0; 274 } 275 276 int fsl_edma_resume(struct dma_chan *chan) 277 { 278 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 279 unsigned long flags; 280 281 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 282 if (fsl_chan->edesc) { 283 fsl_edma_enable_request(fsl_chan); 284 fsl_chan->status = DMA_IN_PROGRESS; 285 fsl_chan->idle = false; 286 } 287 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 288 return 0; 289 } 290 291 static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan) 292 { 293 if (fsl_chan->dma_dir != DMA_NONE) 294 dma_unmap_resource(fsl_chan->vchan.chan.device->dev, 295 fsl_chan->dma_dev_addr, 296 fsl_chan->dma_dev_size, 297 fsl_chan->dma_dir, 0); 298 fsl_chan->dma_dir = DMA_NONE; 299 } 300 301 static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan, 302 enum dma_transfer_direction dir) 303 { 304 struct device *dev = fsl_chan->vchan.chan.device->dev; 305 enum dma_data_direction dma_dir; 306 phys_addr_t addr = 0; 307 u32 size = 0; 308 309 switch (dir) { 310 case DMA_MEM_TO_DEV: 311 dma_dir = DMA_FROM_DEVICE; 312 addr = fsl_chan->cfg.dst_addr; 313 size = fsl_chan->cfg.dst_maxburst; 314 break; 315 case DMA_DEV_TO_MEM: 316 dma_dir = DMA_TO_DEVICE; 317 addr = fsl_chan->cfg.src_addr; 318 size = fsl_chan->cfg.src_maxburst; 319 break; 320 default: 321 dma_dir = DMA_NONE; 322 break; 323 } 324 325 /* Already mapped for this config? */ 326 if (fsl_chan->dma_dir == dma_dir) 327 return true; 328 329 fsl_edma_unprep_slave_dma(fsl_chan); 330 331 fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0); 332 if (dma_mapping_error(dev, fsl_chan->dma_dev_addr)) 333 return false; 334 fsl_chan->dma_dev_size = size; 335 fsl_chan->dma_dir = dma_dir; 336 337 return true; 338 } 339 340 int fsl_edma_slave_config(struct dma_chan *chan, 341 struct dma_slave_config *cfg) 342 { 343 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 344 345 memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg)); 346 fsl_edma_unprep_slave_dma(fsl_chan); 347 348 return 0; 349 } 350 351 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, 352 struct virt_dma_desc *vdesc, bool in_progress) 353 { 354 struct fsl_edma_desc *edesc = fsl_chan->edesc; 355 enum dma_transfer_direction dir = edesc->dirn; 356 dma_addr_t cur_addr, dma_addr, old_addr; 357 size_t len, size; 358 u32 nbytes = 0; 359 int i; 360 361 /* calculate the total size in this desc */ 362 for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) { 363 nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes); 364 if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE)) 365 nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes); 366 len += nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter); 367 } 368 369 if (!in_progress) 370 return len; 371 372 /* 64bit read is not atomic, need read retry when high 32bit changed */ 373 do { 374 if (dir == DMA_MEM_TO_DEV) { 375 old_addr = edma_read_tcdreg(fsl_chan, saddr); 376 cur_addr = edma_read_tcdreg(fsl_chan, saddr); 377 } else { 378 old_addr = edma_read_tcdreg(fsl_chan, daddr); 379 cur_addr = edma_read_tcdreg(fsl_chan, daddr); 380 } 381 } while (upper_32_bits(cur_addr) != upper_32_bits(old_addr)); 382 383 /* figure out the finished and calculate the residue */ 384 for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { 385 nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes); 386 if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE)) 387 nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes); 388 389 size = nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter); 390 391 if (dir == DMA_MEM_TO_DEV) 392 dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, saddr); 393 else 394 dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, daddr); 395 396 len -= size; 397 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { 398 len += dma_addr + size - cur_addr; 399 break; 400 } 401 } 402 403 return len; 404 } 405 406 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 407 dma_cookie_t cookie, struct dma_tx_state *txstate) 408 { 409 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 410 struct virt_dma_desc *vdesc; 411 enum dma_status status; 412 unsigned long flags; 413 414 status = dma_cookie_status(chan, cookie, txstate); 415 if (status == DMA_COMPLETE) 416 return status; 417 418 if (!txstate) 419 return fsl_chan->status; 420 421 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 422 vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); 423 if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) 424 txstate->residue = 425 fsl_edma_desc_residue(fsl_chan, vdesc, true); 426 else if (vdesc) 427 txstate->residue = 428 fsl_edma_desc_residue(fsl_chan, vdesc, false); 429 else 430 txstate->residue = 0; 431 432 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 433 434 return fsl_chan->status; 435 } 436 437 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, void *tcd) 438 { 439 u16 csr = 0; 440 441 /* 442 * TCD parameters are stored in struct fsl_edma_hw_tcd in little 443 * endian format. However, we need to load the TCD registers in 444 * big- or little-endian obeying the eDMA engine model endian, 445 * and this is performed from specific edma_write functions 446 */ 447 edma_write_tcdreg(fsl_chan, 0, csr); 448 449 edma_cp_tcd_to_reg(fsl_chan, tcd, saddr); 450 edma_cp_tcd_to_reg(fsl_chan, tcd, daddr); 451 452 edma_cp_tcd_to_reg(fsl_chan, tcd, attr); 453 edma_cp_tcd_to_reg(fsl_chan, tcd, soff); 454 455 edma_cp_tcd_to_reg(fsl_chan, tcd, nbytes); 456 edma_cp_tcd_to_reg(fsl_chan, tcd, slast); 457 458 edma_cp_tcd_to_reg(fsl_chan, tcd, citer); 459 edma_cp_tcd_to_reg(fsl_chan, tcd, biter); 460 edma_cp_tcd_to_reg(fsl_chan, tcd, doff); 461 462 edma_cp_tcd_to_reg(fsl_chan, tcd, dlast_sga); 463 464 csr = fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr); 465 466 if (fsl_chan->is_sw) { 467 csr |= EDMA_TCD_CSR_START; 468 fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr); 469 } 470 471 /* 472 * Must clear CHn_CSR[DONE] bit before enable TCDn_CSR[ESG] at EDMAv3 473 * eDMAv4 have not such requirement. 474 * Change MLINK need clear CHn_CSR[DONE] for both eDMAv3 and eDMAv4. 475 */ 476 if (((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_SG) && 477 (csr & EDMA_TCD_CSR_E_SG)) || 478 ((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_LINK) && 479 (csr & EDMA_TCD_CSR_E_LINK))) 480 edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr); 481 482 483 edma_cp_tcd_to_reg(fsl_chan, tcd, csr); 484 } 485 486 static inline 487 void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan, 488 struct fsl_edma_hw_tcd *tcd, dma_addr_t src, dma_addr_t dst, 489 u16 attr, u16 soff, u32 nbytes, dma_addr_t slast, u16 citer, 490 u16 biter, u16 doff, dma_addr_t dlast_sga, bool major_int, 491 bool disable_req, bool enable_sg) 492 { 493 struct dma_slave_config *cfg = &fsl_chan->cfg; 494 u16 csr = 0; 495 u32 burst; 496 497 /* 498 * eDMA hardware SGs require the TCDs to be stored in little 499 * endian format irrespective of the register endian model. 500 * So we put the value in little endian in memory, waiting 501 * for fsl_edma_set_tcd_regs doing the swap. 502 */ 503 fsl_edma_set_tcd_to_le(fsl_chan, tcd, src, saddr); 504 fsl_edma_set_tcd_to_le(fsl_chan, tcd, dst, daddr); 505 506 fsl_edma_set_tcd_to_le(fsl_chan, tcd, attr, attr); 507 508 fsl_edma_set_tcd_to_le(fsl_chan, tcd, soff, soff); 509 510 if (fsl_chan->is_multi_fifo) { 511 /* set mloff to support multiple fifo */ 512 burst = cfg->direction == DMA_DEV_TO_MEM ? 513 cfg->src_maxburst : cfg->dst_maxburst; 514 nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4)); 515 /* enable DMLOE/SMLOE */ 516 if (cfg->direction == DMA_MEM_TO_DEV) { 517 nbytes |= EDMA_V3_TCD_NBYTES_DMLOE; 518 nbytes &= ~EDMA_V3_TCD_NBYTES_SMLOE; 519 } else { 520 nbytes |= EDMA_V3_TCD_NBYTES_SMLOE; 521 nbytes &= ~EDMA_V3_TCD_NBYTES_DMLOE; 522 } 523 } 524 525 fsl_edma_set_tcd_to_le(fsl_chan, tcd, nbytes, nbytes); 526 fsl_edma_set_tcd_to_le(fsl_chan, tcd, slast, slast); 527 528 fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_CITER_CITER(citer), citer); 529 fsl_edma_set_tcd_to_le(fsl_chan, tcd, doff, doff); 530 531 fsl_edma_set_tcd_to_le(fsl_chan, tcd, dlast_sga, dlast_sga); 532 533 fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_BITER_BITER(biter), biter); 534 535 if (major_int) 536 csr |= EDMA_TCD_CSR_INT_MAJOR; 537 538 if (disable_req) 539 csr |= EDMA_TCD_CSR_D_REQ; 540 541 if (enable_sg) 542 csr |= EDMA_TCD_CSR_E_SG; 543 544 if (fsl_chan->is_rxchan) 545 csr |= EDMA_TCD_CSR_ACTIVE; 546 547 if (fsl_chan->is_sw) 548 csr |= EDMA_TCD_CSR_START; 549 550 fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr); 551 } 552 553 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, 554 int sg_len) 555 { 556 struct fsl_edma_desc *fsl_desc; 557 int i; 558 559 fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT); 560 if (!fsl_desc) 561 return NULL; 562 563 fsl_desc->echan = fsl_chan; 564 fsl_desc->n_tcds = sg_len; 565 for (i = 0; i < sg_len; i++) { 566 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, 567 GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); 568 if (!fsl_desc->tcd[i].vtcd) 569 goto err; 570 } 571 return fsl_desc; 572 573 err: 574 while (--i >= 0) 575 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, 576 fsl_desc->tcd[i].ptcd); 577 kfree(fsl_desc); 578 return NULL; 579 } 580 581 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 582 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 583 size_t period_len, enum dma_transfer_direction direction, 584 unsigned long flags) 585 { 586 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 587 struct fsl_edma_desc *fsl_desc; 588 dma_addr_t dma_buf_next; 589 bool major_int = true; 590 int sg_len, i; 591 dma_addr_t src_addr, dst_addr, last_sg; 592 u16 soff, doff, iter; 593 u32 nbytes; 594 595 if (!is_slave_direction(direction)) 596 return NULL; 597 598 if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) 599 return NULL; 600 601 sg_len = buf_len / period_len; 602 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 603 if (!fsl_desc) 604 return NULL; 605 fsl_desc->iscyclic = true; 606 fsl_desc->dirn = direction; 607 608 dma_buf_next = dma_addr; 609 if (direction == DMA_MEM_TO_DEV) { 610 fsl_chan->attr = 611 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); 612 nbytes = fsl_chan->cfg.dst_addr_width * 613 fsl_chan->cfg.dst_maxburst; 614 } else { 615 fsl_chan->attr = 616 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); 617 nbytes = fsl_chan->cfg.src_addr_width * 618 fsl_chan->cfg.src_maxburst; 619 } 620 621 iter = period_len / nbytes; 622 623 for (i = 0; i < sg_len; i++) { 624 if (dma_buf_next >= dma_addr + buf_len) 625 dma_buf_next = dma_addr; 626 627 /* get next sg's physical address */ 628 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 629 630 if (direction == DMA_MEM_TO_DEV) { 631 src_addr = dma_buf_next; 632 dst_addr = fsl_chan->dma_dev_addr; 633 soff = fsl_chan->cfg.dst_addr_width; 634 doff = fsl_chan->is_multi_fifo ? 4 : 0; 635 } else if (direction == DMA_DEV_TO_MEM) { 636 src_addr = fsl_chan->dma_dev_addr; 637 dst_addr = dma_buf_next; 638 soff = fsl_chan->is_multi_fifo ? 4 : 0; 639 doff = fsl_chan->cfg.src_addr_width; 640 } else { 641 /* DMA_DEV_TO_DEV */ 642 src_addr = fsl_chan->cfg.src_addr; 643 dst_addr = fsl_chan->cfg.dst_addr; 644 soff = doff = 0; 645 major_int = false; 646 } 647 648 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, dst_addr, 649 fsl_chan->attr, soff, nbytes, 0, iter, 650 iter, doff, last_sg, major_int, false, true); 651 dma_buf_next += period_len; 652 } 653 654 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 655 } 656 657 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 658 struct dma_chan *chan, struct scatterlist *sgl, 659 unsigned int sg_len, enum dma_transfer_direction direction, 660 unsigned long flags, void *context) 661 { 662 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 663 struct fsl_edma_desc *fsl_desc; 664 struct scatterlist *sg; 665 dma_addr_t src_addr, dst_addr, last_sg; 666 u16 soff, doff, iter; 667 u32 nbytes; 668 int i; 669 670 if (!is_slave_direction(direction)) 671 return NULL; 672 673 if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) 674 return NULL; 675 676 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 677 if (!fsl_desc) 678 return NULL; 679 fsl_desc->iscyclic = false; 680 fsl_desc->dirn = direction; 681 682 if (direction == DMA_MEM_TO_DEV) { 683 fsl_chan->attr = 684 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); 685 nbytes = fsl_chan->cfg.dst_addr_width * 686 fsl_chan->cfg.dst_maxburst; 687 } else { 688 fsl_chan->attr = 689 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); 690 nbytes = fsl_chan->cfg.src_addr_width * 691 fsl_chan->cfg.src_maxburst; 692 } 693 694 for_each_sg(sgl, sg, sg_len, i) { 695 if (direction == DMA_MEM_TO_DEV) { 696 src_addr = sg_dma_address(sg); 697 dst_addr = fsl_chan->dma_dev_addr; 698 soff = fsl_chan->cfg.dst_addr_width; 699 doff = 0; 700 } else if (direction == DMA_DEV_TO_MEM) { 701 src_addr = fsl_chan->dma_dev_addr; 702 dst_addr = sg_dma_address(sg); 703 soff = 0; 704 doff = fsl_chan->cfg.src_addr_width; 705 } else { 706 /* DMA_DEV_TO_DEV */ 707 src_addr = fsl_chan->cfg.src_addr; 708 dst_addr = fsl_chan->cfg.dst_addr; 709 soff = 0; 710 doff = 0; 711 } 712 713 /* 714 * Choose the suitable burst length if sg_dma_len is not 715 * multiple of burst length so that the whole transfer length is 716 * multiple of minor loop(burst length). 717 */ 718 if (sg_dma_len(sg) % nbytes) { 719 u32 width = (direction == DMA_DEV_TO_MEM) ? doff : soff; 720 u32 burst = (direction == DMA_DEV_TO_MEM) ? 721 fsl_chan->cfg.src_maxburst : 722 fsl_chan->cfg.dst_maxburst; 723 int j; 724 725 for (j = burst; j > 1; j--) { 726 if (!(sg_dma_len(sg) % (j * width))) { 727 nbytes = j * width; 728 break; 729 } 730 } 731 /* Set burst size as 1 if there's no suitable one */ 732 if (j == 1) 733 nbytes = width; 734 } 735 iter = sg_dma_len(sg) / nbytes; 736 if (i < sg_len - 1) { 737 last_sg = fsl_desc->tcd[(i + 1)].ptcd; 738 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, 739 dst_addr, fsl_chan->attr, soff, 740 nbytes, 0, iter, iter, doff, last_sg, 741 false, false, true); 742 } else { 743 last_sg = 0; 744 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, 745 dst_addr, fsl_chan->attr, soff, 746 nbytes, 0, iter, iter, doff, last_sg, 747 true, true, false); 748 } 749 } 750 751 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 752 } 753 754 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan, 755 dma_addr_t dma_dst, dma_addr_t dma_src, 756 size_t len, unsigned long flags) 757 { 758 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 759 struct fsl_edma_desc *fsl_desc; 760 761 fsl_desc = fsl_edma_alloc_desc(fsl_chan, 1); 762 if (!fsl_desc) 763 return NULL; 764 fsl_desc->iscyclic = false; 765 766 fsl_chan->is_sw = true; 767 768 /* To match with copy_align and max_seg_size so 1 tcd is enough */ 769 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst, 770 fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES), 771 32, len, 0, 1, 1, 32, 0, true, true, false); 772 773 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 774 } 775 776 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) 777 { 778 struct virt_dma_desc *vdesc; 779 780 lockdep_assert_held(&fsl_chan->vchan.lock); 781 782 vdesc = vchan_next_desc(&fsl_chan->vchan); 783 if (!vdesc) 784 return; 785 fsl_chan->edesc = to_fsl_edma_desc(vdesc); 786 fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); 787 fsl_edma_enable_request(fsl_chan); 788 fsl_chan->status = DMA_IN_PROGRESS; 789 fsl_chan->idle = false; 790 } 791 792 void fsl_edma_issue_pending(struct dma_chan *chan) 793 { 794 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 795 unsigned long flags; 796 797 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 798 799 if (unlikely(fsl_chan->pm_state != RUNNING)) { 800 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 801 /* cannot submit due to suspend */ 802 return; 803 } 804 805 if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) 806 fsl_edma_xfer_desc(fsl_chan); 807 808 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 809 } 810 811 int fsl_edma_alloc_chan_resources(struct dma_chan *chan) 812 { 813 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 814 815 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) 816 clk_prepare_enable(fsl_chan->clk); 817 818 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, 819 fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ? 820 sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd), 821 32, 0); 822 return 0; 823 } 824 825 void fsl_edma_free_chan_resources(struct dma_chan *chan) 826 { 827 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 828 struct fsl_edma_engine *edma = fsl_chan->edma; 829 unsigned long flags; 830 LIST_HEAD(head); 831 832 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 833 fsl_edma_disable_request(fsl_chan); 834 if (edma->drvdata->dmamuxs) 835 fsl_edma_chan_mux(fsl_chan, 0, false); 836 fsl_chan->edesc = NULL; 837 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 838 fsl_edma_unprep_slave_dma(fsl_chan); 839 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 840 841 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 842 dma_pool_destroy(fsl_chan->tcd_pool); 843 fsl_chan->tcd_pool = NULL; 844 fsl_chan->is_sw = false; 845 fsl_chan->srcid = 0; 846 if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) 847 clk_disable_unprepare(fsl_chan->clk); 848 } 849 850 void fsl_edma_cleanup_vchan(struct dma_device *dmadev) 851 { 852 struct fsl_edma_chan *chan, *_chan; 853 854 list_for_each_entry_safe(chan, _chan, 855 &dmadev->channels, vchan.chan.device_node) { 856 list_del(&chan->vchan.chan.device_node); 857 tasklet_kill(&chan->vchan.task); 858 } 859 } 860 861 /* 862 * On the 32 channels Vybrid/mpc577x edma version, register offsets are 863 * different compared to ColdFire mcf5441x 64 channels edma. 864 * 865 * This function sets up register offsets as per proper declared version 866 * so must be called in xxx_edma_probe() just after setting the 867 * edma "version" and "membase" appropriately. 868 */ 869 void fsl_edma_setup_regs(struct fsl_edma_engine *edma) 870 { 871 bool is64 = !!(edma->drvdata->flags & FSL_EDMA_DRV_EDMA64); 872 873 edma->regs.cr = edma->membase + EDMA_CR; 874 edma->regs.es = edma->membase + EDMA_ES; 875 edma->regs.erql = edma->membase + EDMA_ERQ; 876 edma->regs.eeil = edma->membase + EDMA_EEI; 877 878 edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); 879 edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); 880 edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); 881 edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); 882 edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); 883 edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); 884 edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); 885 edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); 886 edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); 887 edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); 888 889 if (is64) { 890 edma->regs.erqh = edma->membase + EDMA64_ERQH; 891 edma->regs.eeih = edma->membase + EDMA64_EEIH; 892 edma->regs.errh = edma->membase + EDMA64_ERRH; 893 edma->regs.inth = edma->membase + EDMA64_INTH; 894 } 895 } 896 897 MODULE_LICENSE("GPL v2"); 898