1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> 5 6 #include <linux/dmapool.h> 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 10 #include "fsl-edma-common.h" 11 12 #define EDMA_CR 0x00 13 #define EDMA_ES 0x04 14 #define EDMA_ERQ 0x0C 15 #define EDMA_EEI 0x14 16 #define EDMA_SERQ 0x1B 17 #define EDMA_CERQ 0x1A 18 #define EDMA_SEEI 0x19 19 #define EDMA_CEEI 0x18 20 #define EDMA_CINT 0x1F 21 #define EDMA_CERR 0x1E 22 #define EDMA_SSRT 0x1D 23 #define EDMA_CDNE 0x1C 24 #define EDMA_INTR 0x24 25 #define EDMA_ERR 0x2C 26 27 #define EDMA64_ERQH 0x08 28 #define EDMA64_EEIH 0x10 29 #define EDMA64_SERQ 0x18 30 #define EDMA64_CERQ 0x19 31 #define EDMA64_SEEI 0x1a 32 #define EDMA64_CEEI 0x1b 33 #define EDMA64_CINT 0x1c 34 #define EDMA64_CERR 0x1d 35 #define EDMA64_SSRT 0x1e 36 #define EDMA64_CDNE 0x1f 37 #define EDMA64_INTH 0x20 38 #define EDMA64_INTL 0x24 39 #define EDMA64_ERRH 0x28 40 #define EDMA64_ERRL 0x2c 41 42 #define EDMA_TCD 0x1000 43 44 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) 45 { 46 void __iomem *addr = fsl_chan->edma->membase; 47 u32 ch = fsl_chan->vchan.chan.chan_id; 48 49 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI); 50 edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ); 51 } 52 53 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) 54 { 55 void __iomem *addr = fsl_chan->edma->membase; 56 u32 ch = fsl_chan->vchan.chan.chan_id; 57 58 edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ); 59 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI); 60 } 61 EXPORT_SYMBOL_GPL(fsl_edma_disable_request); 62 63 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 64 unsigned int slot, bool enable) 65 { 66 u32 ch = fsl_chan->vchan.chan.chan_id; 67 void __iomem *muxaddr; 68 unsigned int chans_per_mux, ch_off; 69 70 chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR; 71 ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; 72 muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; 73 slot = EDMAMUX_CHCFG_SOURCE(slot); 74 75 if (enable) 76 iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off); 77 else 78 iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off); 79 } 80 EXPORT_SYMBOL_GPL(fsl_edma_chan_mux); 81 82 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) 83 { 84 switch (addr_width) { 85 case 1: 86 return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; 87 case 2: 88 return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; 89 case 4: 90 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 91 case 8: 92 return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; 93 default: 94 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 95 } 96 } 97 98 void fsl_edma_free_desc(struct virt_dma_desc *vdesc) 99 { 100 struct fsl_edma_desc *fsl_desc; 101 int i; 102 103 fsl_desc = to_fsl_edma_desc(vdesc); 104 for (i = 0; i < fsl_desc->n_tcds; i++) 105 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, 106 fsl_desc->tcd[i].ptcd); 107 kfree(fsl_desc); 108 } 109 EXPORT_SYMBOL_GPL(fsl_edma_free_desc); 110 111 int fsl_edma_terminate_all(struct dma_chan *chan) 112 { 113 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 114 unsigned long flags; 115 LIST_HEAD(head); 116 117 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 118 fsl_edma_disable_request(fsl_chan); 119 fsl_chan->edesc = NULL; 120 fsl_chan->idle = true; 121 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 122 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 123 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 124 return 0; 125 } 126 EXPORT_SYMBOL_GPL(fsl_edma_terminate_all); 127 128 int fsl_edma_pause(struct dma_chan *chan) 129 { 130 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 131 unsigned long flags; 132 133 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 134 if (fsl_chan->edesc) { 135 fsl_edma_disable_request(fsl_chan); 136 fsl_chan->status = DMA_PAUSED; 137 fsl_chan->idle = true; 138 } 139 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 140 return 0; 141 } 142 EXPORT_SYMBOL_GPL(fsl_edma_pause); 143 144 int fsl_edma_resume(struct dma_chan *chan) 145 { 146 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 147 unsigned long flags; 148 149 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 150 if (fsl_chan->edesc) { 151 fsl_edma_enable_request(fsl_chan); 152 fsl_chan->status = DMA_IN_PROGRESS; 153 fsl_chan->idle = false; 154 } 155 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 156 return 0; 157 } 158 EXPORT_SYMBOL_GPL(fsl_edma_resume); 159 160 int fsl_edma_slave_config(struct dma_chan *chan, 161 struct dma_slave_config *cfg) 162 { 163 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 164 165 fsl_chan->fsc.dir = cfg->direction; 166 if (cfg->direction == DMA_DEV_TO_MEM) { 167 fsl_chan->fsc.dev_addr = cfg->src_addr; 168 fsl_chan->fsc.addr_width = cfg->src_addr_width; 169 fsl_chan->fsc.burst = cfg->src_maxburst; 170 fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->src_addr_width); 171 } else if (cfg->direction == DMA_MEM_TO_DEV) { 172 fsl_chan->fsc.dev_addr = cfg->dst_addr; 173 fsl_chan->fsc.addr_width = cfg->dst_addr_width; 174 fsl_chan->fsc.burst = cfg->dst_maxburst; 175 fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->dst_addr_width); 176 } else 177 return -EINVAL; 178 179 return 0; 180 } 181 EXPORT_SYMBOL_GPL(fsl_edma_slave_config); 182 183 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, 184 struct virt_dma_desc *vdesc, bool in_progress) 185 { 186 struct fsl_edma_desc *edesc = fsl_chan->edesc; 187 void __iomem *addr = fsl_chan->edma->membase; 188 u32 ch = fsl_chan->vchan.chan.chan_id; 189 enum dma_transfer_direction dir = fsl_chan->fsc.dir; 190 dma_addr_t cur_addr, dma_addr; 191 size_t len, size; 192 int i; 193 194 /* calculate the total size in this desc */ 195 for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) 196 len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 197 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 198 199 if (!in_progress) 200 return len; 201 202 if (dir == DMA_MEM_TO_DEV) 203 cur_addr = edma_readl( 204 fsl_chan->edma, addr + EDMA_TCD_SADDR(ch)); 205 else 206 cur_addr = edma_readl( 207 fsl_chan->edma, addr + EDMA_TCD_DADDR(ch)); 208 209 /* figure out the finished and calculate the residue */ 210 for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { 211 size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 212 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 213 if (dir == DMA_MEM_TO_DEV) 214 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); 215 else 216 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); 217 218 len -= size; 219 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { 220 len += dma_addr + size - cur_addr; 221 break; 222 } 223 } 224 225 return len; 226 } 227 228 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 229 dma_cookie_t cookie, struct dma_tx_state *txstate) 230 { 231 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 232 struct virt_dma_desc *vdesc; 233 enum dma_status status; 234 unsigned long flags; 235 236 status = dma_cookie_status(chan, cookie, txstate); 237 if (status == DMA_COMPLETE) 238 return status; 239 240 if (!txstate) 241 return fsl_chan->status; 242 243 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 244 vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); 245 if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) 246 txstate->residue = 247 fsl_edma_desc_residue(fsl_chan, vdesc, true); 248 else if (vdesc) 249 txstate->residue = 250 fsl_edma_desc_residue(fsl_chan, vdesc, false); 251 else 252 txstate->residue = 0; 253 254 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 255 256 return fsl_chan->status; 257 } 258 EXPORT_SYMBOL_GPL(fsl_edma_tx_status); 259 260 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, 261 struct fsl_edma_hw_tcd *tcd) 262 { 263 struct fsl_edma_engine *edma = fsl_chan->edma; 264 void __iomem *addr = fsl_chan->edma->membase; 265 u32 ch = fsl_chan->vchan.chan.chan_id; 266 267 /* 268 * TCD parameters are stored in struct fsl_edma_hw_tcd in little 269 * endian format. However, we need to load the TCD registers in 270 * big- or little-endian obeying the eDMA engine model endian. 271 */ 272 edma_writew(edma, 0, addr + EDMA_TCD_CSR(ch)); 273 edma_writel(edma, le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR(ch)); 274 edma_writel(edma, le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR(ch)); 275 276 edma_writew(edma, le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR(ch)); 277 edma_writew(edma, le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF(ch)); 278 279 edma_writel(edma, le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES(ch)); 280 edma_writel(edma, le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST(ch)); 281 282 edma_writew(edma, le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER(ch)); 283 edma_writew(edma, le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER(ch)); 284 edma_writew(edma, le16_to_cpu(tcd->doff), addr + EDMA_TCD_DOFF(ch)); 285 286 edma_writel(edma, 287 le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA(ch)); 288 289 edma_writew(edma, le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR(ch)); 290 } 291 292 static inline 293 void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, 294 u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, 295 u16 biter, u16 doff, u32 dlast_sga, bool major_int, 296 bool disable_req, bool enable_sg) 297 { 298 u16 csr = 0; 299 300 /* 301 * eDMA hardware SGs require the TCDs to be stored in little 302 * endian format irrespective of the register endian model. 303 * So we put the value in little endian in memory, waiting 304 * for fsl_edma_set_tcd_regs doing the swap. 305 */ 306 tcd->saddr = cpu_to_le32(src); 307 tcd->daddr = cpu_to_le32(dst); 308 309 tcd->attr = cpu_to_le16(attr); 310 311 tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff)); 312 313 tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes)); 314 tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast)); 315 316 tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); 317 tcd->doff = cpu_to_le16(EDMA_TCD_DOFF_DOFF(doff)); 318 319 tcd->dlast_sga = cpu_to_le32(EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga)); 320 321 tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); 322 if (major_int) 323 csr |= EDMA_TCD_CSR_INT_MAJOR; 324 325 if (disable_req) 326 csr |= EDMA_TCD_CSR_D_REQ; 327 328 if (enable_sg) 329 csr |= EDMA_TCD_CSR_E_SG; 330 331 tcd->csr = cpu_to_le16(csr); 332 } 333 334 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, 335 int sg_len) 336 { 337 struct fsl_edma_desc *fsl_desc; 338 int i; 339 340 fsl_desc = kzalloc(sizeof(*fsl_desc) + 341 sizeof(struct fsl_edma_sw_tcd) * 342 sg_len, GFP_NOWAIT); 343 if (!fsl_desc) 344 return NULL; 345 346 fsl_desc->echan = fsl_chan; 347 fsl_desc->n_tcds = sg_len; 348 for (i = 0; i < sg_len; i++) { 349 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, 350 GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); 351 if (!fsl_desc->tcd[i].vtcd) 352 goto err; 353 } 354 return fsl_desc; 355 356 err: 357 while (--i >= 0) 358 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, 359 fsl_desc->tcd[i].ptcd); 360 kfree(fsl_desc); 361 return NULL; 362 } 363 364 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 365 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 366 size_t period_len, enum dma_transfer_direction direction, 367 unsigned long flags) 368 { 369 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 370 struct fsl_edma_desc *fsl_desc; 371 dma_addr_t dma_buf_next; 372 int sg_len, i; 373 u32 src_addr, dst_addr, last_sg, nbytes; 374 u16 soff, doff, iter; 375 376 if (!is_slave_direction(fsl_chan->fsc.dir)) 377 return NULL; 378 379 sg_len = buf_len / period_len; 380 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 381 if (!fsl_desc) 382 return NULL; 383 fsl_desc->iscyclic = true; 384 385 dma_buf_next = dma_addr; 386 nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; 387 iter = period_len / nbytes; 388 389 for (i = 0; i < sg_len; i++) { 390 if (dma_buf_next >= dma_addr + buf_len) 391 dma_buf_next = dma_addr; 392 393 /* get next sg's physical address */ 394 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 395 396 if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { 397 src_addr = dma_buf_next; 398 dst_addr = fsl_chan->fsc.dev_addr; 399 soff = fsl_chan->fsc.addr_width; 400 doff = 0; 401 } else { 402 src_addr = fsl_chan->fsc.dev_addr; 403 dst_addr = dma_buf_next; 404 soff = 0; 405 doff = fsl_chan->fsc.addr_width; 406 } 407 408 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr, 409 fsl_chan->fsc.attr, soff, nbytes, 0, iter, 410 iter, doff, last_sg, true, false, true); 411 dma_buf_next += period_len; 412 } 413 414 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 415 } 416 EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic); 417 418 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 419 struct dma_chan *chan, struct scatterlist *sgl, 420 unsigned int sg_len, enum dma_transfer_direction direction, 421 unsigned long flags, void *context) 422 { 423 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 424 struct fsl_edma_desc *fsl_desc; 425 struct scatterlist *sg; 426 u32 src_addr, dst_addr, last_sg, nbytes; 427 u16 soff, doff, iter; 428 int i; 429 430 if (!is_slave_direction(fsl_chan->fsc.dir)) 431 return NULL; 432 433 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 434 if (!fsl_desc) 435 return NULL; 436 fsl_desc->iscyclic = false; 437 438 nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; 439 for_each_sg(sgl, sg, sg_len, i) { 440 /* get next sg's physical address */ 441 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 442 443 if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { 444 src_addr = sg_dma_address(sg); 445 dst_addr = fsl_chan->fsc.dev_addr; 446 soff = fsl_chan->fsc.addr_width; 447 doff = 0; 448 } else { 449 src_addr = fsl_chan->fsc.dev_addr; 450 dst_addr = sg_dma_address(sg); 451 soff = 0; 452 doff = fsl_chan->fsc.addr_width; 453 } 454 455 iter = sg_dma_len(sg) / nbytes; 456 if (i < sg_len - 1) { 457 last_sg = fsl_desc->tcd[(i + 1)].ptcd; 458 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 459 dst_addr, fsl_chan->fsc.attr, soff, 460 nbytes, 0, iter, iter, doff, last_sg, 461 false, false, true); 462 } else { 463 last_sg = 0; 464 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 465 dst_addr, fsl_chan->fsc.attr, soff, 466 nbytes, 0, iter, iter, doff, last_sg, 467 true, true, false); 468 } 469 } 470 471 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 472 } 473 EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg); 474 475 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) 476 { 477 struct virt_dma_desc *vdesc; 478 479 vdesc = vchan_next_desc(&fsl_chan->vchan); 480 if (!vdesc) 481 return; 482 fsl_chan->edesc = to_fsl_edma_desc(vdesc); 483 fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); 484 fsl_edma_enable_request(fsl_chan); 485 fsl_chan->status = DMA_IN_PROGRESS; 486 fsl_chan->idle = false; 487 } 488 EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc); 489 490 void fsl_edma_issue_pending(struct dma_chan *chan) 491 { 492 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 493 unsigned long flags; 494 495 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 496 497 if (unlikely(fsl_chan->pm_state != RUNNING)) { 498 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 499 /* cannot submit due to suspend */ 500 return; 501 } 502 503 if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) 504 fsl_edma_xfer_desc(fsl_chan); 505 506 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 507 } 508 EXPORT_SYMBOL_GPL(fsl_edma_issue_pending); 509 510 int fsl_edma_alloc_chan_resources(struct dma_chan *chan) 511 { 512 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 513 514 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, 515 sizeof(struct fsl_edma_hw_tcd), 516 32, 0); 517 return 0; 518 } 519 EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources); 520 521 void fsl_edma_free_chan_resources(struct dma_chan *chan) 522 { 523 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 524 unsigned long flags; 525 LIST_HEAD(head); 526 527 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 528 fsl_edma_disable_request(fsl_chan); 529 fsl_edma_chan_mux(fsl_chan, 0, false); 530 fsl_chan->edesc = NULL; 531 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 532 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 533 534 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 535 dma_pool_destroy(fsl_chan->tcd_pool); 536 fsl_chan->tcd_pool = NULL; 537 } 538 EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources); 539 540 void fsl_edma_cleanup_vchan(struct dma_device *dmadev) 541 { 542 struct fsl_edma_chan *chan, *_chan; 543 544 list_for_each_entry_safe(chan, _chan, 545 &dmadev->channels, vchan.chan.device_node) { 546 list_del(&chan->vchan.chan.device_node); 547 tasklet_kill(&chan->vchan.task); 548 } 549 } 550 EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan); 551 552 MODULE_LICENSE("GPL v2"); 553