1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> 5 6 #include <linux/dmapool.h> 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/dma-mapping.h> 10 11 #include "fsl-edma-common.h" 12 13 #define EDMA_CR 0x00 14 #define EDMA_ES 0x04 15 #define EDMA_ERQ 0x0C 16 #define EDMA_EEI 0x14 17 #define EDMA_SERQ 0x1B 18 #define EDMA_CERQ 0x1A 19 #define EDMA_SEEI 0x19 20 #define EDMA_CEEI 0x18 21 #define EDMA_CINT 0x1F 22 #define EDMA_CERR 0x1E 23 #define EDMA_SSRT 0x1D 24 #define EDMA_CDNE 0x1C 25 #define EDMA_INTR 0x24 26 #define EDMA_ERR 0x2C 27 28 #define EDMA64_ERQH 0x08 29 #define EDMA64_EEIH 0x10 30 #define EDMA64_SERQ 0x18 31 #define EDMA64_CERQ 0x19 32 #define EDMA64_SEEI 0x1a 33 #define EDMA64_CEEI 0x1b 34 #define EDMA64_CINT 0x1c 35 #define EDMA64_CERR 0x1d 36 #define EDMA64_SSRT 0x1e 37 #define EDMA64_CDNE 0x1f 38 #define EDMA64_INTH 0x20 39 #define EDMA64_INTL 0x24 40 #define EDMA64_ERRH 0x28 41 #define EDMA64_ERRL 0x2c 42 43 #define EDMA_TCD 0x1000 44 45 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan) 46 { 47 spin_lock(&fsl_chan->vchan.lock); 48 49 if (!fsl_chan->edesc) { 50 /* terminate_all called before */ 51 spin_unlock(&fsl_chan->vchan.lock); 52 return; 53 } 54 55 if (!fsl_chan->edesc->iscyclic) { 56 list_del(&fsl_chan->edesc->vdesc.node); 57 vchan_cookie_complete(&fsl_chan->edesc->vdesc); 58 fsl_chan->edesc = NULL; 59 fsl_chan->status = DMA_COMPLETE; 60 fsl_chan->idle = true; 61 } else { 62 vchan_cyclic_callback(&fsl_chan->edesc->vdesc); 63 } 64 65 if (!fsl_chan->edesc) 66 fsl_edma_xfer_desc(fsl_chan); 67 68 spin_unlock(&fsl_chan->vchan.lock); 69 } 70 71 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) 72 { 73 struct edma_regs *regs = &fsl_chan->edma->regs; 74 u32 ch = fsl_chan->vchan.chan.chan_id; 75 76 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { 77 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); 78 edma_writeb(fsl_chan->edma, ch, regs->serq); 79 } else { 80 /* ColdFire is big endian, and accesses natively 81 * big endian I/O peripherals 82 */ 83 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); 84 iowrite8(ch, regs->serq); 85 } 86 } 87 88 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) 89 { 90 struct edma_regs *regs = &fsl_chan->edma->regs; 91 u32 ch = fsl_chan->vchan.chan.chan_id; 92 93 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { 94 edma_writeb(fsl_chan->edma, ch, regs->cerq); 95 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); 96 } else { 97 /* ColdFire is big endian, and accesses natively 98 * big endian I/O peripherals 99 */ 100 iowrite8(ch, regs->cerq); 101 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); 102 } 103 } 104 105 static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr, 106 u32 off, u32 slot, bool enable) 107 { 108 u8 val8; 109 110 if (enable) 111 val8 = EDMAMUX_CHCFG_ENBL | slot; 112 else 113 val8 = EDMAMUX_CHCFG_DIS; 114 115 iowrite8(val8, addr + off); 116 } 117 118 static void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *addr, 119 u32 off, u32 slot, bool enable) 120 { 121 u32 val; 122 123 if (enable) 124 val = EDMAMUX_CHCFG_ENBL << 24 | slot; 125 else 126 val = EDMAMUX_CHCFG_DIS; 127 128 iowrite32(val, addr + off * 4); 129 } 130 131 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 132 unsigned int slot, bool enable) 133 { 134 u32 ch = fsl_chan->vchan.chan.chan_id; 135 void __iomem *muxaddr; 136 unsigned int chans_per_mux, ch_off; 137 int endian_diff[4] = {3, 1, -1, -3}; 138 u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; 139 140 chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; 141 ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; 142 143 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_MUX_SWAP) 144 ch_off += endian_diff[ch_off % 4]; 145 146 muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; 147 slot = EDMAMUX_CHCFG_SOURCE(slot); 148 149 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_CONFIG32) 150 mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable); 151 else 152 mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable); 153 } 154 155 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) 156 { 157 switch (addr_width) { 158 case 1: 159 return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; 160 case 2: 161 return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; 162 case 4: 163 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 164 case 8: 165 return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; 166 default: 167 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 168 } 169 } 170 171 void fsl_edma_free_desc(struct virt_dma_desc *vdesc) 172 { 173 struct fsl_edma_desc *fsl_desc; 174 int i; 175 176 fsl_desc = to_fsl_edma_desc(vdesc); 177 for (i = 0; i < fsl_desc->n_tcds; i++) 178 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, 179 fsl_desc->tcd[i].ptcd); 180 kfree(fsl_desc); 181 } 182 183 int fsl_edma_terminate_all(struct dma_chan *chan) 184 { 185 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 186 unsigned long flags; 187 LIST_HEAD(head); 188 189 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 190 fsl_edma_disable_request(fsl_chan); 191 fsl_chan->edesc = NULL; 192 fsl_chan->idle = true; 193 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 194 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 195 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 196 return 0; 197 } 198 199 int fsl_edma_pause(struct dma_chan *chan) 200 { 201 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 202 unsigned long flags; 203 204 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 205 if (fsl_chan->edesc) { 206 fsl_edma_disable_request(fsl_chan); 207 fsl_chan->status = DMA_PAUSED; 208 fsl_chan->idle = true; 209 } 210 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 211 return 0; 212 } 213 214 int fsl_edma_resume(struct dma_chan *chan) 215 { 216 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 217 unsigned long flags; 218 219 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 220 if (fsl_chan->edesc) { 221 fsl_edma_enable_request(fsl_chan); 222 fsl_chan->status = DMA_IN_PROGRESS; 223 fsl_chan->idle = false; 224 } 225 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 226 return 0; 227 } 228 229 static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan) 230 { 231 if (fsl_chan->dma_dir != DMA_NONE) 232 dma_unmap_resource(fsl_chan->vchan.chan.device->dev, 233 fsl_chan->dma_dev_addr, 234 fsl_chan->dma_dev_size, 235 fsl_chan->dma_dir, 0); 236 fsl_chan->dma_dir = DMA_NONE; 237 } 238 239 static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan, 240 enum dma_transfer_direction dir) 241 { 242 struct device *dev = fsl_chan->vchan.chan.device->dev; 243 enum dma_data_direction dma_dir; 244 phys_addr_t addr = 0; 245 u32 size = 0; 246 247 switch (dir) { 248 case DMA_MEM_TO_DEV: 249 dma_dir = DMA_FROM_DEVICE; 250 addr = fsl_chan->cfg.dst_addr; 251 size = fsl_chan->cfg.dst_maxburst; 252 break; 253 case DMA_DEV_TO_MEM: 254 dma_dir = DMA_TO_DEVICE; 255 addr = fsl_chan->cfg.src_addr; 256 size = fsl_chan->cfg.src_maxburst; 257 break; 258 default: 259 dma_dir = DMA_NONE; 260 break; 261 } 262 263 /* Already mapped for this config? */ 264 if (fsl_chan->dma_dir == dma_dir) 265 return true; 266 267 fsl_edma_unprep_slave_dma(fsl_chan); 268 269 fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0); 270 if (dma_mapping_error(dev, fsl_chan->dma_dev_addr)) 271 return false; 272 fsl_chan->dma_dev_size = size; 273 fsl_chan->dma_dir = dma_dir; 274 275 return true; 276 } 277 278 int fsl_edma_slave_config(struct dma_chan *chan, 279 struct dma_slave_config *cfg) 280 { 281 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 282 283 memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg)); 284 fsl_edma_unprep_slave_dma(fsl_chan); 285 286 return 0; 287 } 288 289 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, 290 struct virt_dma_desc *vdesc, bool in_progress) 291 { 292 struct fsl_edma_desc *edesc = fsl_chan->edesc; 293 struct edma_regs *regs = &fsl_chan->edma->regs; 294 u32 ch = fsl_chan->vchan.chan.chan_id; 295 enum dma_transfer_direction dir = edesc->dirn; 296 dma_addr_t cur_addr, dma_addr; 297 size_t len, size; 298 int i; 299 300 /* calculate the total size in this desc */ 301 for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) 302 len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 303 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 304 305 if (!in_progress) 306 return len; 307 308 if (dir == DMA_MEM_TO_DEV) 309 cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr); 310 else 311 cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr); 312 313 /* figure out the finished and calculate the residue */ 314 for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { 315 size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 316 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 317 if (dir == DMA_MEM_TO_DEV) 318 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); 319 else 320 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); 321 322 len -= size; 323 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { 324 len += dma_addr + size - cur_addr; 325 break; 326 } 327 } 328 329 return len; 330 } 331 332 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 333 dma_cookie_t cookie, struct dma_tx_state *txstate) 334 { 335 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 336 struct virt_dma_desc *vdesc; 337 enum dma_status status; 338 unsigned long flags; 339 340 status = dma_cookie_status(chan, cookie, txstate); 341 if (status == DMA_COMPLETE) 342 return status; 343 344 if (!txstate) 345 return fsl_chan->status; 346 347 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 348 vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); 349 if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) 350 txstate->residue = 351 fsl_edma_desc_residue(fsl_chan, vdesc, true); 352 else if (vdesc) 353 txstate->residue = 354 fsl_edma_desc_residue(fsl_chan, vdesc, false); 355 else 356 txstate->residue = 0; 357 358 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 359 360 return fsl_chan->status; 361 } 362 363 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, 364 struct fsl_edma_hw_tcd *tcd) 365 { 366 struct fsl_edma_engine *edma = fsl_chan->edma; 367 struct edma_regs *regs = &fsl_chan->edma->regs; 368 u32 ch = fsl_chan->vchan.chan.chan_id; 369 u16 csr = 0; 370 371 /* 372 * TCD parameters are stored in struct fsl_edma_hw_tcd in little 373 * endian format. However, we need to load the TCD registers in 374 * big- or little-endian obeying the eDMA engine model endian, 375 * and this is performed from specific edma_write functions 376 */ 377 edma_writew(edma, 0, ®s->tcd[ch].csr); 378 379 edma_writel(edma, (s32)tcd->saddr, ®s->tcd[ch].saddr); 380 edma_writel(edma, (s32)tcd->daddr, ®s->tcd[ch].daddr); 381 382 edma_writew(edma, (s16)tcd->attr, ®s->tcd[ch].attr); 383 edma_writew(edma, tcd->soff, ®s->tcd[ch].soff); 384 385 edma_writel(edma, (s32)tcd->nbytes, ®s->tcd[ch].nbytes); 386 edma_writel(edma, (s32)tcd->slast, ®s->tcd[ch].slast); 387 388 edma_writew(edma, (s16)tcd->citer, ®s->tcd[ch].citer); 389 edma_writew(edma, (s16)tcd->biter, ®s->tcd[ch].biter); 390 edma_writew(edma, (s16)tcd->doff, ®s->tcd[ch].doff); 391 392 edma_writel(edma, (s32)tcd->dlast_sga, 393 ®s->tcd[ch].dlast_sga); 394 395 if (fsl_chan->is_sw) { 396 csr = le16_to_cpu(tcd->csr); 397 csr |= EDMA_TCD_CSR_START; 398 tcd->csr = cpu_to_le16(csr); 399 } 400 401 edma_writew(edma, (s16)tcd->csr, ®s->tcd[ch].csr); 402 } 403 404 static inline 405 void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, 406 u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, 407 u16 biter, u16 doff, u32 dlast_sga, bool major_int, 408 bool disable_req, bool enable_sg) 409 { 410 u16 csr = 0; 411 412 /* 413 * eDMA hardware SGs require the TCDs to be stored in little 414 * endian format irrespective of the register endian model. 415 * So we put the value in little endian in memory, waiting 416 * for fsl_edma_set_tcd_regs doing the swap. 417 */ 418 tcd->saddr = cpu_to_le32(src); 419 tcd->daddr = cpu_to_le32(dst); 420 421 tcd->attr = cpu_to_le16(attr); 422 423 tcd->soff = cpu_to_le16(soff); 424 425 tcd->nbytes = cpu_to_le32(nbytes); 426 tcd->slast = cpu_to_le32(slast); 427 428 tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); 429 tcd->doff = cpu_to_le16(doff); 430 431 tcd->dlast_sga = cpu_to_le32(dlast_sga); 432 433 tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); 434 if (major_int) 435 csr |= EDMA_TCD_CSR_INT_MAJOR; 436 437 if (disable_req) 438 csr |= EDMA_TCD_CSR_D_REQ; 439 440 if (enable_sg) 441 csr |= EDMA_TCD_CSR_E_SG; 442 443 tcd->csr = cpu_to_le16(csr); 444 } 445 446 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, 447 int sg_len) 448 { 449 struct fsl_edma_desc *fsl_desc; 450 int i; 451 452 fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT); 453 if (!fsl_desc) 454 return NULL; 455 456 fsl_desc->echan = fsl_chan; 457 fsl_desc->n_tcds = sg_len; 458 for (i = 0; i < sg_len; i++) { 459 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, 460 GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); 461 if (!fsl_desc->tcd[i].vtcd) 462 goto err; 463 } 464 return fsl_desc; 465 466 err: 467 while (--i >= 0) 468 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, 469 fsl_desc->tcd[i].ptcd); 470 kfree(fsl_desc); 471 return NULL; 472 } 473 474 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 475 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 476 size_t period_len, enum dma_transfer_direction direction, 477 unsigned long flags) 478 { 479 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 480 struct fsl_edma_desc *fsl_desc; 481 dma_addr_t dma_buf_next; 482 int sg_len, i; 483 u32 src_addr, dst_addr, last_sg, nbytes; 484 u16 soff, doff, iter; 485 486 if (!is_slave_direction(direction)) 487 return NULL; 488 489 if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) 490 return NULL; 491 492 sg_len = buf_len / period_len; 493 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 494 if (!fsl_desc) 495 return NULL; 496 fsl_desc->iscyclic = true; 497 fsl_desc->dirn = direction; 498 499 dma_buf_next = dma_addr; 500 if (direction == DMA_MEM_TO_DEV) { 501 fsl_chan->attr = 502 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); 503 nbytes = fsl_chan->cfg.dst_addr_width * 504 fsl_chan->cfg.dst_maxburst; 505 } else { 506 fsl_chan->attr = 507 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); 508 nbytes = fsl_chan->cfg.src_addr_width * 509 fsl_chan->cfg.src_maxburst; 510 } 511 512 iter = period_len / nbytes; 513 514 for (i = 0; i < sg_len; i++) { 515 if (dma_buf_next >= dma_addr + buf_len) 516 dma_buf_next = dma_addr; 517 518 /* get next sg's physical address */ 519 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 520 521 if (direction == DMA_MEM_TO_DEV) { 522 src_addr = dma_buf_next; 523 dst_addr = fsl_chan->dma_dev_addr; 524 soff = fsl_chan->cfg.dst_addr_width; 525 doff = 0; 526 } else { 527 src_addr = fsl_chan->dma_dev_addr; 528 dst_addr = dma_buf_next; 529 soff = 0; 530 doff = fsl_chan->cfg.src_addr_width; 531 } 532 533 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr, 534 fsl_chan->attr, soff, nbytes, 0, iter, 535 iter, doff, last_sg, true, false, true); 536 dma_buf_next += period_len; 537 } 538 539 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 540 } 541 542 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 543 struct dma_chan *chan, struct scatterlist *sgl, 544 unsigned int sg_len, enum dma_transfer_direction direction, 545 unsigned long flags, void *context) 546 { 547 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 548 struct fsl_edma_desc *fsl_desc; 549 struct scatterlist *sg; 550 u32 src_addr, dst_addr, last_sg, nbytes; 551 u16 soff, doff, iter; 552 int i; 553 554 if (!is_slave_direction(direction)) 555 return NULL; 556 557 if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) 558 return NULL; 559 560 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 561 if (!fsl_desc) 562 return NULL; 563 fsl_desc->iscyclic = false; 564 fsl_desc->dirn = direction; 565 566 if (direction == DMA_MEM_TO_DEV) { 567 fsl_chan->attr = 568 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); 569 nbytes = fsl_chan->cfg.dst_addr_width * 570 fsl_chan->cfg.dst_maxburst; 571 } else { 572 fsl_chan->attr = 573 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); 574 nbytes = fsl_chan->cfg.src_addr_width * 575 fsl_chan->cfg.src_maxburst; 576 } 577 578 for_each_sg(sgl, sg, sg_len, i) { 579 if (direction == DMA_MEM_TO_DEV) { 580 src_addr = sg_dma_address(sg); 581 dst_addr = fsl_chan->dma_dev_addr; 582 soff = fsl_chan->cfg.dst_addr_width; 583 doff = 0; 584 } else { 585 src_addr = fsl_chan->dma_dev_addr; 586 dst_addr = sg_dma_address(sg); 587 soff = 0; 588 doff = fsl_chan->cfg.src_addr_width; 589 } 590 591 iter = sg_dma_len(sg) / nbytes; 592 if (i < sg_len - 1) { 593 last_sg = fsl_desc->tcd[(i + 1)].ptcd; 594 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 595 dst_addr, fsl_chan->attr, soff, 596 nbytes, 0, iter, iter, doff, last_sg, 597 false, false, true); 598 } else { 599 last_sg = 0; 600 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 601 dst_addr, fsl_chan->attr, soff, 602 nbytes, 0, iter, iter, doff, last_sg, 603 true, true, false); 604 } 605 } 606 607 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 608 } 609 610 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan, 611 dma_addr_t dma_dst, dma_addr_t dma_src, 612 size_t len, unsigned long flags) 613 { 614 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 615 struct fsl_edma_desc *fsl_desc; 616 617 fsl_desc = fsl_edma_alloc_desc(fsl_chan, 1); 618 if (!fsl_desc) 619 return NULL; 620 fsl_desc->iscyclic = false; 621 622 fsl_chan->is_sw = true; 623 624 /* To match with copy_align and max_seg_size so 1 tcd is enough */ 625 fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst, 626 EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE, 627 32, len, 0, 1, 1, 32, 0, true, true, false); 628 629 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 630 } 631 632 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) 633 { 634 struct virt_dma_desc *vdesc; 635 636 lockdep_assert_held(&fsl_chan->vchan.lock); 637 638 vdesc = vchan_next_desc(&fsl_chan->vchan); 639 if (!vdesc) 640 return; 641 fsl_chan->edesc = to_fsl_edma_desc(vdesc); 642 fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); 643 fsl_edma_enable_request(fsl_chan); 644 fsl_chan->status = DMA_IN_PROGRESS; 645 fsl_chan->idle = false; 646 } 647 648 void fsl_edma_issue_pending(struct dma_chan *chan) 649 { 650 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 651 unsigned long flags; 652 653 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 654 655 if (unlikely(fsl_chan->pm_state != RUNNING)) { 656 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 657 /* cannot submit due to suspend */ 658 return; 659 } 660 661 if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) 662 fsl_edma_xfer_desc(fsl_chan); 663 664 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 665 } 666 667 int fsl_edma_alloc_chan_resources(struct dma_chan *chan) 668 { 669 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 670 671 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, 672 sizeof(struct fsl_edma_hw_tcd), 673 32, 0); 674 return 0; 675 } 676 677 void fsl_edma_free_chan_resources(struct dma_chan *chan) 678 { 679 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 680 struct fsl_edma_engine *edma = fsl_chan->edma; 681 unsigned long flags; 682 LIST_HEAD(head); 683 684 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 685 fsl_edma_disable_request(fsl_chan); 686 if (edma->drvdata->dmamuxs) 687 fsl_edma_chan_mux(fsl_chan, 0, false); 688 fsl_chan->edesc = NULL; 689 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 690 fsl_edma_unprep_slave_dma(fsl_chan); 691 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 692 693 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 694 dma_pool_destroy(fsl_chan->tcd_pool); 695 fsl_chan->tcd_pool = NULL; 696 fsl_chan->is_sw = false; 697 } 698 699 void fsl_edma_cleanup_vchan(struct dma_device *dmadev) 700 { 701 struct fsl_edma_chan *chan, *_chan; 702 703 list_for_each_entry_safe(chan, _chan, 704 &dmadev->channels, vchan.chan.device_node) { 705 list_del(&chan->vchan.chan.device_node); 706 tasklet_kill(&chan->vchan.task); 707 } 708 } 709 710 /* 711 * On the 32 channels Vybrid/mpc577x edma version, register offsets are 712 * different compared to ColdFire mcf5441x 64 channels edma. 713 * 714 * This function sets up register offsets as per proper declared version 715 * so must be called in xxx_edma_probe() just after setting the 716 * edma "version" and "membase" appropriately. 717 */ 718 void fsl_edma_setup_regs(struct fsl_edma_engine *edma) 719 { 720 bool is64 = !!(edma->drvdata->flags & FSL_EDMA_DRV_EDMA64); 721 722 edma->regs.cr = edma->membase + EDMA_CR; 723 edma->regs.es = edma->membase + EDMA_ES; 724 edma->regs.erql = edma->membase + EDMA_ERQ; 725 edma->regs.eeil = edma->membase + EDMA_EEI; 726 727 edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); 728 edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); 729 edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); 730 edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); 731 edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); 732 edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); 733 edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); 734 edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); 735 edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); 736 edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); 737 738 if (is64) { 739 edma->regs.erqh = edma->membase + EDMA64_ERQH; 740 edma->regs.eeih = edma->membase + EDMA64_EEIH; 741 edma->regs.errh = edma->membase + EDMA64_ERRH; 742 edma->regs.inth = edma->membase + EDMA64_INTH; 743 } 744 745 edma->regs.tcd = edma->membase + EDMA_TCD; 746 } 747 748 MODULE_LICENSE("GPL v2"); 749