1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> 5 6 #include <linux/dmapool.h> 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/dma-mapping.h> 10 11 #include "fsl-edma-common.h" 12 13 #define EDMA_CR 0x00 14 #define EDMA_ES 0x04 15 #define EDMA_ERQ 0x0C 16 #define EDMA_EEI 0x14 17 #define EDMA_SERQ 0x1B 18 #define EDMA_CERQ 0x1A 19 #define EDMA_SEEI 0x19 20 #define EDMA_CEEI 0x18 21 #define EDMA_CINT 0x1F 22 #define EDMA_CERR 0x1E 23 #define EDMA_SSRT 0x1D 24 #define EDMA_CDNE 0x1C 25 #define EDMA_INTR 0x24 26 #define EDMA_ERR 0x2C 27 28 #define EDMA64_ERQH 0x08 29 #define EDMA64_EEIH 0x10 30 #define EDMA64_SERQ 0x18 31 #define EDMA64_CERQ 0x19 32 #define EDMA64_SEEI 0x1a 33 #define EDMA64_CEEI 0x1b 34 #define EDMA64_CINT 0x1c 35 #define EDMA64_CERR 0x1d 36 #define EDMA64_SSRT 0x1e 37 #define EDMA64_CDNE 0x1f 38 #define EDMA64_INTH 0x20 39 #define EDMA64_INTL 0x24 40 #define EDMA64_ERRH 0x28 41 #define EDMA64_ERRL 0x2c 42 43 #define EDMA_TCD 0x1000 44 45 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) 46 { 47 struct edma_regs *regs = &fsl_chan->edma->regs; 48 u32 ch = fsl_chan->vchan.chan.chan_id; 49 50 if (fsl_chan->edma->drvdata->version == v1) { 51 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); 52 edma_writeb(fsl_chan->edma, ch, regs->serq); 53 } else { 54 /* ColdFire is big endian, and accesses natively 55 * big endian I/O peripherals 56 */ 57 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); 58 iowrite8(ch, regs->serq); 59 } 60 } 61 62 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) 63 { 64 struct edma_regs *regs = &fsl_chan->edma->regs; 65 u32 ch = fsl_chan->vchan.chan.chan_id; 66 67 if (fsl_chan->edma->drvdata->version == v1) { 68 edma_writeb(fsl_chan->edma, ch, regs->cerq); 69 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); 70 } else { 71 /* ColdFire is big endian, and accesses natively 72 * big endian I/O peripherals 73 */ 74 iowrite8(ch, regs->cerq); 75 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); 76 } 77 } 78 EXPORT_SYMBOL_GPL(fsl_edma_disable_request); 79 80 static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr, 81 u32 off, u32 slot, bool enable) 82 { 83 u8 val8; 84 85 if (enable) 86 val8 = EDMAMUX_CHCFG_ENBL | slot; 87 else 88 val8 = EDMAMUX_CHCFG_DIS; 89 90 iowrite8(val8, addr + off); 91 } 92 93 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 94 unsigned int slot, bool enable) 95 { 96 u32 ch = fsl_chan->vchan.chan.chan_id; 97 void __iomem *muxaddr; 98 unsigned int chans_per_mux, ch_off; 99 u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; 100 101 chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; 102 ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; 103 muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; 104 slot = EDMAMUX_CHCFG_SOURCE(slot); 105 106 mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable); 107 } 108 EXPORT_SYMBOL_GPL(fsl_edma_chan_mux); 109 110 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) 111 { 112 switch (addr_width) { 113 case 1: 114 return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; 115 case 2: 116 return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; 117 case 4: 118 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 119 case 8: 120 return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; 121 default: 122 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 123 } 124 } 125 126 void fsl_edma_free_desc(struct virt_dma_desc *vdesc) 127 { 128 struct fsl_edma_desc *fsl_desc; 129 int i; 130 131 fsl_desc = to_fsl_edma_desc(vdesc); 132 for (i = 0; i < fsl_desc->n_tcds; i++) 133 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, 134 fsl_desc->tcd[i].ptcd); 135 kfree(fsl_desc); 136 } 137 EXPORT_SYMBOL_GPL(fsl_edma_free_desc); 138 139 int fsl_edma_terminate_all(struct dma_chan *chan) 140 { 141 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 142 unsigned long flags; 143 LIST_HEAD(head); 144 145 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 146 fsl_edma_disable_request(fsl_chan); 147 fsl_chan->edesc = NULL; 148 fsl_chan->idle = true; 149 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 150 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 151 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 152 return 0; 153 } 154 EXPORT_SYMBOL_GPL(fsl_edma_terminate_all); 155 156 int fsl_edma_pause(struct dma_chan *chan) 157 { 158 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 159 unsigned long flags; 160 161 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 162 if (fsl_chan->edesc) { 163 fsl_edma_disable_request(fsl_chan); 164 fsl_chan->status = DMA_PAUSED; 165 fsl_chan->idle = true; 166 } 167 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 168 return 0; 169 } 170 EXPORT_SYMBOL_GPL(fsl_edma_pause); 171 172 int fsl_edma_resume(struct dma_chan *chan) 173 { 174 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 175 unsigned long flags; 176 177 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 178 if (fsl_chan->edesc) { 179 fsl_edma_enable_request(fsl_chan); 180 fsl_chan->status = DMA_IN_PROGRESS; 181 fsl_chan->idle = false; 182 } 183 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 184 return 0; 185 } 186 EXPORT_SYMBOL_GPL(fsl_edma_resume); 187 188 static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan) 189 { 190 if (fsl_chan->dma_dir != DMA_NONE) 191 dma_unmap_resource(fsl_chan->vchan.chan.device->dev, 192 fsl_chan->dma_dev_addr, 193 fsl_chan->dma_dev_size, 194 fsl_chan->dma_dir, 0); 195 fsl_chan->dma_dir = DMA_NONE; 196 } 197 198 static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan, 199 enum dma_transfer_direction dir) 200 { 201 struct device *dev = fsl_chan->vchan.chan.device->dev; 202 enum dma_data_direction dma_dir; 203 phys_addr_t addr = 0; 204 u32 size = 0; 205 206 switch (dir) { 207 case DMA_MEM_TO_DEV: 208 dma_dir = DMA_FROM_DEVICE; 209 addr = fsl_chan->cfg.dst_addr; 210 size = fsl_chan->cfg.dst_maxburst; 211 break; 212 case DMA_DEV_TO_MEM: 213 dma_dir = DMA_TO_DEVICE; 214 addr = fsl_chan->cfg.src_addr; 215 size = fsl_chan->cfg.src_maxburst; 216 break; 217 default: 218 dma_dir = DMA_NONE; 219 break; 220 } 221 222 /* Already mapped for this config? */ 223 if (fsl_chan->dma_dir == dma_dir) 224 return true; 225 226 fsl_edma_unprep_slave_dma(fsl_chan); 227 228 fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0); 229 if (dma_mapping_error(dev, fsl_chan->dma_dev_addr)) 230 return false; 231 fsl_chan->dma_dev_size = size; 232 fsl_chan->dma_dir = dma_dir; 233 234 return true; 235 } 236 237 int fsl_edma_slave_config(struct dma_chan *chan, 238 struct dma_slave_config *cfg) 239 { 240 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 241 242 memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg)); 243 fsl_edma_unprep_slave_dma(fsl_chan); 244 245 return 0; 246 } 247 EXPORT_SYMBOL_GPL(fsl_edma_slave_config); 248 249 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, 250 struct virt_dma_desc *vdesc, bool in_progress) 251 { 252 struct fsl_edma_desc *edesc = fsl_chan->edesc; 253 struct edma_regs *regs = &fsl_chan->edma->regs; 254 u32 ch = fsl_chan->vchan.chan.chan_id; 255 enum dma_transfer_direction dir = edesc->dirn; 256 dma_addr_t cur_addr, dma_addr; 257 size_t len, size; 258 int i; 259 260 /* calculate the total size in this desc */ 261 for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) 262 len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 263 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 264 265 if (!in_progress) 266 return len; 267 268 if (dir == DMA_MEM_TO_DEV) 269 cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr); 270 else 271 cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr); 272 273 /* figure out the finished and calculate the residue */ 274 for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { 275 size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 276 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 277 if (dir == DMA_MEM_TO_DEV) 278 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); 279 else 280 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); 281 282 len -= size; 283 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { 284 len += dma_addr + size - cur_addr; 285 break; 286 } 287 } 288 289 return len; 290 } 291 292 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 293 dma_cookie_t cookie, struct dma_tx_state *txstate) 294 { 295 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 296 struct virt_dma_desc *vdesc; 297 enum dma_status status; 298 unsigned long flags; 299 300 status = dma_cookie_status(chan, cookie, txstate); 301 if (status == DMA_COMPLETE) 302 return status; 303 304 if (!txstate) 305 return fsl_chan->status; 306 307 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 308 vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); 309 if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) 310 txstate->residue = 311 fsl_edma_desc_residue(fsl_chan, vdesc, true); 312 else if (vdesc) 313 txstate->residue = 314 fsl_edma_desc_residue(fsl_chan, vdesc, false); 315 else 316 txstate->residue = 0; 317 318 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 319 320 return fsl_chan->status; 321 } 322 EXPORT_SYMBOL_GPL(fsl_edma_tx_status); 323 324 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, 325 struct fsl_edma_hw_tcd *tcd) 326 { 327 struct fsl_edma_engine *edma = fsl_chan->edma; 328 struct edma_regs *regs = &fsl_chan->edma->regs; 329 u32 ch = fsl_chan->vchan.chan.chan_id; 330 331 /* 332 * TCD parameters are stored in struct fsl_edma_hw_tcd in little 333 * endian format. However, we need to load the TCD registers in 334 * big- or little-endian obeying the eDMA engine model endian. 335 */ 336 edma_writew(edma, 0, ®s->tcd[ch].csr); 337 edma_writel(edma, le32_to_cpu(tcd->saddr), ®s->tcd[ch].saddr); 338 edma_writel(edma, le32_to_cpu(tcd->daddr), ®s->tcd[ch].daddr); 339 340 edma_writew(edma, le16_to_cpu(tcd->attr), ®s->tcd[ch].attr); 341 edma_writew(edma, le16_to_cpu(tcd->soff), ®s->tcd[ch].soff); 342 343 edma_writel(edma, le32_to_cpu(tcd->nbytes), ®s->tcd[ch].nbytes); 344 edma_writel(edma, le32_to_cpu(tcd->slast), ®s->tcd[ch].slast); 345 346 edma_writew(edma, le16_to_cpu(tcd->citer), ®s->tcd[ch].citer); 347 edma_writew(edma, le16_to_cpu(tcd->biter), ®s->tcd[ch].biter); 348 edma_writew(edma, le16_to_cpu(tcd->doff), ®s->tcd[ch].doff); 349 350 edma_writel(edma, le32_to_cpu(tcd->dlast_sga), 351 ®s->tcd[ch].dlast_sga); 352 353 edma_writew(edma, le16_to_cpu(tcd->csr), ®s->tcd[ch].csr); 354 } 355 356 static inline 357 void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, 358 u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, 359 u16 biter, u16 doff, u32 dlast_sga, bool major_int, 360 bool disable_req, bool enable_sg) 361 { 362 u16 csr = 0; 363 364 /* 365 * eDMA hardware SGs require the TCDs to be stored in little 366 * endian format irrespective of the register endian model. 367 * So we put the value in little endian in memory, waiting 368 * for fsl_edma_set_tcd_regs doing the swap. 369 */ 370 tcd->saddr = cpu_to_le32(src); 371 tcd->daddr = cpu_to_le32(dst); 372 373 tcd->attr = cpu_to_le16(attr); 374 375 tcd->soff = cpu_to_le16(soff); 376 377 tcd->nbytes = cpu_to_le32(nbytes); 378 tcd->slast = cpu_to_le32(slast); 379 380 tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); 381 tcd->doff = cpu_to_le16(doff); 382 383 tcd->dlast_sga = cpu_to_le32(dlast_sga); 384 385 tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); 386 if (major_int) 387 csr |= EDMA_TCD_CSR_INT_MAJOR; 388 389 if (disable_req) 390 csr |= EDMA_TCD_CSR_D_REQ; 391 392 if (enable_sg) 393 csr |= EDMA_TCD_CSR_E_SG; 394 395 tcd->csr = cpu_to_le16(csr); 396 } 397 398 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, 399 int sg_len) 400 { 401 struct fsl_edma_desc *fsl_desc; 402 int i; 403 404 fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT); 405 if (!fsl_desc) 406 return NULL; 407 408 fsl_desc->echan = fsl_chan; 409 fsl_desc->n_tcds = sg_len; 410 for (i = 0; i < sg_len; i++) { 411 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, 412 GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); 413 if (!fsl_desc->tcd[i].vtcd) 414 goto err; 415 } 416 return fsl_desc; 417 418 err: 419 while (--i >= 0) 420 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, 421 fsl_desc->tcd[i].ptcd); 422 kfree(fsl_desc); 423 return NULL; 424 } 425 426 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 427 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 428 size_t period_len, enum dma_transfer_direction direction, 429 unsigned long flags) 430 { 431 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 432 struct fsl_edma_desc *fsl_desc; 433 dma_addr_t dma_buf_next; 434 int sg_len, i; 435 u32 src_addr, dst_addr, last_sg, nbytes; 436 u16 soff, doff, iter; 437 438 if (!is_slave_direction(direction)) 439 return NULL; 440 441 if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) 442 return NULL; 443 444 sg_len = buf_len / period_len; 445 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 446 if (!fsl_desc) 447 return NULL; 448 fsl_desc->iscyclic = true; 449 fsl_desc->dirn = direction; 450 451 dma_buf_next = dma_addr; 452 if (direction == DMA_MEM_TO_DEV) { 453 fsl_chan->attr = 454 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); 455 nbytes = fsl_chan->cfg.dst_addr_width * 456 fsl_chan->cfg.dst_maxburst; 457 } else { 458 fsl_chan->attr = 459 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); 460 nbytes = fsl_chan->cfg.src_addr_width * 461 fsl_chan->cfg.src_maxburst; 462 } 463 464 iter = period_len / nbytes; 465 466 for (i = 0; i < sg_len; i++) { 467 if (dma_buf_next >= dma_addr + buf_len) 468 dma_buf_next = dma_addr; 469 470 /* get next sg's physical address */ 471 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 472 473 if (direction == DMA_MEM_TO_DEV) { 474 src_addr = dma_buf_next; 475 dst_addr = fsl_chan->dma_dev_addr; 476 soff = fsl_chan->cfg.dst_addr_width; 477 doff = 0; 478 } else { 479 src_addr = fsl_chan->dma_dev_addr; 480 dst_addr = dma_buf_next; 481 soff = 0; 482 doff = fsl_chan->cfg.src_addr_width; 483 } 484 485 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr, 486 fsl_chan->attr, soff, nbytes, 0, iter, 487 iter, doff, last_sg, true, false, true); 488 dma_buf_next += period_len; 489 } 490 491 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 492 } 493 EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic); 494 495 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 496 struct dma_chan *chan, struct scatterlist *sgl, 497 unsigned int sg_len, enum dma_transfer_direction direction, 498 unsigned long flags, void *context) 499 { 500 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 501 struct fsl_edma_desc *fsl_desc; 502 struct scatterlist *sg; 503 u32 src_addr, dst_addr, last_sg, nbytes; 504 u16 soff, doff, iter; 505 int i; 506 507 if (!is_slave_direction(direction)) 508 return NULL; 509 510 if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) 511 return NULL; 512 513 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 514 if (!fsl_desc) 515 return NULL; 516 fsl_desc->iscyclic = false; 517 fsl_desc->dirn = direction; 518 519 if (direction == DMA_MEM_TO_DEV) { 520 fsl_chan->attr = 521 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); 522 nbytes = fsl_chan->cfg.dst_addr_width * 523 fsl_chan->cfg.dst_maxburst; 524 } else { 525 fsl_chan->attr = 526 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); 527 nbytes = fsl_chan->cfg.src_addr_width * 528 fsl_chan->cfg.src_maxburst; 529 } 530 531 for_each_sg(sgl, sg, sg_len, i) { 532 /* get next sg's physical address */ 533 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 534 535 if (direction == DMA_MEM_TO_DEV) { 536 src_addr = sg_dma_address(sg); 537 dst_addr = fsl_chan->dma_dev_addr; 538 soff = fsl_chan->cfg.dst_addr_width; 539 doff = 0; 540 } else { 541 src_addr = fsl_chan->dma_dev_addr; 542 dst_addr = sg_dma_address(sg); 543 soff = 0; 544 doff = fsl_chan->cfg.src_addr_width; 545 } 546 547 iter = sg_dma_len(sg) / nbytes; 548 if (i < sg_len - 1) { 549 last_sg = fsl_desc->tcd[(i + 1)].ptcd; 550 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 551 dst_addr, fsl_chan->attr, soff, 552 nbytes, 0, iter, iter, doff, last_sg, 553 false, false, true); 554 } else { 555 last_sg = 0; 556 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 557 dst_addr, fsl_chan->attr, soff, 558 nbytes, 0, iter, iter, doff, last_sg, 559 true, true, false); 560 } 561 } 562 563 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 564 } 565 EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg); 566 567 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) 568 { 569 struct virt_dma_desc *vdesc; 570 571 vdesc = vchan_next_desc(&fsl_chan->vchan); 572 if (!vdesc) 573 return; 574 fsl_chan->edesc = to_fsl_edma_desc(vdesc); 575 fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); 576 fsl_edma_enable_request(fsl_chan); 577 fsl_chan->status = DMA_IN_PROGRESS; 578 fsl_chan->idle = false; 579 } 580 EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc); 581 582 void fsl_edma_issue_pending(struct dma_chan *chan) 583 { 584 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 585 unsigned long flags; 586 587 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 588 589 if (unlikely(fsl_chan->pm_state != RUNNING)) { 590 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 591 /* cannot submit due to suspend */ 592 return; 593 } 594 595 if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) 596 fsl_edma_xfer_desc(fsl_chan); 597 598 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 599 } 600 EXPORT_SYMBOL_GPL(fsl_edma_issue_pending); 601 602 int fsl_edma_alloc_chan_resources(struct dma_chan *chan) 603 { 604 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 605 606 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, 607 sizeof(struct fsl_edma_hw_tcd), 608 32, 0); 609 return 0; 610 } 611 EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources); 612 613 void fsl_edma_free_chan_resources(struct dma_chan *chan) 614 { 615 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 616 unsigned long flags; 617 LIST_HEAD(head); 618 619 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 620 fsl_edma_disable_request(fsl_chan); 621 fsl_edma_chan_mux(fsl_chan, 0, false); 622 fsl_chan->edesc = NULL; 623 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 624 fsl_edma_unprep_slave_dma(fsl_chan); 625 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 626 627 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 628 dma_pool_destroy(fsl_chan->tcd_pool); 629 fsl_chan->tcd_pool = NULL; 630 } 631 EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources); 632 633 void fsl_edma_cleanup_vchan(struct dma_device *dmadev) 634 { 635 struct fsl_edma_chan *chan, *_chan; 636 637 list_for_each_entry_safe(chan, _chan, 638 &dmadev->channels, vchan.chan.device_node) { 639 list_del(&chan->vchan.chan.device_node); 640 tasklet_kill(&chan->vchan.task); 641 } 642 } 643 EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan); 644 645 /* 646 * On the 32 channels Vybrid/mpc577x edma version (here called "v1"), 647 * register offsets are different compared to ColdFire mcf5441x 64 channels 648 * edma (here called "v2"). 649 * 650 * This function sets up register offsets as per proper declared version 651 * so must be called in xxx_edma_probe() just after setting the 652 * edma "version" and "membase" appropriately. 653 */ 654 void fsl_edma_setup_regs(struct fsl_edma_engine *edma) 655 { 656 edma->regs.cr = edma->membase + EDMA_CR; 657 edma->regs.es = edma->membase + EDMA_ES; 658 edma->regs.erql = edma->membase + EDMA_ERQ; 659 edma->regs.eeil = edma->membase + EDMA_EEI; 660 661 edma->regs.serq = edma->membase + ((edma->drvdata->version == v2) ? 662 EDMA64_SERQ : EDMA_SERQ); 663 edma->regs.cerq = edma->membase + ((edma->drvdata->version == v2) ? 664 EDMA64_CERQ : EDMA_CERQ); 665 edma->regs.seei = edma->membase + ((edma->drvdata->version == v2) ? 666 EDMA64_SEEI : EDMA_SEEI); 667 edma->regs.ceei = edma->membase + ((edma->drvdata->version == v2) ? 668 EDMA64_CEEI : EDMA_CEEI); 669 edma->regs.cint = edma->membase + ((edma->drvdata->version == v2) ? 670 EDMA64_CINT : EDMA_CINT); 671 edma->regs.cerr = edma->membase + ((edma->drvdata->version == v2) ? 672 EDMA64_CERR : EDMA_CERR); 673 edma->regs.ssrt = edma->membase + ((edma->drvdata->version == v2) ? 674 EDMA64_SSRT : EDMA_SSRT); 675 edma->regs.cdne = edma->membase + ((edma->drvdata->version == v2) ? 676 EDMA64_CDNE : EDMA_CDNE); 677 edma->regs.intl = edma->membase + ((edma->drvdata->version == v2) ? 678 EDMA64_INTL : EDMA_INTR); 679 edma->regs.errl = edma->membase + ((edma->drvdata->version == v2) ? 680 EDMA64_ERRL : EDMA_ERR); 681 682 if (edma->drvdata->version == v2) { 683 edma->regs.erqh = edma->membase + EDMA64_ERQH; 684 edma->regs.eeih = edma->membase + EDMA64_EEIH; 685 edma->regs.errh = edma->membase + EDMA64_ERRH; 686 edma->regs.inth = edma->membase + EDMA64_INTH; 687 } 688 689 edma->regs.tcd = edma->membase + EDMA_TCD; 690 } 691 EXPORT_SYMBOL_GPL(fsl_edma_setup_regs); 692 693 MODULE_LICENSE("GPL v2"); 694