1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> 5 6 #include <linux/dmapool.h> 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 10 #include "fsl-edma-common.h" 11 12 #define EDMA_CR 0x00 13 #define EDMA_ES 0x04 14 #define EDMA_ERQ 0x0C 15 #define EDMA_EEI 0x14 16 #define EDMA_SERQ 0x1B 17 #define EDMA_CERQ 0x1A 18 #define EDMA_SEEI 0x19 19 #define EDMA_CEEI 0x18 20 #define EDMA_CINT 0x1F 21 #define EDMA_CERR 0x1E 22 #define EDMA_SSRT 0x1D 23 #define EDMA_CDNE 0x1C 24 #define EDMA_INTR 0x24 25 #define EDMA_ERR 0x2C 26 27 #define EDMA64_ERQH 0x08 28 #define EDMA64_EEIH 0x10 29 #define EDMA64_SERQ 0x18 30 #define EDMA64_CERQ 0x19 31 #define EDMA64_SEEI 0x1a 32 #define EDMA64_CEEI 0x1b 33 #define EDMA64_CINT 0x1c 34 #define EDMA64_CERR 0x1d 35 #define EDMA64_SSRT 0x1e 36 #define EDMA64_CDNE 0x1f 37 #define EDMA64_INTH 0x20 38 #define EDMA64_INTL 0x24 39 #define EDMA64_ERRH 0x28 40 #define EDMA64_ERRL 0x2c 41 42 #define EDMA_TCD 0x1000 43 44 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) 45 { 46 struct edma_regs *regs = &fsl_chan->edma->regs; 47 u32 ch = fsl_chan->vchan.chan.chan_id; 48 49 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); 50 edma_writeb(fsl_chan->edma, ch, regs->serq); 51 } 52 53 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) 54 { 55 struct edma_regs *regs = &fsl_chan->edma->regs; 56 u32 ch = fsl_chan->vchan.chan.chan_id; 57 58 edma_writeb(fsl_chan->edma, ch, regs->cerq); 59 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); 60 } 61 EXPORT_SYMBOL_GPL(fsl_edma_disable_request); 62 63 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 64 unsigned int slot, bool enable) 65 { 66 u32 ch = fsl_chan->vchan.chan.chan_id; 67 void __iomem *muxaddr; 68 unsigned int chans_per_mux, ch_off; 69 70 chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR; 71 ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; 72 muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; 73 slot = EDMAMUX_CHCFG_SOURCE(slot); 74 75 if (enable) 76 iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off); 77 else 78 iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off); 79 } 80 EXPORT_SYMBOL_GPL(fsl_edma_chan_mux); 81 82 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) 83 { 84 switch (addr_width) { 85 case 1: 86 return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; 87 case 2: 88 return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; 89 case 4: 90 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 91 case 8: 92 return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; 93 default: 94 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; 95 } 96 } 97 98 void fsl_edma_free_desc(struct virt_dma_desc *vdesc) 99 { 100 struct fsl_edma_desc *fsl_desc; 101 int i; 102 103 fsl_desc = to_fsl_edma_desc(vdesc); 104 for (i = 0; i < fsl_desc->n_tcds; i++) 105 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, 106 fsl_desc->tcd[i].ptcd); 107 kfree(fsl_desc); 108 } 109 EXPORT_SYMBOL_GPL(fsl_edma_free_desc); 110 111 int fsl_edma_terminate_all(struct dma_chan *chan) 112 { 113 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 114 unsigned long flags; 115 LIST_HEAD(head); 116 117 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 118 fsl_edma_disable_request(fsl_chan); 119 fsl_chan->edesc = NULL; 120 fsl_chan->idle = true; 121 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 122 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 123 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 124 return 0; 125 } 126 EXPORT_SYMBOL_GPL(fsl_edma_terminate_all); 127 128 int fsl_edma_pause(struct dma_chan *chan) 129 { 130 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 131 unsigned long flags; 132 133 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 134 if (fsl_chan->edesc) { 135 fsl_edma_disable_request(fsl_chan); 136 fsl_chan->status = DMA_PAUSED; 137 fsl_chan->idle = true; 138 } 139 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 140 return 0; 141 } 142 EXPORT_SYMBOL_GPL(fsl_edma_pause); 143 144 int fsl_edma_resume(struct dma_chan *chan) 145 { 146 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 147 unsigned long flags; 148 149 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 150 if (fsl_chan->edesc) { 151 fsl_edma_enable_request(fsl_chan); 152 fsl_chan->status = DMA_IN_PROGRESS; 153 fsl_chan->idle = false; 154 } 155 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 156 return 0; 157 } 158 EXPORT_SYMBOL_GPL(fsl_edma_resume); 159 160 int fsl_edma_slave_config(struct dma_chan *chan, 161 struct dma_slave_config *cfg) 162 { 163 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 164 165 fsl_chan->fsc.dir = cfg->direction; 166 if (cfg->direction == DMA_DEV_TO_MEM) { 167 fsl_chan->fsc.dev_addr = cfg->src_addr; 168 fsl_chan->fsc.addr_width = cfg->src_addr_width; 169 fsl_chan->fsc.burst = cfg->src_maxburst; 170 fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->src_addr_width); 171 } else if (cfg->direction == DMA_MEM_TO_DEV) { 172 fsl_chan->fsc.dev_addr = cfg->dst_addr; 173 fsl_chan->fsc.addr_width = cfg->dst_addr_width; 174 fsl_chan->fsc.burst = cfg->dst_maxburst; 175 fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->dst_addr_width); 176 } else 177 return -EINVAL; 178 179 return 0; 180 } 181 EXPORT_SYMBOL_GPL(fsl_edma_slave_config); 182 183 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, 184 struct virt_dma_desc *vdesc, bool in_progress) 185 { 186 struct fsl_edma_desc *edesc = fsl_chan->edesc; 187 struct edma_regs *regs = &fsl_chan->edma->regs; 188 u32 ch = fsl_chan->vchan.chan.chan_id; 189 enum dma_transfer_direction dir = fsl_chan->fsc.dir; 190 dma_addr_t cur_addr, dma_addr; 191 size_t len, size; 192 int i; 193 194 /* calculate the total size in this desc */ 195 for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) 196 len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 197 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 198 199 if (!in_progress) 200 return len; 201 202 if (dir == DMA_MEM_TO_DEV) 203 cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr); 204 else 205 cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr); 206 207 /* figure out the finished and calculate the residue */ 208 for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { 209 size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) 210 * le16_to_cpu(edesc->tcd[i].vtcd->biter); 211 if (dir == DMA_MEM_TO_DEV) 212 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); 213 else 214 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); 215 216 len -= size; 217 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { 218 len += dma_addr + size - cur_addr; 219 break; 220 } 221 } 222 223 return len; 224 } 225 226 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 227 dma_cookie_t cookie, struct dma_tx_state *txstate) 228 { 229 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 230 struct virt_dma_desc *vdesc; 231 enum dma_status status; 232 unsigned long flags; 233 234 status = dma_cookie_status(chan, cookie, txstate); 235 if (status == DMA_COMPLETE) 236 return status; 237 238 if (!txstate) 239 return fsl_chan->status; 240 241 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 242 vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); 243 if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) 244 txstate->residue = 245 fsl_edma_desc_residue(fsl_chan, vdesc, true); 246 else if (vdesc) 247 txstate->residue = 248 fsl_edma_desc_residue(fsl_chan, vdesc, false); 249 else 250 txstate->residue = 0; 251 252 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 253 254 return fsl_chan->status; 255 } 256 EXPORT_SYMBOL_GPL(fsl_edma_tx_status); 257 258 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, 259 struct fsl_edma_hw_tcd *tcd) 260 { 261 struct fsl_edma_engine *edma = fsl_chan->edma; 262 struct edma_regs *regs = &fsl_chan->edma->regs; 263 u32 ch = fsl_chan->vchan.chan.chan_id; 264 265 /* 266 * TCD parameters are stored in struct fsl_edma_hw_tcd in little 267 * endian format. However, we need to load the TCD registers in 268 * big- or little-endian obeying the eDMA engine model endian. 269 */ 270 edma_writew(edma, 0, ®s->tcd[ch].csr); 271 edma_writel(edma, le32_to_cpu(tcd->saddr), ®s->tcd[ch].saddr); 272 edma_writel(edma, le32_to_cpu(tcd->daddr), ®s->tcd[ch].daddr); 273 274 edma_writew(edma, le16_to_cpu(tcd->attr), ®s->tcd[ch].attr); 275 edma_writew(edma, le16_to_cpu(tcd->soff), ®s->tcd[ch].soff); 276 277 edma_writel(edma, le32_to_cpu(tcd->nbytes), ®s->tcd[ch].nbytes); 278 edma_writel(edma, le32_to_cpu(tcd->slast), ®s->tcd[ch].slast); 279 280 edma_writew(edma, le16_to_cpu(tcd->citer), ®s->tcd[ch].citer); 281 edma_writew(edma, le16_to_cpu(tcd->biter), ®s->tcd[ch].biter); 282 edma_writew(edma, le16_to_cpu(tcd->doff), ®s->tcd[ch].doff); 283 284 edma_writel(edma, le32_to_cpu(tcd->dlast_sga), 285 ®s->tcd[ch].dlast_sga); 286 287 edma_writew(edma, le16_to_cpu(tcd->csr), ®s->tcd[ch].csr); 288 } 289 290 static inline 291 void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, 292 u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, 293 u16 biter, u16 doff, u32 dlast_sga, bool major_int, 294 bool disable_req, bool enable_sg) 295 { 296 u16 csr = 0; 297 298 /* 299 * eDMA hardware SGs require the TCDs to be stored in little 300 * endian format irrespective of the register endian model. 301 * So we put the value in little endian in memory, waiting 302 * for fsl_edma_set_tcd_regs doing the swap. 303 */ 304 tcd->saddr = cpu_to_le32(src); 305 tcd->daddr = cpu_to_le32(dst); 306 307 tcd->attr = cpu_to_le16(attr); 308 309 tcd->soff = cpu_to_le16(soff); 310 311 tcd->nbytes = cpu_to_le32(nbytes); 312 tcd->slast = cpu_to_le32(slast); 313 314 tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); 315 tcd->doff = cpu_to_le16(doff); 316 317 tcd->dlast_sga = cpu_to_le32(dlast_sga); 318 319 tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); 320 if (major_int) 321 csr |= EDMA_TCD_CSR_INT_MAJOR; 322 323 if (disable_req) 324 csr |= EDMA_TCD_CSR_D_REQ; 325 326 if (enable_sg) 327 csr |= EDMA_TCD_CSR_E_SG; 328 329 tcd->csr = cpu_to_le16(csr); 330 } 331 332 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, 333 int sg_len) 334 { 335 struct fsl_edma_desc *fsl_desc; 336 int i; 337 338 fsl_desc = kzalloc(sizeof(*fsl_desc) + 339 sizeof(struct fsl_edma_sw_tcd) * 340 sg_len, GFP_NOWAIT); 341 if (!fsl_desc) 342 return NULL; 343 344 fsl_desc->echan = fsl_chan; 345 fsl_desc->n_tcds = sg_len; 346 for (i = 0; i < sg_len; i++) { 347 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, 348 GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); 349 if (!fsl_desc->tcd[i].vtcd) 350 goto err; 351 } 352 return fsl_desc; 353 354 err: 355 while (--i >= 0) 356 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, 357 fsl_desc->tcd[i].ptcd); 358 kfree(fsl_desc); 359 return NULL; 360 } 361 362 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 363 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 364 size_t period_len, enum dma_transfer_direction direction, 365 unsigned long flags) 366 { 367 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 368 struct fsl_edma_desc *fsl_desc; 369 dma_addr_t dma_buf_next; 370 int sg_len, i; 371 u32 src_addr, dst_addr, last_sg, nbytes; 372 u16 soff, doff, iter; 373 374 if (!is_slave_direction(fsl_chan->fsc.dir)) 375 return NULL; 376 377 sg_len = buf_len / period_len; 378 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 379 if (!fsl_desc) 380 return NULL; 381 fsl_desc->iscyclic = true; 382 383 dma_buf_next = dma_addr; 384 nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; 385 iter = period_len / nbytes; 386 387 for (i = 0; i < sg_len; i++) { 388 if (dma_buf_next >= dma_addr + buf_len) 389 dma_buf_next = dma_addr; 390 391 /* get next sg's physical address */ 392 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 393 394 if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { 395 src_addr = dma_buf_next; 396 dst_addr = fsl_chan->fsc.dev_addr; 397 soff = fsl_chan->fsc.addr_width; 398 doff = 0; 399 } else { 400 src_addr = fsl_chan->fsc.dev_addr; 401 dst_addr = dma_buf_next; 402 soff = 0; 403 doff = fsl_chan->fsc.addr_width; 404 } 405 406 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr, 407 fsl_chan->fsc.attr, soff, nbytes, 0, iter, 408 iter, doff, last_sg, true, false, true); 409 dma_buf_next += period_len; 410 } 411 412 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 413 } 414 EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic); 415 416 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 417 struct dma_chan *chan, struct scatterlist *sgl, 418 unsigned int sg_len, enum dma_transfer_direction direction, 419 unsigned long flags, void *context) 420 { 421 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 422 struct fsl_edma_desc *fsl_desc; 423 struct scatterlist *sg; 424 u32 src_addr, dst_addr, last_sg, nbytes; 425 u16 soff, doff, iter; 426 int i; 427 428 if (!is_slave_direction(fsl_chan->fsc.dir)) 429 return NULL; 430 431 fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); 432 if (!fsl_desc) 433 return NULL; 434 fsl_desc->iscyclic = false; 435 436 nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; 437 for_each_sg(sgl, sg, sg_len, i) { 438 /* get next sg's physical address */ 439 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; 440 441 if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { 442 src_addr = sg_dma_address(sg); 443 dst_addr = fsl_chan->fsc.dev_addr; 444 soff = fsl_chan->fsc.addr_width; 445 doff = 0; 446 } else { 447 src_addr = fsl_chan->fsc.dev_addr; 448 dst_addr = sg_dma_address(sg); 449 soff = 0; 450 doff = fsl_chan->fsc.addr_width; 451 } 452 453 iter = sg_dma_len(sg) / nbytes; 454 if (i < sg_len - 1) { 455 last_sg = fsl_desc->tcd[(i + 1)].ptcd; 456 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 457 dst_addr, fsl_chan->fsc.attr, soff, 458 nbytes, 0, iter, iter, doff, last_sg, 459 false, false, true); 460 } else { 461 last_sg = 0; 462 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, 463 dst_addr, fsl_chan->fsc.attr, soff, 464 nbytes, 0, iter, iter, doff, last_sg, 465 true, true, false); 466 } 467 } 468 469 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); 470 } 471 EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg); 472 473 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) 474 { 475 struct virt_dma_desc *vdesc; 476 477 vdesc = vchan_next_desc(&fsl_chan->vchan); 478 if (!vdesc) 479 return; 480 fsl_chan->edesc = to_fsl_edma_desc(vdesc); 481 fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); 482 fsl_edma_enable_request(fsl_chan); 483 fsl_chan->status = DMA_IN_PROGRESS; 484 fsl_chan->idle = false; 485 } 486 EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc); 487 488 void fsl_edma_issue_pending(struct dma_chan *chan) 489 { 490 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 491 unsigned long flags; 492 493 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 494 495 if (unlikely(fsl_chan->pm_state != RUNNING)) { 496 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 497 /* cannot submit due to suspend */ 498 return; 499 } 500 501 if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) 502 fsl_edma_xfer_desc(fsl_chan); 503 504 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 505 } 506 EXPORT_SYMBOL_GPL(fsl_edma_issue_pending); 507 508 int fsl_edma_alloc_chan_resources(struct dma_chan *chan) 509 { 510 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 511 512 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, 513 sizeof(struct fsl_edma_hw_tcd), 514 32, 0); 515 return 0; 516 } 517 EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources); 518 519 void fsl_edma_free_chan_resources(struct dma_chan *chan) 520 { 521 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 522 unsigned long flags; 523 LIST_HEAD(head); 524 525 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 526 fsl_edma_disable_request(fsl_chan); 527 fsl_edma_chan_mux(fsl_chan, 0, false); 528 fsl_chan->edesc = NULL; 529 vchan_get_all_descriptors(&fsl_chan->vchan, &head); 530 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 531 532 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); 533 dma_pool_destroy(fsl_chan->tcd_pool); 534 fsl_chan->tcd_pool = NULL; 535 } 536 EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources); 537 538 void fsl_edma_cleanup_vchan(struct dma_device *dmadev) 539 { 540 struct fsl_edma_chan *chan, *_chan; 541 542 list_for_each_entry_safe(chan, _chan, 543 &dmadev->channels, vchan.chan.device_node) { 544 list_del(&chan->vchan.chan.device_node); 545 tasklet_kill(&chan->vchan.task); 546 } 547 } 548 EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan); 549 550 /* 551 * On the 32 channels Vybrid/mpc577x edma version (here called "v1"), 552 * register offsets are different compared to ColdFire mcf5441x 64 channels 553 * edma (here called "v2"). 554 * 555 * This function sets up register offsets as per proper declared version 556 * so must be called in xxx_edma_probe() just after setting the 557 * edma "version" and "membase" appropriately. 558 */ 559 void fsl_edma_setup_regs(struct fsl_edma_engine *edma) 560 { 561 edma->regs.cr = edma->membase + EDMA_CR; 562 edma->regs.es = edma->membase + EDMA_ES; 563 edma->regs.erql = edma->membase + EDMA_ERQ; 564 edma->regs.eeil = edma->membase + EDMA_EEI; 565 566 edma->regs.serq = edma->membase + ((edma->version == v1) ? 567 EDMA_SERQ : EDMA64_SERQ); 568 edma->regs.cerq = edma->membase + ((edma->version == v1) ? 569 EDMA_CERQ : EDMA64_CERQ); 570 edma->regs.seei = edma->membase + ((edma->version == v1) ? 571 EDMA_SEEI : EDMA64_SEEI); 572 edma->regs.ceei = edma->membase + ((edma->version == v1) ? 573 EDMA_CEEI : EDMA64_CEEI); 574 edma->regs.cint = edma->membase + ((edma->version == v1) ? 575 EDMA_CINT : EDMA64_CINT); 576 edma->regs.cerr = edma->membase + ((edma->version == v1) ? 577 EDMA_CERR : EDMA64_CERR); 578 edma->regs.ssrt = edma->membase + ((edma->version == v1) ? 579 EDMA_SSRT : EDMA64_SSRT); 580 edma->regs.cdne = edma->membase + ((edma->version == v1) ? 581 EDMA_CDNE : EDMA64_CDNE); 582 edma->regs.intl = edma->membase + ((edma->version == v1) ? 583 EDMA_INTR : EDMA64_INTL); 584 edma->regs.errl = edma->membase + ((edma->version == v1) ? 585 EDMA_ERR : EDMA64_ERRL); 586 587 if (edma->version == v2) { 588 edma->regs.erqh = edma->membase + EDMA64_ERQH; 589 edma->regs.eeih = edma->membase + EDMA64_EEIH; 590 edma->regs.errh = edma->membase + EDMA64_ERRH; 591 edma->regs.inth = edma->membase + EDMA64_INTH; 592 } 593 594 edma->regs.tcd = edma->membase + EDMA_TCD; 595 } 596 EXPORT_SYMBOL_GPL(fsl_edma_setup_regs); 597 598 MODULE_LICENSE("GPL v2"); 599