1 /* 2 * Platform driver for the Synopsys DesignWare DMA Controller 3 * 4 * Copyright (C) 2007-2008 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * Copyright (C) 2013 Intel Corporation 7 * 8 * Some parts of this driver are derived from the original dw_dmac. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/device.h> 17 #include <linux/clk.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/platform_device.h> 20 #include <linux/dmaengine.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/of.h> 23 #include <linux/of_dma.h> 24 #include <linux/acpi.h> 25 #include <linux/acpi_dma.h> 26 27 #include "internal.h" 28 29 #define DRV_NAME "dw_dmac" 30 31 static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec, 32 struct of_dma *ofdma) 33 { 34 struct dw_dma *dw = ofdma->of_dma_data; 35 struct dw_dma_slave slave = { 36 .dma_dev = dw->dma.dev, 37 }; 38 dma_cap_mask_t cap; 39 40 if (dma_spec->args_count != 3) 41 return NULL; 42 43 slave.src_id = dma_spec->args[0]; 44 slave.dst_id = dma_spec->args[0]; 45 slave.m_master = dma_spec->args[1]; 46 slave.p_master = dma_spec->args[2]; 47 48 if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS || 49 slave.dst_id >= DW_DMA_MAX_NR_REQUESTS || 50 slave.m_master >= dw->pdata->nr_masters || 51 slave.p_master >= dw->pdata->nr_masters)) 52 return NULL; 53 54 dma_cap_zero(cap); 55 dma_cap_set(DMA_SLAVE, cap); 56 57 /* TODO: there should be a simpler way to do this */ 58 return dma_request_channel(cap, dw_dma_filter, &slave); 59 } 60 61 #ifdef CONFIG_ACPI 62 static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param) 63 { 64 struct acpi_dma_spec *dma_spec = param; 65 struct dw_dma_slave slave = { 66 .dma_dev = dma_spec->dev, 67 .src_id = dma_spec->slave_id, 68 .dst_id = dma_spec->slave_id, 69 .m_master = 0, 70 .p_master = 1, 71 }; 72 73 return dw_dma_filter(chan, &slave); 74 } 75 76 static void dw_dma_acpi_controller_register(struct dw_dma *dw) 77 { 78 struct device *dev = dw->dma.dev; 79 struct acpi_dma_filter_info *info; 80 int ret; 81 82 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 83 if (!info) 84 return; 85 86 dma_cap_zero(info->dma_cap); 87 dma_cap_set(DMA_SLAVE, info->dma_cap); 88 info->filter_fn = dw_dma_acpi_filter; 89 90 ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate, 91 info); 92 if (ret) 93 dev_err(dev, "could not register acpi_dma_controller\n"); 94 } 95 #else /* !CONFIG_ACPI */ 96 static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {} 97 #endif /* !CONFIG_ACPI */ 98 99 #ifdef CONFIG_OF 100 static struct dw_dma_platform_data * 101 dw_dma_parse_dt(struct platform_device *pdev) 102 { 103 struct device_node *np = pdev->dev.of_node; 104 struct dw_dma_platform_data *pdata; 105 u32 tmp, arr[DW_DMA_MAX_NR_MASTERS], mb[DW_DMA_MAX_NR_CHANNELS]; 106 u32 nr_masters; 107 u32 nr_channels; 108 109 if (!np) { 110 dev_err(&pdev->dev, "Missing DT data\n"); 111 return NULL; 112 } 113 114 if (of_property_read_u32(np, "dma-masters", &nr_masters)) 115 return NULL; 116 if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS) 117 return NULL; 118 119 if (of_property_read_u32(np, "dma-channels", &nr_channels)) 120 return NULL; 121 if (nr_channels > DW_DMA_MAX_NR_CHANNELS) 122 return NULL; 123 124 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 125 if (!pdata) 126 return NULL; 127 128 pdata->nr_masters = nr_masters; 129 pdata->nr_channels = nr_channels; 130 131 if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) 132 pdata->chan_allocation_order = (unsigned char)tmp; 133 134 if (!of_property_read_u32(np, "chan_priority", &tmp)) 135 pdata->chan_priority = tmp; 136 137 if (!of_property_read_u32(np, "block_size", &tmp)) 138 pdata->block_size = tmp; 139 140 if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) { 141 for (tmp = 0; tmp < nr_masters; tmp++) 142 pdata->data_width[tmp] = arr[tmp]; 143 } else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) { 144 for (tmp = 0; tmp < nr_masters; tmp++) 145 pdata->data_width[tmp] = BIT(arr[tmp] & 0x07); 146 } 147 148 if (!of_property_read_u32_array(np, "multi-block", mb, nr_channels)) { 149 for (tmp = 0; tmp < nr_channels; tmp++) 150 pdata->multi_block[tmp] = mb[tmp]; 151 } else { 152 for (tmp = 0; tmp < nr_channels; tmp++) 153 pdata->multi_block[tmp] = 1; 154 } 155 156 if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) { 157 if (tmp > CHAN_PROTCTL_MASK) 158 return NULL; 159 pdata->protctl = tmp; 160 } 161 162 return pdata; 163 } 164 #else 165 static inline struct dw_dma_platform_data * 166 dw_dma_parse_dt(struct platform_device *pdev) 167 { 168 return NULL; 169 } 170 #endif 171 172 static int dw_probe(struct platform_device *pdev) 173 { 174 struct dw_dma_chip *chip; 175 struct device *dev = &pdev->dev; 176 struct resource *mem; 177 const struct dw_dma_platform_data *pdata; 178 int err; 179 180 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 181 if (!chip) 182 return -ENOMEM; 183 184 chip->irq = platform_get_irq(pdev, 0); 185 if (chip->irq < 0) 186 return chip->irq; 187 188 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 189 chip->regs = devm_ioremap_resource(dev, mem); 190 if (IS_ERR(chip->regs)) 191 return PTR_ERR(chip->regs); 192 193 err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 194 if (err) 195 return err; 196 197 pdata = dev_get_platdata(dev); 198 if (!pdata) 199 pdata = dw_dma_parse_dt(pdev); 200 201 chip->dev = dev; 202 chip->id = pdev->id; 203 chip->pdata = pdata; 204 205 chip->clk = devm_clk_get(chip->dev, "hclk"); 206 if (IS_ERR(chip->clk)) 207 return PTR_ERR(chip->clk); 208 err = clk_prepare_enable(chip->clk); 209 if (err) 210 return err; 211 212 pm_runtime_enable(&pdev->dev); 213 214 err = dw_dma_probe(chip); 215 if (err) 216 goto err_dw_dma_probe; 217 218 platform_set_drvdata(pdev, chip); 219 220 if (pdev->dev.of_node) { 221 err = of_dma_controller_register(pdev->dev.of_node, 222 dw_dma_of_xlate, chip->dw); 223 if (err) 224 dev_err(&pdev->dev, 225 "could not register of_dma_controller\n"); 226 } 227 228 if (ACPI_HANDLE(&pdev->dev)) 229 dw_dma_acpi_controller_register(chip->dw); 230 231 return 0; 232 233 err_dw_dma_probe: 234 pm_runtime_disable(&pdev->dev); 235 clk_disable_unprepare(chip->clk); 236 return err; 237 } 238 239 static int dw_remove(struct platform_device *pdev) 240 { 241 struct dw_dma_chip *chip = platform_get_drvdata(pdev); 242 243 if (pdev->dev.of_node) 244 of_dma_controller_free(pdev->dev.of_node); 245 246 dw_dma_remove(chip); 247 pm_runtime_disable(&pdev->dev); 248 clk_disable_unprepare(chip->clk); 249 250 return 0; 251 } 252 253 static void dw_shutdown(struct platform_device *pdev) 254 { 255 struct dw_dma_chip *chip = platform_get_drvdata(pdev); 256 257 /* 258 * We have to call do_dw_dma_disable() to stop any ongoing transfer. On 259 * some platforms we can't do that since DMA device is powered off. 260 * Moreover we have no possibility to check if the platform is affected 261 * or not. That's why we call pm_runtime_get_sync() / pm_runtime_put() 262 * unconditionally. On the other hand we can't use 263 * pm_runtime_suspended() because runtime PM framework is not fully 264 * used by the driver. 265 */ 266 pm_runtime_get_sync(chip->dev); 267 do_dw_dma_disable(chip); 268 pm_runtime_put_sync_suspend(chip->dev); 269 270 clk_disable_unprepare(chip->clk); 271 } 272 273 #ifdef CONFIG_OF 274 static const struct of_device_id dw_dma_of_id_table[] = { 275 { .compatible = "snps,dma-spear1340" }, 276 {} 277 }; 278 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); 279 #endif 280 281 #ifdef CONFIG_ACPI 282 static const struct acpi_device_id dw_dma_acpi_id_table[] = { 283 { "INTL9C60", 0 }, 284 { "80862286", 0 }, 285 { "808622C0", 0 }, 286 { } 287 }; 288 MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table); 289 #endif 290 291 #ifdef CONFIG_PM_SLEEP 292 293 static int dw_suspend_late(struct device *dev) 294 { 295 struct dw_dma_chip *chip = dev_get_drvdata(dev); 296 297 do_dw_dma_disable(chip); 298 clk_disable_unprepare(chip->clk); 299 300 return 0; 301 } 302 303 static int dw_resume_early(struct device *dev) 304 { 305 struct dw_dma_chip *chip = dev_get_drvdata(dev); 306 int ret; 307 308 ret = clk_prepare_enable(chip->clk); 309 if (ret) 310 return ret; 311 312 return do_dw_dma_enable(chip); 313 } 314 315 #endif /* CONFIG_PM_SLEEP */ 316 317 static const struct dev_pm_ops dw_dev_pm_ops = { 318 SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early) 319 }; 320 321 static struct platform_driver dw_driver = { 322 .probe = dw_probe, 323 .remove = dw_remove, 324 .shutdown = dw_shutdown, 325 .driver = { 326 .name = DRV_NAME, 327 .pm = &dw_dev_pm_ops, 328 .of_match_table = of_match_ptr(dw_dma_of_id_table), 329 .acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table), 330 }, 331 }; 332 333 static int __init dw_init(void) 334 { 335 return platform_driver_register(&dw_driver); 336 } 337 subsys_initcall(dw_init); 338 339 static void __exit dw_exit(void) 340 { 341 platform_driver_unregister(&dw_driver); 342 } 343 module_exit(dw_exit); 344 345 MODULE_LICENSE("GPL v2"); 346 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver"); 347 MODULE_ALIAS("platform:" DRV_NAME); 348