1 /* 2 * Core driver for the Synopsys DesignWare DMA Controller 3 * 4 * Copyright (C) 2007-2008 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * Copyright (C) 2013 Intel Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/dmapool.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/mm.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/pm_runtime.h> 26 27 #include "../dmaengine.h" 28 #include "internal.h" 29 30 /* 31 * This supports the Synopsys "DesignWare AHB Central DMA Controller", 32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all 33 * of which use ARM any more). See the "Databook" from Synopsys for 34 * information beyond what licensees probably provide. 35 * 36 * The driver has been tested with the Atmel AT32AP7000, which does not 37 * support descriptor writeback. 38 */ 39 40 #define DWC_DEFAULT_CTLLO(_chan) ({ \ 41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ 42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ 43 bool _is_slave = is_slave_direction(_dwc->direction); \ 44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ 45 DW_DMA_MSIZE_16; \ 46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ 47 DW_DMA_MSIZE_16; \ 48 u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \ 49 _dwc->dws.p_master : _dwc->dws.m_master; \ 50 u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \ 51 _dwc->dws.p_master : _dwc->dws.m_master; \ 52 \ 53 (DWC_CTLL_DST_MSIZE(_dmsize) \ 54 | DWC_CTLL_SRC_MSIZE(_smsize) \ 55 | DWC_CTLL_LLP_D_EN \ 56 | DWC_CTLL_LLP_S_EN \ 57 | DWC_CTLL_DMS(_dms) \ 58 | DWC_CTLL_SMS(_sms)); \ 59 }) 60 61 /* The set of bus widths supported by the DMA controller */ 62 #define DW_DMA_BUSWIDTHS \ 63 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 64 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 65 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 66 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) 67 68 /*----------------------------------------------------------------------*/ 69 70 static struct device *chan2dev(struct dma_chan *chan) 71 { 72 return &chan->dev->device; 73 } 74 75 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) 76 { 77 return to_dw_desc(dwc->active_list.next); 78 } 79 80 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) 81 { 82 struct dw_desc *desc = txd_to_dw_desc(tx); 83 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); 84 dma_cookie_t cookie; 85 unsigned long flags; 86 87 spin_lock_irqsave(&dwc->lock, flags); 88 cookie = dma_cookie_assign(tx); 89 90 /* 91 * REVISIT: We should attempt to chain as many descriptors as 92 * possible, perhaps even appending to those already submitted 93 * for DMA. But this is hard to do in a race-free manner. 94 */ 95 96 list_add_tail(&desc->desc_node, &dwc->queue); 97 spin_unlock_irqrestore(&dwc->lock, flags); 98 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", 99 __func__, desc->txd.cookie); 100 101 return cookie; 102 } 103 104 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) 105 { 106 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 107 struct dw_desc *desc; 108 dma_addr_t phys; 109 110 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); 111 if (!desc) 112 return NULL; 113 114 dwc->descs_allocated++; 115 INIT_LIST_HEAD(&desc->tx_list); 116 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); 117 desc->txd.tx_submit = dwc_tx_submit; 118 desc->txd.flags = DMA_CTRL_ACK; 119 desc->txd.phys = phys; 120 return desc; 121 } 122 123 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) 124 { 125 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 126 struct dw_desc *child, *_next; 127 128 if (unlikely(!desc)) 129 return; 130 131 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { 132 list_del(&child->desc_node); 133 dma_pool_free(dw->desc_pool, child, child->txd.phys); 134 dwc->descs_allocated--; 135 } 136 137 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); 138 dwc->descs_allocated--; 139 } 140 141 static void dwc_initialize(struct dw_dma_chan *dwc) 142 { 143 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 144 u32 cfghi = DWC_CFGH_FIFO_MODE; 145 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); 146 bool hs_polarity = dwc->dws.hs_polarity; 147 148 if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) 149 return; 150 151 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); 152 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); 153 154 /* Set polarity of handshake interface */ 155 cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0; 156 157 channel_writel(dwc, CFG_LO, cfglo); 158 channel_writel(dwc, CFG_HI, cfghi); 159 160 /* Enable interrupts */ 161 channel_set_bit(dw, MASK.XFER, dwc->mask); 162 channel_set_bit(dw, MASK.ERROR, dwc->mask); 163 164 set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); 165 } 166 167 /*----------------------------------------------------------------------*/ 168 169 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) 170 { 171 dev_err(chan2dev(&dwc->chan), 172 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", 173 channel_readl(dwc, SAR), 174 channel_readl(dwc, DAR), 175 channel_readl(dwc, LLP), 176 channel_readl(dwc, CTL_HI), 177 channel_readl(dwc, CTL_LO)); 178 } 179 180 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) 181 { 182 channel_clear_bit(dw, CH_EN, dwc->mask); 183 while (dma_readl(dw, CH_EN) & dwc->mask) 184 cpu_relax(); 185 } 186 187 /*----------------------------------------------------------------------*/ 188 189 /* Perform single block transfer */ 190 static inline void dwc_do_single_block(struct dw_dma_chan *dwc, 191 struct dw_desc *desc) 192 { 193 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 194 u32 ctllo; 195 196 /* 197 * Software emulation of LLP mode relies on interrupts to continue 198 * multi block transfer. 199 */ 200 ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; 201 202 channel_writel(dwc, SAR, lli_read(desc, sar)); 203 channel_writel(dwc, DAR, lli_read(desc, dar)); 204 channel_writel(dwc, CTL_LO, ctllo); 205 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); 206 channel_set_bit(dw, CH_EN, dwc->mask); 207 208 /* Move pointer to next descriptor */ 209 dwc->tx_node_active = dwc->tx_node_active->next; 210 } 211 212 /* Called with dwc->lock held and bh disabled */ 213 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) 214 { 215 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 216 u8 lms = DWC_LLP_LMS(dwc->dws.m_master); 217 unsigned long was_soft_llp; 218 219 /* ASSERT: channel is idle */ 220 if (dma_readl(dw, CH_EN) & dwc->mask) { 221 dev_err(chan2dev(&dwc->chan), 222 "%s: BUG: Attempted to start non-idle channel\n", 223 __func__); 224 dwc_dump_chan_regs(dwc); 225 226 /* The tasklet will hopefully advance the queue... */ 227 return; 228 } 229 230 if (dwc->nollp) { 231 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, 232 &dwc->flags); 233 if (was_soft_llp) { 234 dev_err(chan2dev(&dwc->chan), 235 "BUG: Attempted to start new LLP transfer inside ongoing one\n"); 236 return; 237 } 238 239 dwc_initialize(dwc); 240 241 first->residue = first->total_len; 242 dwc->tx_node_active = &first->tx_list; 243 244 /* Submit first block */ 245 dwc_do_single_block(dwc, first); 246 247 return; 248 } 249 250 dwc_initialize(dwc); 251 252 channel_writel(dwc, LLP, first->txd.phys | lms); 253 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 254 channel_writel(dwc, CTL_HI, 0); 255 channel_set_bit(dw, CH_EN, dwc->mask); 256 } 257 258 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) 259 { 260 struct dw_desc *desc; 261 262 if (list_empty(&dwc->queue)) 263 return; 264 265 list_move(dwc->queue.next, &dwc->active_list); 266 desc = dwc_first_active(dwc); 267 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); 268 dwc_dostart(dwc, desc); 269 } 270 271 /*----------------------------------------------------------------------*/ 272 273 static void 274 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, 275 bool callback_required) 276 { 277 dma_async_tx_callback callback = NULL; 278 void *param = NULL; 279 struct dma_async_tx_descriptor *txd = &desc->txd; 280 struct dw_desc *child; 281 unsigned long flags; 282 283 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); 284 285 spin_lock_irqsave(&dwc->lock, flags); 286 dma_cookie_complete(txd); 287 if (callback_required) { 288 callback = txd->callback; 289 param = txd->callback_param; 290 } 291 292 /* async_tx_ack */ 293 list_for_each_entry(child, &desc->tx_list, desc_node) 294 async_tx_ack(&child->txd); 295 async_tx_ack(&desc->txd); 296 dwc_desc_put(dwc, desc); 297 spin_unlock_irqrestore(&dwc->lock, flags); 298 299 if (callback) 300 callback(param); 301 } 302 303 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) 304 { 305 struct dw_desc *desc, *_desc; 306 LIST_HEAD(list); 307 unsigned long flags; 308 309 spin_lock_irqsave(&dwc->lock, flags); 310 if (dma_readl(dw, CH_EN) & dwc->mask) { 311 dev_err(chan2dev(&dwc->chan), 312 "BUG: XFER bit set, but channel not idle!\n"); 313 314 /* Try to continue after resetting the channel... */ 315 dwc_chan_disable(dw, dwc); 316 } 317 318 /* 319 * Submit queued descriptors ASAP, i.e. before we go through 320 * the completed ones. 321 */ 322 list_splice_init(&dwc->active_list, &list); 323 dwc_dostart_first_queued(dwc); 324 325 spin_unlock_irqrestore(&dwc->lock, flags); 326 327 list_for_each_entry_safe(desc, _desc, &list, desc_node) 328 dwc_descriptor_complete(dwc, desc, true); 329 } 330 331 /* Returns how many bytes were already received from source */ 332 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) 333 { 334 u32 ctlhi = channel_readl(dwc, CTL_HI); 335 u32 ctllo = channel_readl(dwc, CTL_LO); 336 337 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); 338 } 339 340 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) 341 { 342 dma_addr_t llp; 343 struct dw_desc *desc, *_desc; 344 struct dw_desc *child; 345 u32 status_xfer; 346 unsigned long flags; 347 348 spin_lock_irqsave(&dwc->lock, flags); 349 llp = channel_readl(dwc, LLP); 350 status_xfer = dma_readl(dw, RAW.XFER); 351 352 if (status_xfer & dwc->mask) { 353 /* Everything we've submitted is done */ 354 dma_writel(dw, CLEAR.XFER, dwc->mask); 355 356 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 357 struct list_head *head, *active = dwc->tx_node_active; 358 359 /* 360 * We are inside first active descriptor. 361 * Otherwise something is really wrong. 362 */ 363 desc = dwc_first_active(dwc); 364 365 head = &desc->tx_list; 366 if (active != head) { 367 /* Update residue to reflect last sent descriptor */ 368 if (active == head->next) 369 desc->residue -= desc->len; 370 else 371 desc->residue -= to_dw_desc(active->prev)->len; 372 373 child = to_dw_desc(active); 374 375 /* Submit next block */ 376 dwc_do_single_block(dwc, child); 377 378 spin_unlock_irqrestore(&dwc->lock, flags); 379 return; 380 } 381 382 /* We are done here */ 383 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 384 } 385 386 spin_unlock_irqrestore(&dwc->lock, flags); 387 388 dwc_complete_all(dw, dwc); 389 return; 390 } 391 392 if (list_empty(&dwc->active_list)) { 393 spin_unlock_irqrestore(&dwc->lock, flags); 394 return; 395 } 396 397 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 398 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); 399 spin_unlock_irqrestore(&dwc->lock, flags); 400 return; 401 } 402 403 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); 404 405 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { 406 /* Initial residue value */ 407 desc->residue = desc->total_len; 408 409 /* Check first descriptors addr */ 410 if (desc->txd.phys == DWC_LLP_LOC(llp)) { 411 spin_unlock_irqrestore(&dwc->lock, flags); 412 return; 413 } 414 415 /* Check first descriptors llp */ 416 if (lli_read(desc, llp) == llp) { 417 /* This one is currently in progress */ 418 desc->residue -= dwc_get_sent(dwc); 419 spin_unlock_irqrestore(&dwc->lock, flags); 420 return; 421 } 422 423 desc->residue -= desc->len; 424 list_for_each_entry(child, &desc->tx_list, desc_node) { 425 if (lli_read(child, llp) == llp) { 426 /* Currently in progress */ 427 desc->residue -= dwc_get_sent(dwc); 428 spin_unlock_irqrestore(&dwc->lock, flags); 429 return; 430 } 431 desc->residue -= child->len; 432 } 433 434 /* 435 * No descriptors so far seem to be in progress, i.e. 436 * this one must be done. 437 */ 438 spin_unlock_irqrestore(&dwc->lock, flags); 439 dwc_descriptor_complete(dwc, desc, true); 440 spin_lock_irqsave(&dwc->lock, flags); 441 } 442 443 dev_err(chan2dev(&dwc->chan), 444 "BUG: All descriptors done, but channel not idle!\n"); 445 446 /* Try to continue after resetting the channel... */ 447 dwc_chan_disable(dw, dwc); 448 449 dwc_dostart_first_queued(dwc); 450 spin_unlock_irqrestore(&dwc->lock, flags); 451 } 452 453 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) 454 { 455 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", 456 lli_read(desc, sar), 457 lli_read(desc, dar), 458 lli_read(desc, llp), 459 lli_read(desc, ctlhi), 460 lli_read(desc, ctllo)); 461 } 462 463 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) 464 { 465 struct dw_desc *bad_desc; 466 struct dw_desc *child; 467 unsigned long flags; 468 469 dwc_scan_descriptors(dw, dwc); 470 471 spin_lock_irqsave(&dwc->lock, flags); 472 473 /* 474 * The descriptor currently at the head of the active list is 475 * borked. Since we don't have any way to report errors, we'll 476 * just have to scream loudly and try to carry on. 477 */ 478 bad_desc = dwc_first_active(dwc); 479 list_del_init(&bad_desc->desc_node); 480 list_move(dwc->queue.next, dwc->active_list.prev); 481 482 /* Clear the error flag and try to restart the controller */ 483 dma_writel(dw, CLEAR.ERROR, dwc->mask); 484 if (!list_empty(&dwc->active_list)) 485 dwc_dostart(dwc, dwc_first_active(dwc)); 486 487 /* 488 * WARN may seem harsh, but since this only happens 489 * when someone submits a bad physical address in a 490 * descriptor, we should consider ourselves lucky that the 491 * controller flagged an error instead of scribbling over 492 * random memory locations. 493 */ 494 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" 495 " cookie: %d\n", bad_desc->txd.cookie); 496 dwc_dump_lli(dwc, bad_desc); 497 list_for_each_entry(child, &bad_desc->tx_list, desc_node) 498 dwc_dump_lli(dwc, child); 499 500 spin_unlock_irqrestore(&dwc->lock, flags); 501 502 /* Pretend the descriptor completed successfully */ 503 dwc_descriptor_complete(dwc, bad_desc, true); 504 } 505 506 /* --------------------- Cyclic DMA API extensions -------------------- */ 507 508 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) 509 { 510 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 511 return channel_readl(dwc, SAR); 512 } 513 EXPORT_SYMBOL(dw_dma_get_src_addr); 514 515 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) 516 { 517 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 518 return channel_readl(dwc, DAR); 519 } 520 EXPORT_SYMBOL(dw_dma_get_dst_addr); 521 522 /* Called with dwc->lock held and all DMAC interrupts disabled */ 523 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, 524 u32 status_block, u32 status_err, u32 status_xfer) 525 { 526 unsigned long flags; 527 528 if (status_block & dwc->mask) { 529 void (*callback)(void *param); 530 void *callback_param; 531 532 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", 533 channel_readl(dwc, LLP)); 534 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 535 536 callback = dwc->cdesc->period_callback; 537 callback_param = dwc->cdesc->period_callback_param; 538 539 if (callback) 540 callback(callback_param); 541 } 542 543 /* 544 * Error and transfer complete are highly unlikely, and will most 545 * likely be due to a configuration error by the user. 546 */ 547 if (unlikely(status_err & dwc->mask) || 548 unlikely(status_xfer & dwc->mask)) { 549 unsigned int i; 550 551 dev_err(chan2dev(&dwc->chan), 552 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", 553 status_xfer ? "xfer" : "error"); 554 555 spin_lock_irqsave(&dwc->lock, flags); 556 557 dwc_dump_chan_regs(dwc); 558 559 dwc_chan_disable(dw, dwc); 560 561 /* Make sure DMA does not restart by loading a new list */ 562 channel_writel(dwc, LLP, 0); 563 channel_writel(dwc, CTL_LO, 0); 564 channel_writel(dwc, CTL_HI, 0); 565 566 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 567 dma_writel(dw, CLEAR.ERROR, dwc->mask); 568 dma_writel(dw, CLEAR.XFER, dwc->mask); 569 570 for (i = 0; i < dwc->cdesc->periods; i++) 571 dwc_dump_lli(dwc, dwc->cdesc->desc[i]); 572 573 spin_unlock_irqrestore(&dwc->lock, flags); 574 } 575 576 /* Re-enable interrupts */ 577 channel_set_bit(dw, MASK.BLOCK, dwc->mask); 578 } 579 580 /* ------------------------------------------------------------------------- */ 581 582 static void dw_dma_tasklet(unsigned long data) 583 { 584 struct dw_dma *dw = (struct dw_dma *)data; 585 struct dw_dma_chan *dwc; 586 u32 status_block; 587 u32 status_xfer; 588 u32 status_err; 589 unsigned int i; 590 591 status_block = dma_readl(dw, RAW.BLOCK); 592 status_xfer = dma_readl(dw, RAW.XFER); 593 status_err = dma_readl(dw, RAW.ERROR); 594 595 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); 596 597 for (i = 0; i < dw->dma.chancnt; i++) { 598 dwc = &dw->chan[i]; 599 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) 600 dwc_handle_cyclic(dw, dwc, status_block, status_err, 601 status_xfer); 602 else if (status_err & (1 << i)) 603 dwc_handle_error(dw, dwc); 604 else if (status_xfer & (1 << i)) 605 dwc_scan_descriptors(dw, dwc); 606 } 607 608 /* Re-enable interrupts */ 609 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); 610 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); 611 } 612 613 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) 614 { 615 struct dw_dma *dw = dev_id; 616 u32 status; 617 618 /* Check if we have any interrupt from the DMAC which is not in use */ 619 if (!dw->in_use) 620 return IRQ_NONE; 621 622 status = dma_readl(dw, STATUS_INT); 623 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); 624 625 /* Check if we have any interrupt from the DMAC */ 626 if (!status) 627 return IRQ_NONE; 628 629 /* 630 * Just disable the interrupts. We'll turn them back on in the 631 * softirq handler. 632 */ 633 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 634 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 635 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 636 637 status = dma_readl(dw, STATUS_INT); 638 if (status) { 639 dev_err(dw->dma.dev, 640 "BUG: Unexpected interrupts pending: 0x%x\n", 641 status); 642 643 /* Try to recover */ 644 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); 645 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); 646 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); 647 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); 648 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); 649 } 650 651 tasklet_schedule(&dw->tasklet); 652 653 return IRQ_HANDLED; 654 } 655 656 /*----------------------------------------------------------------------*/ 657 658 static struct dma_async_tx_descriptor * 659 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 660 size_t len, unsigned long flags) 661 { 662 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 663 struct dw_dma *dw = to_dw_dma(chan->device); 664 struct dw_desc *desc; 665 struct dw_desc *first; 666 struct dw_desc *prev; 667 size_t xfer_count; 668 size_t offset; 669 u8 m_master = dwc->dws.m_master; 670 unsigned int src_width; 671 unsigned int dst_width; 672 unsigned int data_width = dw->pdata->data_width[m_master]; 673 u32 ctllo; 674 u8 lms = DWC_LLP_LMS(m_master); 675 676 dev_vdbg(chan2dev(chan), 677 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, 678 &dest, &src, len, flags); 679 680 if (unlikely(!len)) { 681 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); 682 return NULL; 683 } 684 685 dwc->direction = DMA_MEM_TO_MEM; 686 687 src_width = dst_width = __ffs(data_width | src | dest | len); 688 689 ctllo = DWC_DEFAULT_CTLLO(chan) 690 | DWC_CTLL_DST_WIDTH(dst_width) 691 | DWC_CTLL_SRC_WIDTH(src_width) 692 | DWC_CTLL_DST_INC 693 | DWC_CTLL_SRC_INC 694 | DWC_CTLL_FC_M2M; 695 prev = first = NULL; 696 697 for (offset = 0; offset < len; offset += xfer_count << src_width) { 698 xfer_count = min_t(size_t, (len - offset) >> src_width, 699 dwc->block_size); 700 701 desc = dwc_desc_get(dwc); 702 if (!desc) 703 goto err_desc_get; 704 705 lli_write(desc, sar, src + offset); 706 lli_write(desc, dar, dest + offset); 707 lli_write(desc, ctllo, ctllo); 708 lli_write(desc, ctlhi, xfer_count); 709 desc->len = xfer_count << src_width; 710 711 if (!first) { 712 first = desc; 713 } else { 714 lli_write(prev, llp, desc->txd.phys | lms); 715 list_add_tail(&desc->desc_node, &first->tx_list); 716 } 717 prev = desc; 718 } 719 720 if (flags & DMA_PREP_INTERRUPT) 721 /* Trigger interrupt after last block */ 722 lli_set(prev, ctllo, DWC_CTLL_INT_EN); 723 724 prev->lli.llp = 0; 725 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 726 first->txd.flags = flags; 727 first->total_len = len; 728 729 return &first->txd; 730 731 err_desc_get: 732 dwc_desc_put(dwc, first); 733 return NULL; 734 } 735 736 static struct dma_async_tx_descriptor * 737 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 738 unsigned int sg_len, enum dma_transfer_direction direction, 739 unsigned long flags, void *context) 740 { 741 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 742 struct dw_dma *dw = to_dw_dma(chan->device); 743 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 744 struct dw_desc *prev; 745 struct dw_desc *first; 746 u32 ctllo; 747 u8 m_master = dwc->dws.m_master; 748 u8 lms = DWC_LLP_LMS(m_master); 749 dma_addr_t reg; 750 unsigned int reg_width; 751 unsigned int mem_width; 752 unsigned int data_width = dw->pdata->data_width[m_master]; 753 unsigned int i; 754 struct scatterlist *sg; 755 size_t total_len = 0; 756 757 dev_vdbg(chan2dev(chan), "%s\n", __func__); 758 759 if (unlikely(!is_slave_direction(direction) || !sg_len)) 760 return NULL; 761 762 dwc->direction = direction; 763 764 prev = first = NULL; 765 766 switch (direction) { 767 case DMA_MEM_TO_DEV: 768 reg_width = __ffs(sconfig->dst_addr_width); 769 reg = sconfig->dst_addr; 770 ctllo = (DWC_DEFAULT_CTLLO(chan) 771 | DWC_CTLL_DST_WIDTH(reg_width) 772 | DWC_CTLL_DST_FIX 773 | DWC_CTLL_SRC_INC); 774 775 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 776 DWC_CTLL_FC(DW_DMA_FC_D_M2P); 777 778 for_each_sg(sgl, sg, sg_len, i) { 779 struct dw_desc *desc; 780 u32 len, dlen, mem; 781 782 mem = sg_dma_address(sg); 783 len = sg_dma_len(sg); 784 785 mem_width = __ffs(data_width | mem | len); 786 787 slave_sg_todev_fill_desc: 788 desc = dwc_desc_get(dwc); 789 if (!desc) 790 goto err_desc_get; 791 792 lli_write(desc, sar, mem); 793 lli_write(desc, dar, reg); 794 lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); 795 if ((len >> mem_width) > dwc->block_size) { 796 dlen = dwc->block_size << mem_width; 797 mem += dlen; 798 len -= dlen; 799 } else { 800 dlen = len; 801 len = 0; 802 } 803 804 lli_write(desc, ctlhi, dlen >> mem_width); 805 desc->len = dlen; 806 807 if (!first) { 808 first = desc; 809 } else { 810 lli_write(prev, llp, desc->txd.phys | lms); 811 list_add_tail(&desc->desc_node, &first->tx_list); 812 } 813 prev = desc; 814 total_len += dlen; 815 816 if (len) 817 goto slave_sg_todev_fill_desc; 818 } 819 break; 820 case DMA_DEV_TO_MEM: 821 reg_width = __ffs(sconfig->src_addr_width); 822 reg = sconfig->src_addr; 823 ctllo = (DWC_DEFAULT_CTLLO(chan) 824 | DWC_CTLL_SRC_WIDTH(reg_width) 825 | DWC_CTLL_DST_INC 826 | DWC_CTLL_SRC_FIX); 827 828 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 829 DWC_CTLL_FC(DW_DMA_FC_D_P2M); 830 831 for_each_sg(sgl, sg, sg_len, i) { 832 struct dw_desc *desc; 833 u32 len, dlen, mem; 834 835 mem = sg_dma_address(sg); 836 len = sg_dma_len(sg); 837 838 mem_width = __ffs(data_width | mem | len); 839 840 slave_sg_fromdev_fill_desc: 841 desc = dwc_desc_get(dwc); 842 if (!desc) 843 goto err_desc_get; 844 845 lli_write(desc, sar, reg); 846 lli_write(desc, dar, mem); 847 lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); 848 if ((len >> reg_width) > dwc->block_size) { 849 dlen = dwc->block_size << reg_width; 850 mem += dlen; 851 len -= dlen; 852 } else { 853 dlen = len; 854 len = 0; 855 } 856 lli_write(desc, ctlhi, dlen >> reg_width); 857 desc->len = dlen; 858 859 if (!first) { 860 first = desc; 861 } else { 862 lli_write(prev, llp, desc->txd.phys | lms); 863 list_add_tail(&desc->desc_node, &first->tx_list); 864 } 865 prev = desc; 866 total_len += dlen; 867 868 if (len) 869 goto slave_sg_fromdev_fill_desc; 870 } 871 break; 872 default: 873 return NULL; 874 } 875 876 if (flags & DMA_PREP_INTERRUPT) 877 /* Trigger interrupt after last block */ 878 lli_set(prev, ctllo, DWC_CTLL_INT_EN); 879 880 prev->lli.llp = 0; 881 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 882 first->total_len = total_len; 883 884 return &first->txd; 885 886 err_desc_get: 887 dev_err(chan2dev(chan), 888 "not enough descriptors available. Direction %d\n", direction); 889 dwc_desc_put(dwc, first); 890 return NULL; 891 } 892 893 bool dw_dma_filter(struct dma_chan *chan, void *param) 894 { 895 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 896 struct dw_dma_slave *dws = param; 897 898 if (dws->dma_dev != chan->device->dev) 899 return false; 900 901 /* We have to copy data since dws can be temporary storage */ 902 memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); 903 904 return true; 905 } 906 EXPORT_SYMBOL_GPL(dw_dma_filter); 907 908 /* 909 * Fix sconfig's burst size according to dw_dmac. We need to convert them as: 910 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. 911 * 912 * NOTE: burst size 2 is not supported by controller. 913 * 914 * This can be done by finding least significant bit set: n & (n - 1) 915 */ 916 static inline void convert_burst(u32 *maxburst) 917 { 918 if (*maxburst > 1) 919 *maxburst = fls(*maxburst) - 2; 920 else 921 *maxburst = 0; 922 } 923 924 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) 925 { 926 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 927 928 /* Check if chan will be configured for slave transfers */ 929 if (!is_slave_direction(sconfig->direction)) 930 return -EINVAL; 931 932 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); 933 dwc->direction = sconfig->direction; 934 935 convert_burst(&dwc->dma_sconfig.src_maxburst); 936 convert_burst(&dwc->dma_sconfig.dst_maxburst); 937 938 return 0; 939 } 940 941 static int dwc_pause(struct dma_chan *chan) 942 { 943 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 944 unsigned long flags; 945 unsigned int count = 20; /* timeout iterations */ 946 u32 cfglo; 947 948 spin_lock_irqsave(&dwc->lock, flags); 949 950 cfglo = channel_readl(dwc, CFG_LO); 951 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); 952 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) 953 udelay(2); 954 955 set_bit(DW_DMA_IS_PAUSED, &dwc->flags); 956 957 spin_unlock_irqrestore(&dwc->lock, flags); 958 959 return 0; 960 } 961 962 static inline void dwc_chan_resume(struct dw_dma_chan *dwc) 963 { 964 u32 cfglo = channel_readl(dwc, CFG_LO); 965 966 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); 967 968 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); 969 } 970 971 static int dwc_resume(struct dma_chan *chan) 972 { 973 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 974 unsigned long flags; 975 976 spin_lock_irqsave(&dwc->lock, flags); 977 978 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) 979 dwc_chan_resume(dwc); 980 981 spin_unlock_irqrestore(&dwc->lock, flags); 982 983 return 0; 984 } 985 986 static int dwc_terminate_all(struct dma_chan *chan) 987 { 988 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 989 struct dw_dma *dw = to_dw_dma(chan->device); 990 struct dw_desc *desc, *_desc; 991 unsigned long flags; 992 LIST_HEAD(list); 993 994 spin_lock_irqsave(&dwc->lock, flags); 995 996 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 997 998 dwc_chan_disable(dw, dwc); 999 1000 dwc_chan_resume(dwc); 1001 1002 /* active_list entries will end up before queued entries */ 1003 list_splice_init(&dwc->queue, &list); 1004 list_splice_init(&dwc->active_list, &list); 1005 1006 spin_unlock_irqrestore(&dwc->lock, flags); 1007 1008 /* Flush all pending and queued descriptors */ 1009 list_for_each_entry_safe(desc, _desc, &list, desc_node) 1010 dwc_descriptor_complete(dwc, desc, false); 1011 1012 return 0; 1013 } 1014 1015 static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c) 1016 { 1017 struct dw_desc *desc; 1018 1019 list_for_each_entry(desc, &dwc->active_list, desc_node) 1020 if (desc->txd.cookie == c) 1021 return desc; 1022 1023 return NULL; 1024 } 1025 1026 static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie) 1027 { 1028 struct dw_desc *desc; 1029 unsigned long flags; 1030 u32 residue; 1031 1032 spin_lock_irqsave(&dwc->lock, flags); 1033 1034 desc = dwc_find_desc(dwc, cookie); 1035 if (desc) { 1036 if (desc == dwc_first_active(dwc)) { 1037 residue = desc->residue; 1038 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) 1039 residue -= dwc_get_sent(dwc); 1040 } else { 1041 residue = desc->total_len; 1042 } 1043 } else { 1044 residue = 0; 1045 } 1046 1047 spin_unlock_irqrestore(&dwc->lock, flags); 1048 return residue; 1049 } 1050 1051 static enum dma_status 1052 dwc_tx_status(struct dma_chan *chan, 1053 dma_cookie_t cookie, 1054 struct dma_tx_state *txstate) 1055 { 1056 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1057 enum dma_status ret; 1058 1059 ret = dma_cookie_status(chan, cookie, txstate); 1060 if (ret == DMA_COMPLETE) 1061 return ret; 1062 1063 dwc_scan_descriptors(to_dw_dma(chan->device), dwc); 1064 1065 ret = dma_cookie_status(chan, cookie, txstate); 1066 if (ret == DMA_COMPLETE) 1067 return ret; 1068 1069 dma_set_residue(txstate, dwc_get_residue(dwc, cookie)); 1070 1071 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) 1072 return DMA_PAUSED; 1073 1074 return ret; 1075 } 1076 1077 static void dwc_issue_pending(struct dma_chan *chan) 1078 { 1079 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1080 unsigned long flags; 1081 1082 spin_lock_irqsave(&dwc->lock, flags); 1083 if (list_empty(&dwc->active_list)) 1084 dwc_dostart_first_queued(dwc); 1085 spin_unlock_irqrestore(&dwc->lock, flags); 1086 } 1087 1088 /*----------------------------------------------------------------------*/ 1089 1090 static void dw_dma_off(struct dw_dma *dw) 1091 { 1092 unsigned int i; 1093 1094 dma_writel(dw, CFG, 0); 1095 1096 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 1097 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 1098 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); 1099 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); 1100 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 1101 1102 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) 1103 cpu_relax(); 1104 1105 for (i = 0; i < dw->dma.chancnt; i++) 1106 clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags); 1107 } 1108 1109 static void dw_dma_on(struct dw_dma *dw) 1110 { 1111 dma_writel(dw, CFG, DW_CFG_DMA_EN); 1112 } 1113 1114 static int dwc_alloc_chan_resources(struct dma_chan *chan) 1115 { 1116 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1117 struct dw_dma *dw = to_dw_dma(chan->device); 1118 1119 dev_vdbg(chan2dev(chan), "%s\n", __func__); 1120 1121 /* ASSERT: channel is idle */ 1122 if (dma_readl(dw, CH_EN) & dwc->mask) { 1123 dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); 1124 return -EIO; 1125 } 1126 1127 dma_cookie_init(chan); 1128 1129 /* 1130 * NOTE: some controllers may have additional features that we 1131 * need to initialize here, like "scatter-gather" (which 1132 * doesn't mean what you think it means), and status writeback. 1133 */ 1134 1135 /* 1136 * We need controller-specific data to set up slave transfers. 1137 */ 1138 if (chan->private && !dw_dma_filter(chan, chan->private)) { 1139 dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); 1140 return -EINVAL; 1141 } 1142 1143 /* Enable controller here if needed */ 1144 if (!dw->in_use) 1145 dw_dma_on(dw); 1146 dw->in_use |= dwc->mask; 1147 1148 return 0; 1149 } 1150 1151 static void dwc_free_chan_resources(struct dma_chan *chan) 1152 { 1153 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1154 struct dw_dma *dw = to_dw_dma(chan->device); 1155 unsigned long flags; 1156 LIST_HEAD(list); 1157 1158 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, 1159 dwc->descs_allocated); 1160 1161 /* ASSERT: channel is idle */ 1162 BUG_ON(!list_empty(&dwc->active_list)); 1163 BUG_ON(!list_empty(&dwc->queue)); 1164 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); 1165 1166 spin_lock_irqsave(&dwc->lock, flags); 1167 1168 /* Clear custom channel configuration */ 1169 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); 1170 1171 clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); 1172 1173 /* Disable interrupts */ 1174 channel_clear_bit(dw, MASK.XFER, dwc->mask); 1175 channel_clear_bit(dw, MASK.BLOCK, dwc->mask); 1176 channel_clear_bit(dw, MASK.ERROR, dwc->mask); 1177 1178 spin_unlock_irqrestore(&dwc->lock, flags); 1179 1180 /* Disable controller in case it was a last user */ 1181 dw->in_use &= ~dwc->mask; 1182 if (!dw->in_use) 1183 dw_dma_off(dw); 1184 1185 dev_vdbg(chan2dev(chan), "%s: done\n", __func__); 1186 } 1187 1188 /* --------------------- Cyclic DMA API extensions -------------------- */ 1189 1190 /** 1191 * dw_dma_cyclic_start - start the cyclic DMA transfer 1192 * @chan: the DMA channel to start 1193 * 1194 * Must be called with soft interrupts disabled. Returns zero on success or 1195 * -errno on failure. 1196 */ 1197 int dw_dma_cyclic_start(struct dma_chan *chan) 1198 { 1199 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1200 struct dw_dma *dw = to_dw_dma(chan->device); 1201 unsigned long flags; 1202 1203 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { 1204 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); 1205 return -ENODEV; 1206 } 1207 1208 spin_lock_irqsave(&dwc->lock, flags); 1209 1210 /* Enable interrupts to perform cyclic transfer */ 1211 channel_set_bit(dw, MASK.BLOCK, dwc->mask); 1212 1213 dwc_dostart(dwc, dwc->cdesc->desc[0]); 1214 1215 spin_unlock_irqrestore(&dwc->lock, flags); 1216 1217 return 0; 1218 } 1219 EXPORT_SYMBOL(dw_dma_cyclic_start); 1220 1221 /** 1222 * dw_dma_cyclic_stop - stop the cyclic DMA transfer 1223 * @chan: the DMA channel to stop 1224 * 1225 * Must be called with soft interrupts disabled. 1226 */ 1227 void dw_dma_cyclic_stop(struct dma_chan *chan) 1228 { 1229 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1230 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1231 unsigned long flags; 1232 1233 spin_lock_irqsave(&dwc->lock, flags); 1234 1235 dwc_chan_disable(dw, dwc); 1236 1237 spin_unlock_irqrestore(&dwc->lock, flags); 1238 } 1239 EXPORT_SYMBOL(dw_dma_cyclic_stop); 1240 1241 /** 1242 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer 1243 * @chan: the DMA channel to prepare 1244 * @buf_addr: physical DMA address where the buffer starts 1245 * @buf_len: total number of bytes for the entire buffer 1246 * @period_len: number of bytes for each period 1247 * @direction: transfer direction, to or from device 1248 * 1249 * Must be called before trying to start the transfer. Returns a valid struct 1250 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. 1251 */ 1252 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 1253 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 1254 enum dma_transfer_direction direction) 1255 { 1256 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1257 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 1258 struct dw_cyclic_desc *cdesc; 1259 struct dw_cyclic_desc *retval = NULL; 1260 struct dw_desc *desc; 1261 struct dw_desc *last = NULL; 1262 u8 lms = DWC_LLP_LMS(dwc->dws.m_master); 1263 unsigned long was_cyclic; 1264 unsigned int reg_width; 1265 unsigned int periods; 1266 unsigned int i; 1267 unsigned long flags; 1268 1269 spin_lock_irqsave(&dwc->lock, flags); 1270 if (dwc->nollp) { 1271 spin_unlock_irqrestore(&dwc->lock, flags); 1272 dev_dbg(chan2dev(&dwc->chan), 1273 "channel doesn't support LLP transfers\n"); 1274 return ERR_PTR(-EINVAL); 1275 } 1276 1277 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { 1278 spin_unlock_irqrestore(&dwc->lock, flags); 1279 dev_dbg(chan2dev(&dwc->chan), 1280 "queue and/or active list are not empty\n"); 1281 return ERR_PTR(-EBUSY); 1282 } 1283 1284 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1285 spin_unlock_irqrestore(&dwc->lock, flags); 1286 if (was_cyclic) { 1287 dev_dbg(chan2dev(&dwc->chan), 1288 "channel already prepared for cyclic DMA\n"); 1289 return ERR_PTR(-EBUSY); 1290 } 1291 1292 retval = ERR_PTR(-EINVAL); 1293 1294 if (unlikely(!is_slave_direction(direction))) 1295 goto out_err; 1296 1297 dwc->direction = direction; 1298 1299 if (direction == DMA_MEM_TO_DEV) 1300 reg_width = __ffs(sconfig->dst_addr_width); 1301 else 1302 reg_width = __ffs(sconfig->src_addr_width); 1303 1304 periods = buf_len / period_len; 1305 1306 /* Check for too big/unaligned periods and unaligned DMA buffer. */ 1307 if (period_len > (dwc->block_size << reg_width)) 1308 goto out_err; 1309 if (unlikely(period_len & ((1 << reg_width) - 1))) 1310 goto out_err; 1311 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 1312 goto out_err; 1313 1314 retval = ERR_PTR(-ENOMEM); 1315 1316 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); 1317 if (!cdesc) 1318 goto out_err; 1319 1320 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); 1321 if (!cdesc->desc) 1322 goto out_err_alloc; 1323 1324 for (i = 0; i < periods; i++) { 1325 desc = dwc_desc_get(dwc); 1326 if (!desc) 1327 goto out_err_desc_get; 1328 1329 switch (direction) { 1330 case DMA_MEM_TO_DEV: 1331 lli_write(desc, dar, sconfig->dst_addr); 1332 lli_write(desc, sar, buf_addr + period_len * i); 1333 lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan) 1334 | DWC_CTLL_DST_WIDTH(reg_width) 1335 | DWC_CTLL_SRC_WIDTH(reg_width) 1336 | DWC_CTLL_DST_FIX 1337 | DWC_CTLL_SRC_INC 1338 | DWC_CTLL_INT_EN)); 1339 1340 lli_set(desc, ctllo, sconfig->device_fc ? 1341 DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 1342 DWC_CTLL_FC(DW_DMA_FC_D_M2P)); 1343 1344 break; 1345 case DMA_DEV_TO_MEM: 1346 lli_write(desc, dar, buf_addr + period_len * i); 1347 lli_write(desc, sar, sconfig->src_addr); 1348 lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan) 1349 | DWC_CTLL_SRC_WIDTH(reg_width) 1350 | DWC_CTLL_DST_WIDTH(reg_width) 1351 | DWC_CTLL_DST_INC 1352 | DWC_CTLL_SRC_FIX 1353 | DWC_CTLL_INT_EN)); 1354 1355 lli_set(desc, ctllo, sconfig->device_fc ? 1356 DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 1357 DWC_CTLL_FC(DW_DMA_FC_D_P2M)); 1358 1359 break; 1360 default: 1361 break; 1362 } 1363 1364 lli_write(desc, ctlhi, period_len >> reg_width); 1365 cdesc->desc[i] = desc; 1366 1367 if (last) 1368 lli_write(last, llp, desc->txd.phys | lms); 1369 1370 last = desc; 1371 } 1372 1373 /* Let's make a cyclic list */ 1374 lli_write(last, llp, cdesc->desc[0]->txd.phys | lms); 1375 1376 dev_dbg(chan2dev(&dwc->chan), 1377 "cyclic prepared buf %pad len %zu period %zu periods %d\n", 1378 &buf_addr, buf_len, period_len, periods); 1379 1380 cdesc->periods = periods; 1381 dwc->cdesc = cdesc; 1382 1383 return cdesc; 1384 1385 out_err_desc_get: 1386 while (i--) 1387 dwc_desc_put(dwc, cdesc->desc[i]); 1388 out_err_alloc: 1389 kfree(cdesc); 1390 out_err: 1391 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1392 return (struct dw_cyclic_desc *)retval; 1393 } 1394 EXPORT_SYMBOL(dw_dma_cyclic_prep); 1395 1396 /** 1397 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer 1398 * @chan: the DMA channel to free 1399 */ 1400 void dw_dma_cyclic_free(struct dma_chan *chan) 1401 { 1402 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1403 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1404 struct dw_cyclic_desc *cdesc = dwc->cdesc; 1405 unsigned int i; 1406 unsigned long flags; 1407 1408 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); 1409 1410 if (!cdesc) 1411 return; 1412 1413 spin_lock_irqsave(&dwc->lock, flags); 1414 1415 dwc_chan_disable(dw, dwc); 1416 1417 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 1418 dma_writel(dw, CLEAR.ERROR, dwc->mask); 1419 dma_writel(dw, CLEAR.XFER, dwc->mask); 1420 1421 spin_unlock_irqrestore(&dwc->lock, flags); 1422 1423 for (i = 0; i < cdesc->periods; i++) 1424 dwc_desc_put(dwc, cdesc->desc[i]); 1425 1426 kfree(cdesc->desc); 1427 kfree(cdesc); 1428 1429 dwc->cdesc = NULL; 1430 1431 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1432 } 1433 EXPORT_SYMBOL(dw_dma_cyclic_free); 1434 1435 /*----------------------------------------------------------------------*/ 1436 1437 int dw_dma_probe(struct dw_dma_chip *chip) 1438 { 1439 struct dw_dma_platform_data *pdata; 1440 struct dw_dma *dw; 1441 bool autocfg = false; 1442 unsigned int dw_params; 1443 unsigned int i; 1444 int err; 1445 1446 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); 1447 if (!dw) 1448 return -ENOMEM; 1449 1450 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); 1451 if (!dw->pdata) 1452 return -ENOMEM; 1453 1454 dw->regs = chip->regs; 1455 chip->dw = dw; 1456 1457 pm_runtime_get_sync(chip->dev); 1458 1459 if (!chip->pdata) { 1460 dw_params = dma_readl(dw, DW_PARAMS); 1461 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); 1462 1463 autocfg = dw_params >> DW_PARAMS_EN & 1; 1464 if (!autocfg) { 1465 err = -EINVAL; 1466 goto err_pdata; 1467 } 1468 1469 /* Reassign the platform data pointer */ 1470 pdata = dw->pdata; 1471 1472 /* Get hardware configuration parameters */ 1473 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; 1474 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; 1475 for (i = 0; i < pdata->nr_masters; i++) { 1476 pdata->data_width[i] = 1477 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3); 1478 } 1479 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); 1480 1481 /* Fill platform data with the default values */ 1482 pdata->is_private = true; 1483 pdata->is_memcpy = true; 1484 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; 1485 pdata->chan_priority = CHAN_PRIORITY_ASCENDING; 1486 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { 1487 err = -EINVAL; 1488 goto err_pdata; 1489 } else { 1490 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); 1491 1492 /* Reassign the platform data pointer */ 1493 pdata = dw->pdata; 1494 } 1495 1496 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), 1497 GFP_KERNEL); 1498 if (!dw->chan) { 1499 err = -ENOMEM; 1500 goto err_pdata; 1501 } 1502 1503 /* Calculate all channel mask before DMA setup */ 1504 dw->all_chan_mask = (1 << pdata->nr_channels) - 1; 1505 1506 /* Force dma off, just in case */ 1507 dw_dma_off(dw); 1508 1509 /* Create a pool of consistent memory blocks for hardware descriptors */ 1510 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, 1511 sizeof(struct dw_desc), 4, 0); 1512 if (!dw->desc_pool) { 1513 dev_err(chip->dev, "No memory for descriptors dma pool\n"); 1514 err = -ENOMEM; 1515 goto err_pdata; 1516 } 1517 1518 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); 1519 1520 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, 1521 "dw_dmac", dw); 1522 if (err) 1523 goto err_pdata; 1524 1525 INIT_LIST_HEAD(&dw->dma.channels); 1526 for (i = 0; i < pdata->nr_channels; i++) { 1527 struct dw_dma_chan *dwc = &dw->chan[i]; 1528 1529 dwc->chan.device = &dw->dma; 1530 dma_cookie_init(&dwc->chan); 1531 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) 1532 list_add_tail(&dwc->chan.device_node, 1533 &dw->dma.channels); 1534 else 1535 list_add(&dwc->chan.device_node, &dw->dma.channels); 1536 1537 /* 7 is highest priority & 0 is lowest. */ 1538 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) 1539 dwc->priority = pdata->nr_channels - i - 1; 1540 else 1541 dwc->priority = i; 1542 1543 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; 1544 spin_lock_init(&dwc->lock); 1545 dwc->mask = 1 << i; 1546 1547 INIT_LIST_HEAD(&dwc->active_list); 1548 INIT_LIST_HEAD(&dwc->queue); 1549 1550 channel_clear_bit(dw, CH_EN, dwc->mask); 1551 1552 dwc->direction = DMA_TRANS_NONE; 1553 1554 /* Hardware configuration */ 1555 if (autocfg) { 1556 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; 1557 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; 1558 unsigned int dwc_params = dma_readl_native(addr); 1559 1560 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, 1561 dwc_params); 1562 1563 /* 1564 * Decode maximum block size for given channel. The 1565 * stored 4 bit value represents blocks from 0x00 for 3 1566 * up to 0x0a for 4095. 1567 */ 1568 dwc->block_size = 1569 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; 1570 dwc->nollp = 1571 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; 1572 } else { 1573 dwc->block_size = pdata->block_size; 1574 dwc->nollp = pdata->is_nollp; 1575 } 1576 } 1577 1578 /* Clear all interrupts on all channels. */ 1579 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); 1580 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); 1581 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); 1582 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); 1583 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); 1584 1585 /* Set capabilities */ 1586 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); 1587 if (pdata->is_private) 1588 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); 1589 if (pdata->is_memcpy) 1590 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 1591 1592 dw->dma.dev = chip->dev; 1593 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; 1594 dw->dma.device_free_chan_resources = dwc_free_chan_resources; 1595 1596 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; 1597 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; 1598 1599 dw->dma.device_config = dwc_config; 1600 dw->dma.device_pause = dwc_pause; 1601 dw->dma.device_resume = dwc_resume; 1602 dw->dma.device_terminate_all = dwc_terminate_all; 1603 1604 dw->dma.device_tx_status = dwc_tx_status; 1605 dw->dma.device_issue_pending = dwc_issue_pending; 1606 1607 /* DMA capabilities */ 1608 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; 1609 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; 1610 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | 1611 BIT(DMA_MEM_TO_MEM); 1612 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1613 1614 err = dma_async_device_register(&dw->dma); 1615 if (err) 1616 goto err_dma_register; 1617 1618 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", 1619 pdata->nr_channels); 1620 1621 pm_runtime_put_sync_suspend(chip->dev); 1622 1623 return 0; 1624 1625 err_dma_register: 1626 free_irq(chip->irq, dw); 1627 err_pdata: 1628 pm_runtime_put_sync_suspend(chip->dev); 1629 return err; 1630 } 1631 EXPORT_SYMBOL_GPL(dw_dma_probe); 1632 1633 int dw_dma_remove(struct dw_dma_chip *chip) 1634 { 1635 struct dw_dma *dw = chip->dw; 1636 struct dw_dma_chan *dwc, *_dwc; 1637 1638 pm_runtime_get_sync(chip->dev); 1639 1640 dw_dma_off(dw); 1641 dma_async_device_unregister(&dw->dma); 1642 1643 free_irq(chip->irq, dw); 1644 tasklet_kill(&dw->tasklet); 1645 1646 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, 1647 chan.device_node) { 1648 list_del(&dwc->chan.device_node); 1649 channel_clear_bit(dw, CH_EN, dwc->mask); 1650 } 1651 1652 pm_runtime_put_sync_suspend(chip->dev); 1653 return 0; 1654 } 1655 EXPORT_SYMBOL_GPL(dw_dma_remove); 1656 1657 int dw_dma_disable(struct dw_dma_chip *chip) 1658 { 1659 struct dw_dma *dw = chip->dw; 1660 1661 dw_dma_off(dw); 1662 return 0; 1663 } 1664 EXPORT_SYMBOL_GPL(dw_dma_disable); 1665 1666 int dw_dma_enable(struct dw_dma_chip *chip) 1667 { 1668 struct dw_dma *dw = chip->dw; 1669 1670 dw_dma_on(dw); 1671 return 0; 1672 } 1673 EXPORT_SYMBOL_GPL(dw_dma_enable); 1674 1675 MODULE_LICENSE("GPL v2"); 1676 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); 1677 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1678 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); 1679