1 /* 2 * Core driver for the Synopsys DesignWare DMA Controller 3 * 4 * Copyright (C) 2007-2008 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * Copyright (C) 2013 Intel Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/dmapool.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/mm.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/pm_runtime.h> 26 27 #include "../dmaengine.h" 28 #include "internal.h" 29 30 /* 31 * This supports the Synopsys "DesignWare AHB Central DMA Controller", 32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all 33 * of which use ARM any more). See the "Databook" from Synopsys for 34 * information beyond what licensees probably provide. 35 * 36 * The driver has been tested with the Atmel AT32AP7000, which does not 37 * support descriptor writeback. 38 */ 39 40 #define DWC_DEFAULT_CTLLO(_chan) ({ \ 41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ 42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ 43 bool _is_slave = is_slave_direction(_dwc->direction); \ 44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ 45 DW_DMA_MSIZE_16; \ 46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ 47 DW_DMA_MSIZE_16; \ 48 \ 49 (DWC_CTLL_DST_MSIZE(_dmsize) \ 50 | DWC_CTLL_SRC_MSIZE(_smsize) \ 51 | DWC_CTLL_LLP_D_EN \ 52 | DWC_CTLL_LLP_S_EN \ 53 | DWC_CTLL_DMS(_dwc->dst_master) \ 54 | DWC_CTLL_SMS(_dwc->src_master)); \ 55 }) 56 57 /* 58 * Number of descriptors to allocate for each channel. This should be 59 * made configurable somehow; preferably, the clients (at least the 60 * ones using slave transfers) should be able to give us a hint. 61 */ 62 #define NR_DESCS_PER_CHANNEL 64 63 64 /* The set of bus widths supported by the DMA controller */ 65 #define DW_DMA_BUSWIDTHS \ 66 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 67 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 68 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 69 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) 70 71 /*----------------------------------------------------------------------*/ 72 73 static struct device *chan2dev(struct dma_chan *chan) 74 { 75 return &chan->dev->device; 76 } 77 78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) 79 { 80 return to_dw_desc(dwc->active_list.next); 81 } 82 83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) 84 { 85 struct dw_desc *desc, *_desc; 86 struct dw_desc *ret = NULL; 87 unsigned int i = 0; 88 unsigned long flags; 89 90 spin_lock_irqsave(&dwc->lock, flags); 91 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { 92 i++; 93 if (async_tx_test_ack(&desc->txd)) { 94 list_del(&desc->desc_node); 95 ret = desc; 96 break; 97 } 98 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); 99 } 100 spin_unlock_irqrestore(&dwc->lock, flags); 101 102 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); 103 104 return ret; 105 } 106 107 /* 108 * Move a descriptor, including any children, to the free list. 109 * `desc' must not be on any lists. 110 */ 111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) 112 { 113 unsigned long flags; 114 115 if (desc) { 116 struct dw_desc *child; 117 118 spin_lock_irqsave(&dwc->lock, flags); 119 list_for_each_entry(child, &desc->tx_list, desc_node) 120 dev_vdbg(chan2dev(&dwc->chan), 121 "moving child desc %p to freelist\n", 122 child); 123 list_splice_init(&desc->tx_list, &dwc->free_list); 124 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); 125 list_add(&desc->desc_node, &dwc->free_list); 126 spin_unlock_irqrestore(&dwc->lock, flags); 127 } 128 } 129 130 static void dwc_initialize(struct dw_dma_chan *dwc) 131 { 132 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 133 u32 cfghi = DWC_CFGH_FIFO_MODE; 134 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); 135 136 if (dwc->initialized == true) 137 return; 138 139 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); 140 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); 141 142 channel_writel(dwc, CFG_LO, cfglo); 143 channel_writel(dwc, CFG_HI, cfghi); 144 145 /* Enable interrupts */ 146 channel_set_bit(dw, MASK.XFER, dwc->mask); 147 channel_set_bit(dw, MASK.ERROR, dwc->mask); 148 149 dwc->initialized = true; 150 } 151 152 /*----------------------------------------------------------------------*/ 153 154 static inline unsigned int dwc_fast_ffs(unsigned long long v) 155 { 156 /* 157 * We can be a lot more clever here, but this should take care 158 * of the most common optimization. 159 */ 160 if (!(v & 7)) 161 return 3; 162 else if (!(v & 3)) 163 return 2; 164 else if (!(v & 1)) 165 return 1; 166 return 0; 167 } 168 169 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) 170 { 171 dev_err(chan2dev(&dwc->chan), 172 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", 173 channel_readl(dwc, SAR), 174 channel_readl(dwc, DAR), 175 channel_readl(dwc, LLP), 176 channel_readl(dwc, CTL_HI), 177 channel_readl(dwc, CTL_LO)); 178 } 179 180 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) 181 { 182 channel_clear_bit(dw, CH_EN, dwc->mask); 183 while (dma_readl(dw, CH_EN) & dwc->mask) 184 cpu_relax(); 185 } 186 187 /*----------------------------------------------------------------------*/ 188 189 /* Perform single block transfer */ 190 static inline void dwc_do_single_block(struct dw_dma_chan *dwc, 191 struct dw_desc *desc) 192 { 193 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 194 u32 ctllo; 195 196 /* 197 * Software emulation of LLP mode relies on interrupts to continue 198 * multi block transfer. 199 */ 200 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; 201 202 channel_writel(dwc, SAR, desc->lli.sar); 203 channel_writel(dwc, DAR, desc->lli.dar); 204 channel_writel(dwc, CTL_LO, ctllo); 205 channel_writel(dwc, CTL_HI, desc->lli.ctlhi); 206 channel_set_bit(dw, CH_EN, dwc->mask); 207 208 /* Move pointer to next descriptor */ 209 dwc->tx_node_active = dwc->tx_node_active->next; 210 } 211 212 /* Called with dwc->lock held and bh disabled */ 213 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) 214 { 215 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 216 unsigned long was_soft_llp; 217 218 /* ASSERT: channel is idle */ 219 if (dma_readl(dw, CH_EN) & dwc->mask) { 220 dev_err(chan2dev(&dwc->chan), 221 "%s: BUG: Attempted to start non-idle channel\n", 222 __func__); 223 dwc_dump_chan_regs(dwc); 224 225 /* The tasklet will hopefully advance the queue... */ 226 return; 227 } 228 229 if (dwc->nollp) { 230 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, 231 &dwc->flags); 232 if (was_soft_llp) { 233 dev_err(chan2dev(&dwc->chan), 234 "BUG: Attempted to start new LLP transfer inside ongoing one\n"); 235 return; 236 } 237 238 dwc_initialize(dwc); 239 240 dwc->residue = first->total_len; 241 dwc->tx_node_active = &first->tx_list; 242 243 /* Submit first block */ 244 dwc_do_single_block(dwc, first); 245 246 return; 247 } 248 249 dwc_initialize(dwc); 250 251 channel_writel(dwc, LLP, first->txd.phys); 252 channel_writel(dwc, CTL_LO, 253 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 254 channel_writel(dwc, CTL_HI, 0); 255 channel_set_bit(dw, CH_EN, dwc->mask); 256 } 257 258 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) 259 { 260 struct dw_desc *desc; 261 262 if (list_empty(&dwc->queue)) 263 return; 264 265 list_move(dwc->queue.next, &dwc->active_list); 266 desc = dwc_first_active(dwc); 267 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); 268 dwc_dostart(dwc, desc); 269 } 270 271 /*----------------------------------------------------------------------*/ 272 273 static void 274 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, 275 bool callback_required) 276 { 277 dma_async_tx_callback callback = NULL; 278 void *param = NULL; 279 struct dma_async_tx_descriptor *txd = &desc->txd; 280 struct dw_desc *child; 281 unsigned long flags; 282 283 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); 284 285 spin_lock_irqsave(&dwc->lock, flags); 286 dma_cookie_complete(txd); 287 if (callback_required) { 288 callback = txd->callback; 289 param = txd->callback_param; 290 } 291 292 /* async_tx_ack */ 293 list_for_each_entry(child, &desc->tx_list, desc_node) 294 async_tx_ack(&child->txd); 295 async_tx_ack(&desc->txd); 296 297 list_splice_init(&desc->tx_list, &dwc->free_list); 298 list_move(&desc->desc_node, &dwc->free_list); 299 300 dma_descriptor_unmap(txd); 301 spin_unlock_irqrestore(&dwc->lock, flags); 302 303 if (callback) 304 callback(param); 305 } 306 307 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) 308 { 309 struct dw_desc *desc, *_desc; 310 LIST_HEAD(list); 311 unsigned long flags; 312 313 spin_lock_irqsave(&dwc->lock, flags); 314 if (dma_readl(dw, CH_EN) & dwc->mask) { 315 dev_err(chan2dev(&dwc->chan), 316 "BUG: XFER bit set, but channel not idle!\n"); 317 318 /* Try to continue after resetting the channel... */ 319 dwc_chan_disable(dw, dwc); 320 } 321 322 /* 323 * Submit queued descriptors ASAP, i.e. before we go through 324 * the completed ones. 325 */ 326 list_splice_init(&dwc->active_list, &list); 327 dwc_dostart_first_queued(dwc); 328 329 spin_unlock_irqrestore(&dwc->lock, flags); 330 331 list_for_each_entry_safe(desc, _desc, &list, desc_node) 332 dwc_descriptor_complete(dwc, desc, true); 333 } 334 335 /* Returns how many bytes were already received from source */ 336 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) 337 { 338 u32 ctlhi = channel_readl(dwc, CTL_HI); 339 u32 ctllo = channel_readl(dwc, CTL_LO); 340 341 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); 342 } 343 344 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) 345 { 346 dma_addr_t llp; 347 struct dw_desc *desc, *_desc; 348 struct dw_desc *child; 349 u32 status_xfer; 350 unsigned long flags; 351 352 spin_lock_irqsave(&dwc->lock, flags); 353 llp = channel_readl(dwc, LLP); 354 status_xfer = dma_readl(dw, RAW.XFER); 355 356 if (status_xfer & dwc->mask) { 357 /* Everything we've submitted is done */ 358 dma_writel(dw, CLEAR.XFER, dwc->mask); 359 360 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 361 struct list_head *head, *active = dwc->tx_node_active; 362 363 /* 364 * We are inside first active descriptor. 365 * Otherwise something is really wrong. 366 */ 367 desc = dwc_first_active(dwc); 368 369 head = &desc->tx_list; 370 if (active != head) { 371 /* Update desc to reflect last sent one */ 372 if (active != head->next) 373 desc = to_dw_desc(active->prev); 374 375 dwc->residue -= desc->len; 376 377 child = to_dw_desc(active); 378 379 /* Submit next block */ 380 dwc_do_single_block(dwc, child); 381 382 spin_unlock_irqrestore(&dwc->lock, flags); 383 return; 384 } 385 386 /* We are done here */ 387 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 388 } 389 390 dwc->residue = 0; 391 392 spin_unlock_irqrestore(&dwc->lock, flags); 393 394 dwc_complete_all(dw, dwc); 395 return; 396 } 397 398 if (list_empty(&dwc->active_list)) { 399 dwc->residue = 0; 400 spin_unlock_irqrestore(&dwc->lock, flags); 401 return; 402 } 403 404 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 405 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); 406 spin_unlock_irqrestore(&dwc->lock, flags); 407 return; 408 } 409 410 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); 411 412 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { 413 /* Initial residue value */ 414 dwc->residue = desc->total_len; 415 416 /* Check first descriptors addr */ 417 if (desc->txd.phys == llp) { 418 spin_unlock_irqrestore(&dwc->lock, flags); 419 return; 420 } 421 422 /* Check first descriptors llp */ 423 if (desc->lli.llp == llp) { 424 /* This one is currently in progress */ 425 dwc->residue -= dwc_get_sent(dwc); 426 spin_unlock_irqrestore(&dwc->lock, flags); 427 return; 428 } 429 430 dwc->residue -= desc->len; 431 list_for_each_entry(child, &desc->tx_list, desc_node) { 432 if (child->lli.llp == llp) { 433 /* Currently in progress */ 434 dwc->residue -= dwc_get_sent(dwc); 435 spin_unlock_irqrestore(&dwc->lock, flags); 436 return; 437 } 438 dwc->residue -= child->len; 439 } 440 441 /* 442 * No descriptors so far seem to be in progress, i.e. 443 * this one must be done. 444 */ 445 spin_unlock_irqrestore(&dwc->lock, flags); 446 dwc_descriptor_complete(dwc, desc, true); 447 spin_lock_irqsave(&dwc->lock, flags); 448 } 449 450 dev_err(chan2dev(&dwc->chan), 451 "BUG: All descriptors done, but channel not idle!\n"); 452 453 /* Try to continue after resetting the channel... */ 454 dwc_chan_disable(dw, dwc); 455 456 dwc_dostart_first_queued(dwc); 457 spin_unlock_irqrestore(&dwc->lock, flags); 458 } 459 460 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) 461 { 462 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", 463 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); 464 } 465 466 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) 467 { 468 struct dw_desc *bad_desc; 469 struct dw_desc *child; 470 unsigned long flags; 471 472 dwc_scan_descriptors(dw, dwc); 473 474 spin_lock_irqsave(&dwc->lock, flags); 475 476 /* 477 * The descriptor currently at the head of the active list is 478 * borked. Since we don't have any way to report errors, we'll 479 * just have to scream loudly and try to carry on. 480 */ 481 bad_desc = dwc_first_active(dwc); 482 list_del_init(&bad_desc->desc_node); 483 list_move(dwc->queue.next, dwc->active_list.prev); 484 485 /* Clear the error flag and try to restart the controller */ 486 dma_writel(dw, CLEAR.ERROR, dwc->mask); 487 if (!list_empty(&dwc->active_list)) 488 dwc_dostart(dwc, dwc_first_active(dwc)); 489 490 /* 491 * WARN may seem harsh, but since this only happens 492 * when someone submits a bad physical address in a 493 * descriptor, we should consider ourselves lucky that the 494 * controller flagged an error instead of scribbling over 495 * random memory locations. 496 */ 497 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" 498 " cookie: %d\n", bad_desc->txd.cookie); 499 dwc_dump_lli(dwc, &bad_desc->lli); 500 list_for_each_entry(child, &bad_desc->tx_list, desc_node) 501 dwc_dump_lli(dwc, &child->lli); 502 503 spin_unlock_irqrestore(&dwc->lock, flags); 504 505 /* Pretend the descriptor completed successfully */ 506 dwc_descriptor_complete(dwc, bad_desc, true); 507 } 508 509 /* --------------------- Cyclic DMA API extensions -------------------- */ 510 511 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) 512 { 513 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 514 return channel_readl(dwc, SAR); 515 } 516 EXPORT_SYMBOL(dw_dma_get_src_addr); 517 518 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) 519 { 520 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 521 return channel_readl(dwc, DAR); 522 } 523 EXPORT_SYMBOL(dw_dma_get_dst_addr); 524 525 /* Called with dwc->lock held and all DMAC interrupts disabled */ 526 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, 527 u32 status_block, u32 status_err, u32 status_xfer) 528 { 529 unsigned long flags; 530 531 if (status_block & dwc->mask) { 532 void (*callback)(void *param); 533 void *callback_param; 534 535 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", 536 channel_readl(dwc, LLP)); 537 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 538 539 callback = dwc->cdesc->period_callback; 540 callback_param = dwc->cdesc->period_callback_param; 541 542 if (callback) 543 callback(callback_param); 544 } 545 546 /* 547 * Error and transfer complete are highly unlikely, and will most 548 * likely be due to a configuration error by the user. 549 */ 550 if (unlikely(status_err & dwc->mask) || 551 unlikely(status_xfer & dwc->mask)) { 552 int i; 553 554 dev_err(chan2dev(&dwc->chan), 555 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", 556 status_xfer ? "xfer" : "error"); 557 558 spin_lock_irqsave(&dwc->lock, flags); 559 560 dwc_dump_chan_regs(dwc); 561 562 dwc_chan_disable(dw, dwc); 563 564 /* Make sure DMA does not restart by loading a new list */ 565 channel_writel(dwc, LLP, 0); 566 channel_writel(dwc, CTL_LO, 0); 567 channel_writel(dwc, CTL_HI, 0); 568 569 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 570 dma_writel(dw, CLEAR.ERROR, dwc->mask); 571 dma_writel(dw, CLEAR.XFER, dwc->mask); 572 573 for (i = 0; i < dwc->cdesc->periods; i++) 574 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); 575 576 spin_unlock_irqrestore(&dwc->lock, flags); 577 } 578 579 /* Re-enable interrupts */ 580 channel_set_bit(dw, MASK.BLOCK, dwc->mask); 581 } 582 583 /* ------------------------------------------------------------------------- */ 584 585 static void dw_dma_tasklet(unsigned long data) 586 { 587 struct dw_dma *dw = (struct dw_dma *)data; 588 struct dw_dma_chan *dwc; 589 u32 status_block; 590 u32 status_xfer; 591 u32 status_err; 592 int i; 593 594 status_block = dma_readl(dw, RAW.BLOCK); 595 status_xfer = dma_readl(dw, RAW.XFER); 596 status_err = dma_readl(dw, RAW.ERROR); 597 598 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); 599 600 for (i = 0; i < dw->dma.chancnt; i++) { 601 dwc = &dw->chan[i]; 602 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) 603 dwc_handle_cyclic(dw, dwc, status_block, status_err, 604 status_xfer); 605 else if (status_err & (1 << i)) 606 dwc_handle_error(dw, dwc); 607 else if (status_xfer & (1 << i)) 608 dwc_scan_descriptors(dw, dwc); 609 } 610 611 /* Re-enable interrupts */ 612 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); 613 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); 614 } 615 616 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) 617 { 618 struct dw_dma *dw = dev_id; 619 u32 status; 620 621 /* Check if we have any interrupt from the DMAC which is not in use */ 622 if (!dw->in_use) 623 return IRQ_NONE; 624 625 status = dma_readl(dw, STATUS_INT); 626 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); 627 628 /* Check if we have any interrupt from the DMAC */ 629 if (!status) 630 return IRQ_NONE; 631 632 /* 633 * Just disable the interrupts. We'll turn them back on in the 634 * softirq handler. 635 */ 636 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 637 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 638 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 639 640 status = dma_readl(dw, STATUS_INT); 641 if (status) { 642 dev_err(dw->dma.dev, 643 "BUG: Unexpected interrupts pending: 0x%x\n", 644 status); 645 646 /* Try to recover */ 647 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); 648 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); 649 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); 650 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); 651 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); 652 } 653 654 tasklet_schedule(&dw->tasklet); 655 656 return IRQ_HANDLED; 657 } 658 659 /*----------------------------------------------------------------------*/ 660 661 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) 662 { 663 struct dw_desc *desc = txd_to_dw_desc(tx); 664 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); 665 dma_cookie_t cookie; 666 unsigned long flags; 667 668 spin_lock_irqsave(&dwc->lock, flags); 669 cookie = dma_cookie_assign(tx); 670 671 /* 672 * REVISIT: We should attempt to chain as many descriptors as 673 * possible, perhaps even appending to those already submitted 674 * for DMA. But this is hard to do in a race-free manner. 675 */ 676 677 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); 678 list_add_tail(&desc->desc_node, &dwc->queue); 679 680 spin_unlock_irqrestore(&dwc->lock, flags); 681 682 return cookie; 683 } 684 685 static struct dma_async_tx_descriptor * 686 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 687 size_t len, unsigned long flags) 688 { 689 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 690 struct dw_dma *dw = to_dw_dma(chan->device); 691 struct dw_desc *desc; 692 struct dw_desc *first; 693 struct dw_desc *prev; 694 size_t xfer_count; 695 size_t offset; 696 unsigned int src_width; 697 unsigned int dst_width; 698 unsigned int data_width; 699 u32 ctllo; 700 701 dev_vdbg(chan2dev(chan), 702 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, 703 &dest, &src, len, flags); 704 705 if (unlikely(!len)) { 706 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); 707 return NULL; 708 } 709 710 dwc->direction = DMA_MEM_TO_MEM; 711 712 data_width = min_t(unsigned int, dw->data_width[dwc->src_master], 713 dw->data_width[dwc->dst_master]); 714 715 src_width = dst_width = min_t(unsigned int, data_width, 716 dwc_fast_ffs(src | dest | len)); 717 718 ctllo = DWC_DEFAULT_CTLLO(chan) 719 | DWC_CTLL_DST_WIDTH(dst_width) 720 | DWC_CTLL_SRC_WIDTH(src_width) 721 | DWC_CTLL_DST_INC 722 | DWC_CTLL_SRC_INC 723 | DWC_CTLL_FC_M2M; 724 prev = first = NULL; 725 726 for (offset = 0; offset < len; offset += xfer_count << src_width) { 727 xfer_count = min_t(size_t, (len - offset) >> src_width, 728 dwc->block_size); 729 730 desc = dwc_desc_get(dwc); 731 if (!desc) 732 goto err_desc_get; 733 734 desc->lli.sar = src + offset; 735 desc->lli.dar = dest + offset; 736 desc->lli.ctllo = ctllo; 737 desc->lli.ctlhi = xfer_count; 738 desc->len = xfer_count << src_width; 739 740 if (!first) { 741 first = desc; 742 } else { 743 prev->lli.llp = desc->txd.phys; 744 list_add_tail(&desc->desc_node, 745 &first->tx_list); 746 } 747 prev = desc; 748 } 749 750 if (flags & DMA_PREP_INTERRUPT) 751 /* Trigger interrupt after last block */ 752 prev->lli.ctllo |= DWC_CTLL_INT_EN; 753 754 prev->lli.llp = 0; 755 first->txd.flags = flags; 756 first->total_len = len; 757 758 return &first->txd; 759 760 err_desc_get: 761 dwc_desc_put(dwc, first); 762 return NULL; 763 } 764 765 static struct dma_async_tx_descriptor * 766 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 767 unsigned int sg_len, enum dma_transfer_direction direction, 768 unsigned long flags, void *context) 769 { 770 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 771 struct dw_dma *dw = to_dw_dma(chan->device); 772 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 773 struct dw_desc *prev; 774 struct dw_desc *first; 775 u32 ctllo; 776 dma_addr_t reg; 777 unsigned int reg_width; 778 unsigned int mem_width; 779 unsigned int data_width; 780 unsigned int i; 781 struct scatterlist *sg; 782 size_t total_len = 0; 783 784 dev_vdbg(chan2dev(chan), "%s\n", __func__); 785 786 if (unlikely(!is_slave_direction(direction) || !sg_len)) 787 return NULL; 788 789 dwc->direction = direction; 790 791 prev = first = NULL; 792 793 switch (direction) { 794 case DMA_MEM_TO_DEV: 795 reg_width = __ffs(sconfig->dst_addr_width); 796 reg = sconfig->dst_addr; 797 ctllo = (DWC_DEFAULT_CTLLO(chan) 798 | DWC_CTLL_DST_WIDTH(reg_width) 799 | DWC_CTLL_DST_FIX 800 | DWC_CTLL_SRC_INC); 801 802 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 803 DWC_CTLL_FC(DW_DMA_FC_D_M2P); 804 805 data_width = dw->data_width[dwc->src_master]; 806 807 for_each_sg(sgl, sg, sg_len, i) { 808 struct dw_desc *desc; 809 u32 len, dlen, mem; 810 811 mem = sg_dma_address(sg); 812 len = sg_dma_len(sg); 813 814 mem_width = min_t(unsigned int, 815 data_width, dwc_fast_ffs(mem | len)); 816 817 slave_sg_todev_fill_desc: 818 desc = dwc_desc_get(dwc); 819 if (!desc) 820 goto err_desc_get; 821 822 desc->lli.sar = mem; 823 desc->lli.dar = reg; 824 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); 825 if ((len >> mem_width) > dwc->block_size) { 826 dlen = dwc->block_size << mem_width; 827 mem += dlen; 828 len -= dlen; 829 } else { 830 dlen = len; 831 len = 0; 832 } 833 834 desc->lli.ctlhi = dlen >> mem_width; 835 desc->len = dlen; 836 837 if (!first) { 838 first = desc; 839 } else { 840 prev->lli.llp = desc->txd.phys; 841 list_add_tail(&desc->desc_node, 842 &first->tx_list); 843 } 844 prev = desc; 845 total_len += dlen; 846 847 if (len) 848 goto slave_sg_todev_fill_desc; 849 } 850 break; 851 case DMA_DEV_TO_MEM: 852 reg_width = __ffs(sconfig->src_addr_width); 853 reg = sconfig->src_addr; 854 ctllo = (DWC_DEFAULT_CTLLO(chan) 855 | DWC_CTLL_SRC_WIDTH(reg_width) 856 | DWC_CTLL_DST_INC 857 | DWC_CTLL_SRC_FIX); 858 859 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 860 DWC_CTLL_FC(DW_DMA_FC_D_P2M); 861 862 data_width = dw->data_width[dwc->dst_master]; 863 864 for_each_sg(sgl, sg, sg_len, i) { 865 struct dw_desc *desc; 866 u32 len, dlen, mem; 867 868 mem = sg_dma_address(sg); 869 len = sg_dma_len(sg); 870 871 mem_width = min_t(unsigned int, 872 data_width, dwc_fast_ffs(mem | len)); 873 874 slave_sg_fromdev_fill_desc: 875 desc = dwc_desc_get(dwc); 876 if (!desc) 877 goto err_desc_get; 878 879 desc->lli.sar = reg; 880 desc->lli.dar = mem; 881 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); 882 if ((len >> reg_width) > dwc->block_size) { 883 dlen = dwc->block_size << reg_width; 884 mem += dlen; 885 len -= dlen; 886 } else { 887 dlen = len; 888 len = 0; 889 } 890 desc->lli.ctlhi = dlen >> reg_width; 891 desc->len = dlen; 892 893 if (!first) { 894 first = desc; 895 } else { 896 prev->lli.llp = desc->txd.phys; 897 list_add_tail(&desc->desc_node, 898 &first->tx_list); 899 } 900 prev = desc; 901 total_len += dlen; 902 903 if (len) 904 goto slave_sg_fromdev_fill_desc; 905 } 906 break; 907 default: 908 return NULL; 909 } 910 911 if (flags & DMA_PREP_INTERRUPT) 912 /* Trigger interrupt after last block */ 913 prev->lli.ctllo |= DWC_CTLL_INT_EN; 914 915 prev->lli.llp = 0; 916 first->total_len = total_len; 917 918 return &first->txd; 919 920 err_desc_get: 921 dev_err(chan2dev(chan), 922 "not enough descriptors available. Direction %d\n", direction); 923 dwc_desc_put(dwc, first); 924 return NULL; 925 } 926 927 bool dw_dma_filter(struct dma_chan *chan, void *param) 928 { 929 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 930 struct dw_dma_slave *dws = param; 931 932 if (dws->dma_dev != chan->device->dev) 933 return false; 934 935 /* We have to copy data since dws can be temporary storage */ 936 937 dwc->src_id = dws->src_id; 938 dwc->dst_id = dws->dst_id; 939 940 dwc->src_master = dws->src_master; 941 dwc->dst_master = dws->dst_master; 942 943 return true; 944 } 945 EXPORT_SYMBOL_GPL(dw_dma_filter); 946 947 /* 948 * Fix sconfig's burst size according to dw_dmac. We need to convert them as: 949 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. 950 * 951 * NOTE: burst size 2 is not supported by controller. 952 * 953 * This can be done by finding least significant bit set: n & (n - 1) 954 */ 955 static inline void convert_burst(u32 *maxburst) 956 { 957 if (*maxburst > 1) 958 *maxburst = fls(*maxburst) - 2; 959 else 960 *maxburst = 0; 961 } 962 963 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) 964 { 965 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 966 967 /* Check if chan will be configured for slave transfers */ 968 if (!is_slave_direction(sconfig->direction)) 969 return -EINVAL; 970 971 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); 972 dwc->direction = sconfig->direction; 973 974 convert_burst(&dwc->dma_sconfig.src_maxburst); 975 convert_burst(&dwc->dma_sconfig.dst_maxburst); 976 977 return 0; 978 } 979 980 static int dwc_pause(struct dma_chan *chan) 981 { 982 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 983 unsigned long flags; 984 unsigned int count = 20; /* timeout iterations */ 985 u32 cfglo; 986 987 spin_lock_irqsave(&dwc->lock, flags); 988 989 cfglo = channel_readl(dwc, CFG_LO); 990 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); 991 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) 992 udelay(2); 993 994 dwc->paused = true; 995 996 spin_unlock_irqrestore(&dwc->lock, flags); 997 998 return 0; 999 } 1000 1001 static inline void dwc_chan_resume(struct dw_dma_chan *dwc) 1002 { 1003 u32 cfglo = channel_readl(dwc, CFG_LO); 1004 1005 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); 1006 1007 dwc->paused = false; 1008 } 1009 1010 static int dwc_resume(struct dma_chan *chan) 1011 { 1012 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1013 unsigned long flags; 1014 1015 if (!dwc->paused) 1016 return 0; 1017 1018 spin_lock_irqsave(&dwc->lock, flags); 1019 1020 dwc_chan_resume(dwc); 1021 1022 spin_unlock_irqrestore(&dwc->lock, flags); 1023 1024 return 0; 1025 } 1026 1027 static int dwc_terminate_all(struct dma_chan *chan) 1028 { 1029 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1030 struct dw_dma *dw = to_dw_dma(chan->device); 1031 struct dw_desc *desc, *_desc; 1032 unsigned long flags; 1033 LIST_HEAD(list); 1034 1035 spin_lock_irqsave(&dwc->lock, flags); 1036 1037 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 1038 1039 dwc_chan_disable(dw, dwc); 1040 1041 dwc_chan_resume(dwc); 1042 1043 /* active_list entries will end up before queued entries */ 1044 list_splice_init(&dwc->queue, &list); 1045 list_splice_init(&dwc->active_list, &list); 1046 1047 spin_unlock_irqrestore(&dwc->lock, flags); 1048 1049 /* Flush all pending and queued descriptors */ 1050 list_for_each_entry_safe(desc, _desc, &list, desc_node) 1051 dwc_descriptor_complete(dwc, desc, false); 1052 1053 return 0; 1054 } 1055 1056 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) 1057 { 1058 unsigned long flags; 1059 u32 residue; 1060 1061 spin_lock_irqsave(&dwc->lock, flags); 1062 1063 residue = dwc->residue; 1064 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) 1065 residue -= dwc_get_sent(dwc); 1066 1067 spin_unlock_irqrestore(&dwc->lock, flags); 1068 return residue; 1069 } 1070 1071 static enum dma_status 1072 dwc_tx_status(struct dma_chan *chan, 1073 dma_cookie_t cookie, 1074 struct dma_tx_state *txstate) 1075 { 1076 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1077 enum dma_status ret; 1078 1079 ret = dma_cookie_status(chan, cookie, txstate); 1080 if (ret == DMA_COMPLETE) 1081 return ret; 1082 1083 dwc_scan_descriptors(to_dw_dma(chan->device), dwc); 1084 1085 ret = dma_cookie_status(chan, cookie, txstate); 1086 if (ret != DMA_COMPLETE) 1087 dma_set_residue(txstate, dwc_get_residue(dwc)); 1088 1089 if (dwc->paused && ret == DMA_IN_PROGRESS) 1090 return DMA_PAUSED; 1091 1092 return ret; 1093 } 1094 1095 static void dwc_issue_pending(struct dma_chan *chan) 1096 { 1097 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1098 unsigned long flags; 1099 1100 spin_lock_irqsave(&dwc->lock, flags); 1101 if (list_empty(&dwc->active_list)) 1102 dwc_dostart_first_queued(dwc); 1103 spin_unlock_irqrestore(&dwc->lock, flags); 1104 } 1105 1106 /*----------------------------------------------------------------------*/ 1107 1108 static void dw_dma_off(struct dw_dma *dw) 1109 { 1110 int i; 1111 1112 dma_writel(dw, CFG, 0); 1113 1114 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 1115 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 1116 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); 1117 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); 1118 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 1119 1120 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) 1121 cpu_relax(); 1122 1123 for (i = 0; i < dw->dma.chancnt; i++) 1124 dw->chan[i].initialized = false; 1125 } 1126 1127 static void dw_dma_on(struct dw_dma *dw) 1128 { 1129 dma_writel(dw, CFG, DW_CFG_DMA_EN); 1130 } 1131 1132 static int dwc_alloc_chan_resources(struct dma_chan *chan) 1133 { 1134 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1135 struct dw_dma *dw = to_dw_dma(chan->device); 1136 struct dw_desc *desc; 1137 int i; 1138 unsigned long flags; 1139 1140 dev_vdbg(chan2dev(chan), "%s\n", __func__); 1141 1142 /* ASSERT: channel is idle */ 1143 if (dma_readl(dw, CH_EN) & dwc->mask) { 1144 dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); 1145 return -EIO; 1146 } 1147 1148 dma_cookie_init(chan); 1149 1150 /* 1151 * NOTE: some controllers may have additional features that we 1152 * need to initialize here, like "scatter-gather" (which 1153 * doesn't mean what you think it means), and status writeback. 1154 */ 1155 1156 /* 1157 * We need controller-specific data to set up slave transfers. 1158 */ 1159 if (chan->private && !dw_dma_filter(chan, chan->private)) { 1160 dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); 1161 return -EINVAL; 1162 } 1163 1164 /* Enable controller here if needed */ 1165 if (!dw->in_use) 1166 dw_dma_on(dw); 1167 dw->in_use |= dwc->mask; 1168 1169 spin_lock_irqsave(&dwc->lock, flags); 1170 i = dwc->descs_allocated; 1171 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { 1172 dma_addr_t phys; 1173 1174 spin_unlock_irqrestore(&dwc->lock, flags); 1175 1176 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); 1177 if (!desc) 1178 goto err_desc_alloc; 1179 1180 memset(desc, 0, sizeof(struct dw_desc)); 1181 1182 INIT_LIST_HEAD(&desc->tx_list); 1183 dma_async_tx_descriptor_init(&desc->txd, chan); 1184 desc->txd.tx_submit = dwc_tx_submit; 1185 desc->txd.flags = DMA_CTRL_ACK; 1186 desc->txd.phys = phys; 1187 1188 dwc_desc_put(dwc, desc); 1189 1190 spin_lock_irqsave(&dwc->lock, flags); 1191 i = ++dwc->descs_allocated; 1192 } 1193 1194 spin_unlock_irqrestore(&dwc->lock, flags); 1195 1196 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); 1197 1198 return i; 1199 1200 err_desc_alloc: 1201 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); 1202 1203 return i; 1204 } 1205 1206 static void dwc_free_chan_resources(struct dma_chan *chan) 1207 { 1208 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1209 struct dw_dma *dw = to_dw_dma(chan->device); 1210 struct dw_desc *desc, *_desc; 1211 unsigned long flags; 1212 LIST_HEAD(list); 1213 1214 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, 1215 dwc->descs_allocated); 1216 1217 /* ASSERT: channel is idle */ 1218 BUG_ON(!list_empty(&dwc->active_list)); 1219 BUG_ON(!list_empty(&dwc->queue)); 1220 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); 1221 1222 spin_lock_irqsave(&dwc->lock, flags); 1223 list_splice_init(&dwc->free_list, &list); 1224 dwc->descs_allocated = 0; 1225 1226 /* Clear custom channel configuration */ 1227 dwc->src_id = 0; 1228 dwc->dst_id = 0; 1229 1230 dwc->src_master = 0; 1231 dwc->dst_master = 0; 1232 1233 dwc->initialized = false; 1234 1235 /* Disable interrupts */ 1236 channel_clear_bit(dw, MASK.XFER, dwc->mask); 1237 channel_clear_bit(dw, MASK.BLOCK, dwc->mask); 1238 channel_clear_bit(dw, MASK.ERROR, dwc->mask); 1239 1240 spin_unlock_irqrestore(&dwc->lock, flags); 1241 1242 /* Disable controller in case it was a last user */ 1243 dw->in_use &= ~dwc->mask; 1244 if (!dw->in_use) 1245 dw_dma_off(dw); 1246 1247 list_for_each_entry_safe(desc, _desc, &list, desc_node) { 1248 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); 1249 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); 1250 } 1251 1252 dev_vdbg(chan2dev(chan), "%s: done\n", __func__); 1253 } 1254 1255 /* --------------------- Cyclic DMA API extensions -------------------- */ 1256 1257 /** 1258 * dw_dma_cyclic_start - start the cyclic DMA transfer 1259 * @chan: the DMA channel to start 1260 * 1261 * Must be called with soft interrupts disabled. Returns zero on success or 1262 * -errno on failure. 1263 */ 1264 int dw_dma_cyclic_start(struct dma_chan *chan) 1265 { 1266 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1267 struct dw_dma *dw = to_dw_dma(chan->device); 1268 unsigned long flags; 1269 1270 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { 1271 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); 1272 return -ENODEV; 1273 } 1274 1275 spin_lock_irqsave(&dwc->lock, flags); 1276 1277 /* Enable interrupts to perform cyclic transfer */ 1278 channel_set_bit(dw, MASK.BLOCK, dwc->mask); 1279 1280 dwc_dostart(dwc, dwc->cdesc->desc[0]); 1281 1282 spin_unlock_irqrestore(&dwc->lock, flags); 1283 1284 return 0; 1285 } 1286 EXPORT_SYMBOL(dw_dma_cyclic_start); 1287 1288 /** 1289 * dw_dma_cyclic_stop - stop the cyclic DMA transfer 1290 * @chan: the DMA channel to stop 1291 * 1292 * Must be called with soft interrupts disabled. 1293 */ 1294 void dw_dma_cyclic_stop(struct dma_chan *chan) 1295 { 1296 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1297 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1298 unsigned long flags; 1299 1300 spin_lock_irqsave(&dwc->lock, flags); 1301 1302 dwc_chan_disable(dw, dwc); 1303 1304 spin_unlock_irqrestore(&dwc->lock, flags); 1305 } 1306 EXPORT_SYMBOL(dw_dma_cyclic_stop); 1307 1308 /** 1309 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer 1310 * @chan: the DMA channel to prepare 1311 * @buf_addr: physical DMA address where the buffer starts 1312 * @buf_len: total number of bytes for the entire buffer 1313 * @period_len: number of bytes for each period 1314 * @direction: transfer direction, to or from device 1315 * 1316 * Must be called before trying to start the transfer. Returns a valid struct 1317 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. 1318 */ 1319 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 1320 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 1321 enum dma_transfer_direction direction) 1322 { 1323 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1324 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 1325 struct dw_cyclic_desc *cdesc; 1326 struct dw_cyclic_desc *retval = NULL; 1327 struct dw_desc *desc; 1328 struct dw_desc *last = NULL; 1329 unsigned long was_cyclic; 1330 unsigned int reg_width; 1331 unsigned int periods; 1332 unsigned int i; 1333 unsigned long flags; 1334 1335 spin_lock_irqsave(&dwc->lock, flags); 1336 if (dwc->nollp) { 1337 spin_unlock_irqrestore(&dwc->lock, flags); 1338 dev_dbg(chan2dev(&dwc->chan), 1339 "channel doesn't support LLP transfers\n"); 1340 return ERR_PTR(-EINVAL); 1341 } 1342 1343 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { 1344 spin_unlock_irqrestore(&dwc->lock, flags); 1345 dev_dbg(chan2dev(&dwc->chan), 1346 "queue and/or active list are not empty\n"); 1347 return ERR_PTR(-EBUSY); 1348 } 1349 1350 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1351 spin_unlock_irqrestore(&dwc->lock, flags); 1352 if (was_cyclic) { 1353 dev_dbg(chan2dev(&dwc->chan), 1354 "channel already prepared for cyclic DMA\n"); 1355 return ERR_PTR(-EBUSY); 1356 } 1357 1358 retval = ERR_PTR(-EINVAL); 1359 1360 if (unlikely(!is_slave_direction(direction))) 1361 goto out_err; 1362 1363 dwc->direction = direction; 1364 1365 if (direction == DMA_MEM_TO_DEV) 1366 reg_width = __ffs(sconfig->dst_addr_width); 1367 else 1368 reg_width = __ffs(sconfig->src_addr_width); 1369 1370 periods = buf_len / period_len; 1371 1372 /* Check for too big/unaligned periods and unaligned DMA buffer. */ 1373 if (period_len > (dwc->block_size << reg_width)) 1374 goto out_err; 1375 if (unlikely(period_len & ((1 << reg_width) - 1))) 1376 goto out_err; 1377 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 1378 goto out_err; 1379 1380 retval = ERR_PTR(-ENOMEM); 1381 1382 if (periods > NR_DESCS_PER_CHANNEL) 1383 goto out_err; 1384 1385 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); 1386 if (!cdesc) 1387 goto out_err; 1388 1389 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); 1390 if (!cdesc->desc) 1391 goto out_err_alloc; 1392 1393 for (i = 0; i < periods; i++) { 1394 desc = dwc_desc_get(dwc); 1395 if (!desc) 1396 goto out_err_desc_get; 1397 1398 switch (direction) { 1399 case DMA_MEM_TO_DEV: 1400 desc->lli.dar = sconfig->dst_addr; 1401 desc->lli.sar = buf_addr + (period_len * i); 1402 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) 1403 | DWC_CTLL_DST_WIDTH(reg_width) 1404 | DWC_CTLL_SRC_WIDTH(reg_width) 1405 | DWC_CTLL_DST_FIX 1406 | DWC_CTLL_SRC_INC 1407 | DWC_CTLL_INT_EN); 1408 1409 desc->lli.ctllo |= sconfig->device_fc ? 1410 DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 1411 DWC_CTLL_FC(DW_DMA_FC_D_M2P); 1412 1413 break; 1414 case DMA_DEV_TO_MEM: 1415 desc->lli.dar = buf_addr + (period_len * i); 1416 desc->lli.sar = sconfig->src_addr; 1417 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) 1418 | DWC_CTLL_SRC_WIDTH(reg_width) 1419 | DWC_CTLL_DST_WIDTH(reg_width) 1420 | DWC_CTLL_DST_INC 1421 | DWC_CTLL_SRC_FIX 1422 | DWC_CTLL_INT_EN); 1423 1424 desc->lli.ctllo |= sconfig->device_fc ? 1425 DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 1426 DWC_CTLL_FC(DW_DMA_FC_D_P2M); 1427 1428 break; 1429 default: 1430 break; 1431 } 1432 1433 desc->lli.ctlhi = (period_len >> reg_width); 1434 cdesc->desc[i] = desc; 1435 1436 if (last) 1437 last->lli.llp = desc->txd.phys; 1438 1439 last = desc; 1440 } 1441 1442 /* Let's make a cyclic list */ 1443 last->lli.llp = cdesc->desc[0]->txd.phys; 1444 1445 dev_dbg(chan2dev(&dwc->chan), 1446 "cyclic prepared buf %pad len %zu period %zu periods %d\n", 1447 &buf_addr, buf_len, period_len, periods); 1448 1449 cdesc->periods = periods; 1450 dwc->cdesc = cdesc; 1451 1452 return cdesc; 1453 1454 out_err_desc_get: 1455 while (i--) 1456 dwc_desc_put(dwc, cdesc->desc[i]); 1457 out_err_alloc: 1458 kfree(cdesc); 1459 out_err: 1460 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1461 return (struct dw_cyclic_desc *)retval; 1462 } 1463 EXPORT_SYMBOL(dw_dma_cyclic_prep); 1464 1465 /** 1466 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer 1467 * @chan: the DMA channel to free 1468 */ 1469 void dw_dma_cyclic_free(struct dma_chan *chan) 1470 { 1471 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1472 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1473 struct dw_cyclic_desc *cdesc = dwc->cdesc; 1474 int i; 1475 unsigned long flags; 1476 1477 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); 1478 1479 if (!cdesc) 1480 return; 1481 1482 spin_lock_irqsave(&dwc->lock, flags); 1483 1484 dwc_chan_disable(dw, dwc); 1485 1486 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 1487 dma_writel(dw, CLEAR.ERROR, dwc->mask); 1488 dma_writel(dw, CLEAR.XFER, dwc->mask); 1489 1490 spin_unlock_irqrestore(&dwc->lock, flags); 1491 1492 for (i = 0; i < cdesc->periods; i++) 1493 dwc_desc_put(dwc, cdesc->desc[i]); 1494 1495 kfree(cdesc->desc); 1496 kfree(cdesc); 1497 1498 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1499 } 1500 EXPORT_SYMBOL(dw_dma_cyclic_free); 1501 1502 /*----------------------------------------------------------------------*/ 1503 1504 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) 1505 { 1506 struct dw_dma *dw; 1507 bool autocfg = false; 1508 unsigned int dw_params; 1509 unsigned int max_blk_size = 0; 1510 int err; 1511 int i; 1512 1513 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); 1514 if (!dw) 1515 return -ENOMEM; 1516 1517 dw->regs = chip->regs; 1518 chip->dw = dw; 1519 1520 pm_runtime_get_sync(chip->dev); 1521 1522 if (!pdata) { 1523 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); 1524 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); 1525 1526 autocfg = dw_params >> DW_PARAMS_EN & 1; 1527 if (!autocfg) { 1528 err = -EINVAL; 1529 goto err_pdata; 1530 } 1531 1532 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); 1533 if (!pdata) { 1534 err = -ENOMEM; 1535 goto err_pdata; 1536 } 1537 1538 /* Get hardware configuration parameters */ 1539 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; 1540 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; 1541 for (i = 0; i < pdata->nr_masters; i++) { 1542 pdata->data_width[i] = 1543 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; 1544 } 1545 max_blk_size = dma_readl(dw, MAX_BLK_SIZE); 1546 1547 /* Fill platform data with the default values */ 1548 pdata->is_private = true; 1549 pdata->is_memcpy = true; 1550 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; 1551 pdata->chan_priority = CHAN_PRIORITY_ASCENDING; 1552 } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { 1553 err = -EINVAL; 1554 goto err_pdata; 1555 } 1556 1557 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), 1558 GFP_KERNEL); 1559 if (!dw->chan) { 1560 err = -ENOMEM; 1561 goto err_pdata; 1562 } 1563 1564 /* Get hardware configuration parameters */ 1565 dw->nr_masters = pdata->nr_masters; 1566 for (i = 0; i < dw->nr_masters; i++) 1567 dw->data_width[i] = pdata->data_width[i]; 1568 1569 /* Calculate all channel mask before DMA setup */ 1570 dw->all_chan_mask = (1 << pdata->nr_channels) - 1; 1571 1572 /* Force dma off, just in case */ 1573 dw_dma_off(dw); 1574 1575 /* Create a pool of consistent memory blocks for hardware descriptors */ 1576 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, 1577 sizeof(struct dw_desc), 4, 0); 1578 if (!dw->desc_pool) { 1579 dev_err(chip->dev, "No memory for descriptors dma pool\n"); 1580 err = -ENOMEM; 1581 goto err_pdata; 1582 } 1583 1584 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); 1585 1586 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, 1587 "dw_dmac", dw); 1588 if (err) 1589 goto err_pdata; 1590 1591 INIT_LIST_HEAD(&dw->dma.channels); 1592 for (i = 0; i < pdata->nr_channels; i++) { 1593 struct dw_dma_chan *dwc = &dw->chan[i]; 1594 1595 dwc->chan.device = &dw->dma; 1596 dma_cookie_init(&dwc->chan); 1597 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) 1598 list_add_tail(&dwc->chan.device_node, 1599 &dw->dma.channels); 1600 else 1601 list_add(&dwc->chan.device_node, &dw->dma.channels); 1602 1603 /* 7 is highest priority & 0 is lowest. */ 1604 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) 1605 dwc->priority = pdata->nr_channels - i - 1; 1606 else 1607 dwc->priority = i; 1608 1609 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; 1610 spin_lock_init(&dwc->lock); 1611 dwc->mask = 1 << i; 1612 1613 INIT_LIST_HEAD(&dwc->active_list); 1614 INIT_LIST_HEAD(&dwc->queue); 1615 INIT_LIST_HEAD(&dwc->free_list); 1616 1617 channel_clear_bit(dw, CH_EN, dwc->mask); 1618 1619 dwc->direction = DMA_TRANS_NONE; 1620 1621 /* Hardware configuration */ 1622 if (autocfg) { 1623 unsigned int dwc_params; 1624 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; 1625 void __iomem *addr = chip->regs + r * sizeof(u32); 1626 1627 dwc_params = dma_read_byaddr(addr, DWC_PARAMS); 1628 1629 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, 1630 dwc_params); 1631 1632 /* 1633 * Decode maximum block size for given channel. The 1634 * stored 4 bit value represents blocks from 0x00 for 3 1635 * up to 0x0a for 4095. 1636 */ 1637 dwc->block_size = 1638 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; 1639 dwc->nollp = 1640 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; 1641 } else { 1642 dwc->block_size = pdata->block_size; 1643 1644 /* Check if channel supports multi block transfer */ 1645 channel_writel(dwc, LLP, 0xfffffffc); 1646 dwc->nollp = 1647 (channel_readl(dwc, LLP) & 0xfffffffc) == 0; 1648 channel_writel(dwc, LLP, 0); 1649 } 1650 } 1651 1652 /* Clear all interrupts on all channels. */ 1653 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); 1654 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); 1655 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); 1656 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); 1657 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); 1658 1659 /* Set capabilities */ 1660 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); 1661 if (pdata->is_private) 1662 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); 1663 if (pdata->is_memcpy) 1664 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 1665 1666 dw->dma.dev = chip->dev; 1667 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; 1668 dw->dma.device_free_chan_resources = dwc_free_chan_resources; 1669 1670 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; 1671 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; 1672 1673 dw->dma.device_config = dwc_config; 1674 dw->dma.device_pause = dwc_pause; 1675 dw->dma.device_resume = dwc_resume; 1676 dw->dma.device_terminate_all = dwc_terminate_all; 1677 1678 dw->dma.device_tx_status = dwc_tx_status; 1679 dw->dma.device_issue_pending = dwc_issue_pending; 1680 1681 /* DMA capabilities */ 1682 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; 1683 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; 1684 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | 1685 BIT(DMA_MEM_TO_MEM); 1686 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1687 1688 err = dma_async_device_register(&dw->dma); 1689 if (err) 1690 goto err_dma_register; 1691 1692 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", 1693 pdata->nr_channels); 1694 1695 pm_runtime_put_sync_suspend(chip->dev); 1696 1697 return 0; 1698 1699 err_dma_register: 1700 free_irq(chip->irq, dw); 1701 err_pdata: 1702 pm_runtime_put_sync_suspend(chip->dev); 1703 return err; 1704 } 1705 EXPORT_SYMBOL_GPL(dw_dma_probe); 1706 1707 int dw_dma_remove(struct dw_dma_chip *chip) 1708 { 1709 struct dw_dma *dw = chip->dw; 1710 struct dw_dma_chan *dwc, *_dwc; 1711 1712 pm_runtime_get_sync(chip->dev); 1713 1714 dw_dma_off(dw); 1715 dma_async_device_unregister(&dw->dma); 1716 1717 free_irq(chip->irq, dw); 1718 tasklet_kill(&dw->tasklet); 1719 1720 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, 1721 chan.device_node) { 1722 list_del(&dwc->chan.device_node); 1723 channel_clear_bit(dw, CH_EN, dwc->mask); 1724 } 1725 1726 pm_runtime_put_sync_suspend(chip->dev); 1727 return 0; 1728 } 1729 EXPORT_SYMBOL_GPL(dw_dma_remove); 1730 1731 int dw_dma_disable(struct dw_dma_chip *chip) 1732 { 1733 struct dw_dma *dw = chip->dw; 1734 1735 dw_dma_off(dw); 1736 return 0; 1737 } 1738 EXPORT_SYMBOL_GPL(dw_dma_disable); 1739 1740 int dw_dma_enable(struct dw_dma_chip *chip) 1741 { 1742 struct dw_dma *dw = chip->dw; 1743 1744 dw_dma_on(dw); 1745 return 0; 1746 } 1747 EXPORT_SYMBOL_GPL(dw_dma_enable); 1748 1749 MODULE_LICENSE("GPL v2"); 1750 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); 1751 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1752 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); 1753