1 /* 2 * Core driver for the Synopsys DesignWare DMA Controller 3 * 4 * Copyright (C) 2007-2008 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * Copyright (C) 2013 Intel Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/dmapool.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/mm.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/pm_runtime.h> 26 27 #include "../dmaengine.h" 28 #include "internal.h" 29 30 /* 31 * This supports the Synopsys "DesignWare AHB Central DMA Controller", 32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all 33 * of which use ARM any more). See the "Databook" from Synopsys for 34 * information beyond what licensees probably provide. 35 * 36 * The driver has been tested with the Atmel AT32AP7000, which does not 37 * support descriptor writeback. 38 */ 39 40 /* The set of bus widths supported by the DMA controller */ 41 #define DW_DMA_BUSWIDTHS \ 42 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 43 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 44 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 45 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) 46 47 /*----------------------------------------------------------------------*/ 48 49 static struct device *chan2dev(struct dma_chan *chan) 50 { 51 return &chan->dev->device; 52 } 53 54 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) 55 { 56 return to_dw_desc(dwc->active_list.next); 57 } 58 59 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) 60 { 61 struct dw_desc *desc = txd_to_dw_desc(tx); 62 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); 63 dma_cookie_t cookie; 64 unsigned long flags; 65 66 spin_lock_irqsave(&dwc->lock, flags); 67 cookie = dma_cookie_assign(tx); 68 69 /* 70 * REVISIT: We should attempt to chain as many descriptors as 71 * possible, perhaps even appending to those already submitted 72 * for DMA. But this is hard to do in a race-free manner. 73 */ 74 75 list_add_tail(&desc->desc_node, &dwc->queue); 76 spin_unlock_irqrestore(&dwc->lock, flags); 77 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", 78 __func__, desc->txd.cookie); 79 80 return cookie; 81 } 82 83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) 84 { 85 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 86 struct dw_desc *desc; 87 dma_addr_t phys; 88 89 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); 90 if (!desc) 91 return NULL; 92 93 dwc->descs_allocated++; 94 INIT_LIST_HEAD(&desc->tx_list); 95 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); 96 desc->txd.tx_submit = dwc_tx_submit; 97 desc->txd.flags = DMA_CTRL_ACK; 98 desc->txd.phys = phys; 99 return desc; 100 } 101 102 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) 103 { 104 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 105 struct dw_desc *child, *_next; 106 107 if (unlikely(!desc)) 108 return; 109 110 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { 111 list_del(&child->desc_node); 112 dma_pool_free(dw->desc_pool, child, child->txd.phys); 113 dwc->descs_allocated--; 114 } 115 116 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); 117 dwc->descs_allocated--; 118 } 119 120 static void dwc_initialize(struct dw_dma_chan *dwc) 121 { 122 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 123 124 if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) 125 return; 126 127 dw->initialize_chan(dwc); 128 129 /* Enable interrupts */ 130 channel_set_bit(dw, MASK.XFER, dwc->mask); 131 channel_set_bit(dw, MASK.ERROR, dwc->mask); 132 133 set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); 134 } 135 136 /*----------------------------------------------------------------------*/ 137 138 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) 139 { 140 dev_err(chan2dev(&dwc->chan), 141 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", 142 channel_readl(dwc, SAR), 143 channel_readl(dwc, DAR), 144 channel_readl(dwc, LLP), 145 channel_readl(dwc, CTL_HI), 146 channel_readl(dwc, CTL_LO)); 147 } 148 149 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) 150 { 151 channel_clear_bit(dw, CH_EN, dwc->mask); 152 while (dma_readl(dw, CH_EN) & dwc->mask) 153 cpu_relax(); 154 } 155 156 /*----------------------------------------------------------------------*/ 157 158 /* Perform single block transfer */ 159 static inline void dwc_do_single_block(struct dw_dma_chan *dwc, 160 struct dw_desc *desc) 161 { 162 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 163 u32 ctllo; 164 165 /* 166 * Software emulation of LLP mode relies on interrupts to continue 167 * multi block transfer. 168 */ 169 ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; 170 171 channel_writel(dwc, SAR, lli_read(desc, sar)); 172 channel_writel(dwc, DAR, lli_read(desc, dar)); 173 channel_writel(dwc, CTL_LO, ctllo); 174 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); 175 channel_set_bit(dw, CH_EN, dwc->mask); 176 177 /* Move pointer to next descriptor */ 178 dwc->tx_node_active = dwc->tx_node_active->next; 179 } 180 181 /* Called with dwc->lock held and bh disabled */ 182 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) 183 { 184 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 185 u8 lms = DWC_LLP_LMS(dwc->dws.m_master); 186 unsigned long was_soft_llp; 187 188 /* ASSERT: channel is idle */ 189 if (dma_readl(dw, CH_EN) & dwc->mask) { 190 dev_err(chan2dev(&dwc->chan), 191 "%s: BUG: Attempted to start non-idle channel\n", 192 __func__); 193 dwc_dump_chan_regs(dwc); 194 195 /* The tasklet will hopefully advance the queue... */ 196 return; 197 } 198 199 if (dwc->nollp) { 200 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, 201 &dwc->flags); 202 if (was_soft_llp) { 203 dev_err(chan2dev(&dwc->chan), 204 "BUG: Attempted to start new LLP transfer inside ongoing one\n"); 205 return; 206 } 207 208 dwc_initialize(dwc); 209 210 first->residue = first->total_len; 211 dwc->tx_node_active = &first->tx_list; 212 213 /* Submit first block */ 214 dwc_do_single_block(dwc, first); 215 216 return; 217 } 218 219 dwc_initialize(dwc); 220 221 channel_writel(dwc, LLP, first->txd.phys | lms); 222 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 223 channel_writel(dwc, CTL_HI, 0); 224 channel_set_bit(dw, CH_EN, dwc->mask); 225 } 226 227 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) 228 { 229 struct dw_desc *desc; 230 231 if (list_empty(&dwc->queue)) 232 return; 233 234 list_move(dwc->queue.next, &dwc->active_list); 235 desc = dwc_first_active(dwc); 236 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); 237 dwc_dostart(dwc, desc); 238 } 239 240 /*----------------------------------------------------------------------*/ 241 242 static void 243 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, 244 bool callback_required) 245 { 246 struct dma_async_tx_descriptor *txd = &desc->txd; 247 struct dw_desc *child; 248 unsigned long flags; 249 struct dmaengine_desc_callback cb; 250 251 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); 252 253 spin_lock_irqsave(&dwc->lock, flags); 254 dma_cookie_complete(txd); 255 if (callback_required) 256 dmaengine_desc_get_callback(txd, &cb); 257 else 258 memset(&cb, 0, sizeof(cb)); 259 260 /* async_tx_ack */ 261 list_for_each_entry(child, &desc->tx_list, desc_node) 262 async_tx_ack(&child->txd); 263 async_tx_ack(&desc->txd); 264 dwc_desc_put(dwc, desc); 265 spin_unlock_irqrestore(&dwc->lock, flags); 266 267 dmaengine_desc_callback_invoke(&cb, NULL); 268 } 269 270 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) 271 { 272 struct dw_desc *desc, *_desc; 273 LIST_HEAD(list); 274 unsigned long flags; 275 276 spin_lock_irqsave(&dwc->lock, flags); 277 if (dma_readl(dw, CH_EN) & dwc->mask) { 278 dev_err(chan2dev(&dwc->chan), 279 "BUG: XFER bit set, but channel not idle!\n"); 280 281 /* Try to continue after resetting the channel... */ 282 dwc_chan_disable(dw, dwc); 283 } 284 285 /* 286 * Submit queued descriptors ASAP, i.e. before we go through 287 * the completed ones. 288 */ 289 list_splice_init(&dwc->active_list, &list); 290 dwc_dostart_first_queued(dwc); 291 292 spin_unlock_irqrestore(&dwc->lock, flags); 293 294 list_for_each_entry_safe(desc, _desc, &list, desc_node) 295 dwc_descriptor_complete(dwc, desc, true); 296 } 297 298 /* Returns how many bytes were already received from source */ 299 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) 300 { 301 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 302 u32 ctlhi = channel_readl(dwc, CTL_HI); 303 u32 ctllo = channel_readl(dwc, CTL_LO); 304 305 return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7); 306 } 307 308 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) 309 { 310 dma_addr_t llp; 311 struct dw_desc *desc, *_desc; 312 struct dw_desc *child; 313 u32 status_xfer; 314 unsigned long flags; 315 316 spin_lock_irqsave(&dwc->lock, flags); 317 llp = channel_readl(dwc, LLP); 318 status_xfer = dma_readl(dw, RAW.XFER); 319 320 if (status_xfer & dwc->mask) { 321 /* Everything we've submitted is done */ 322 dma_writel(dw, CLEAR.XFER, dwc->mask); 323 324 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 325 struct list_head *head, *active = dwc->tx_node_active; 326 327 /* 328 * We are inside first active descriptor. 329 * Otherwise something is really wrong. 330 */ 331 desc = dwc_first_active(dwc); 332 333 head = &desc->tx_list; 334 if (active != head) { 335 /* Update residue to reflect last sent descriptor */ 336 if (active == head->next) 337 desc->residue -= desc->len; 338 else 339 desc->residue -= to_dw_desc(active->prev)->len; 340 341 child = to_dw_desc(active); 342 343 /* Submit next block */ 344 dwc_do_single_block(dwc, child); 345 346 spin_unlock_irqrestore(&dwc->lock, flags); 347 return; 348 } 349 350 /* We are done here */ 351 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 352 } 353 354 spin_unlock_irqrestore(&dwc->lock, flags); 355 356 dwc_complete_all(dw, dwc); 357 return; 358 } 359 360 if (list_empty(&dwc->active_list)) { 361 spin_unlock_irqrestore(&dwc->lock, flags); 362 return; 363 } 364 365 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 366 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); 367 spin_unlock_irqrestore(&dwc->lock, flags); 368 return; 369 } 370 371 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); 372 373 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { 374 /* Initial residue value */ 375 desc->residue = desc->total_len; 376 377 /* Check first descriptors addr */ 378 if (desc->txd.phys == DWC_LLP_LOC(llp)) { 379 spin_unlock_irqrestore(&dwc->lock, flags); 380 return; 381 } 382 383 /* Check first descriptors llp */ 384 if (lli_read(desc, llp) == llp) { 385 /* This one is currently in progress */ 386 desc->residue -= dwc_get_sent(dwc); 387 spin_unlock_irqrestore(&dwc->lock, flags); 388 return; 389 } 390 391 desc->residue -= desc->len; 392 list_for_each_entry(child, &desc->tx_list, desc_node) { 393 if (lli_read(child, llp) == llp) { 394 /* Currently in progress */ 395 desc->residue -= dwc_get_sent(dwc); 396 spin_unlock_irqrestore(&dwc->lock, flags); 397 return; 398 } 399 desc->residue -= child->len; 400 } 401 402 /* 403 * No descriptors so far seem to be in progress, i.e. 404 * this one must be done. 405 */ 406 spin_unlock_irqrestore(&dwc->lock, flags); 407 dwc_descriptor_complete(dwc, desc, true); 408 spin_lock_irqsave(&dwc->lock, flags); 409 } 410 411 dev_err(chan2dev(&dwc->chan), 412 "BUG: All descriptors done, but channel not idle!\n"); 413 414 /* Try to continue after resetting the channel... */ 415 dwc_chan_disable(dw, dwc); 416 417 dwc_dostart_first_queued(dwc); 418 spin_unlock_irqrestore(&dwc->lock, flags); 419 } 420 421 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) 422 { 423 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", 424 lli_read(desc, sar), 425 lli_read(desc, dar), 426 lli_read(desc, llp), 427 lli_read(desc, ctlhi), 428 lli_read(desc, ctllo)); 429 } 430 431 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) 432 { 433 struct dw_desc *bad_desc; 434 struct dw_desc *child; 435 unsigned long flags; 436 437 dwc_scan_descriptors(dw, dwc); 438 439 spin_lock_irqsave(&dwc->lock, flags); 440 441 /* 442 * The descriptor currently at the head of the active list is 443 * borked. Since we don't have any way to report errors, we'll 444 * just have to scream loudly and try to carry on. 445 */ 446 bad_desc = dwc_first_active(dwc); 447 list_del_init(&bad_desc->desc_node); 448 list_move(dwc->queue.next, dwc->active_list.prev); 449 450 /* Clear the error flag and try to restart the controller */ 451 dma_writel(dw, CLEAR.ERROR, dwc->mask); 452 if (!list_empty(&dwc->active_list)) 453 dwc_dostart(dwc, dwc_first_active(dwc)); 454 455 /* 456 * WARN may seem harsh, but since this only happens 457 * when someone submits a bad physical address in a 458 * descriptor, we should consider ourselves lucky that the 459 * controller flagged an error instead of scribbling over 460 * random memory locations. 461 */ 462 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" 463 " cookie: %d\n", bad_desc->txd.cookie); 464 dwc_dump_lli(dwc, bad_desc); 465 list_for_each_entry(child, &bad_desc->tx_list, desc_node) 466 dwc_dump_lli(dwc, child); 467 468 spin_unlock_irqrestore(&dwc->lock, flags); 469 470 /* Pretend the descriptor completed successfully */ 471 dwc_descriptor_complete(dwc, bad_desc, true); 472 } 473 474 static void dw_dma_tasklet(unsigned long data) 475 { 476 struct dw_dma *dw = (struct dw_dma *)data; 477 struct dw_dma_chan *dwc; 478 u32 status_xfer; 479 u32 status_err; 480 unsigned int i; 481 482 status_xfer = dma_readl(dw, RAW.XFER); 483 status_err = dma_readl(dw, RAW.ERROR); 484 485 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); 486 487 for (i = 0; i < dw->dma.chancnt; i++) { 488 dwc = &dw->chan[i]; 489 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) 490 dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n"); 491 else if (status_err & (1 << i)) 492 dwc_handle_error(dw, dwc); 493 else if (status_xfer & (1 << i)) 494 dwc_scan_descriptors(dw, dwc); 495 } 496 497 /* Re-enable interrupts */ 498 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); 499 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); 500 } 501 502 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) 503 { 504 struct dw_dma *dw = dev_id; 505 u32 status; 506 507 /* Check if we have any interrupt from the DMAC which is not in use */ 508 if (!dw->in_use) 509 return IRQ_NONE; 510 511 status = dma_readl(dw, STATUS_INT); 512 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); 513 514 /* Check if we have any interrupt from the DMAC */ 515 if (!status) 516 return IRQ_NONE; 517 518 /* 519 * Just disable the interrupts. We'll turn them back on in the 520 * softirq handler. 521 */ 522 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 523 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 524 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 525 526 status = dma_readl(dw, STATUS_INT); 527 if (status) { 528 dev_err(dw->dma.dev, 529 "BUG: Unexpected interrupts pending: 0x%x\n", 530 status); 531 532 /* Try to recover */ 533 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); 534 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); 535 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); 536 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); 537 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); 538 } 539 540 tasklet_schedule(&dw->tasklet); 541 542 return IRQ_HANDLED; 543 } 544 545 /*----------------------------------------------------------------------*/ 546 547 static struct dma_async_tx_descriptor * 548 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 549 size_t len, unsigned long flags) 550 { 551 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 552 struct dw_dma *dw = to_dw_dma(chan->device); 553 struct dw_desc *desc; 554 struct dw_desc *first; 555 struct dw_desc *prev; 556 size_t xfer_count; 557 size_t offset; 558 u8 m_master = dwc->dws.m_master; 559 unsigned int src_width; 560 unsigned int dst_width; 561 unsigned int data_width = dw->pdata->data_width[m_master]; 562 u32 ctllo, ctlhi; 563 u8 lms = DWC_LLP_LMS(m_master); 564 565 dev_vdbg(chan2dev(chan), 566 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, 567 &dest, &src, len, flags); 568 569 if (unlikely(!len)) { 570 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); 571 return NULL; 572 } 573 574 dwc->direction = DMA_MEM_TO_MEM; 575 576 src_width = dst_width = __ffs(data_width | src | dest | len); 577 578 ctllo = dw->prepare_ctllo(dwc) 579 | DWC_CTLL_DST_WIDTH(dst_width) 580 | DWC_CTLL_SRC_WIDTH(src_width) 581 | DWC_CTLL_DST_INC 582 | DWC_CTLL_SRC_INC 583 | DWC_CTLL_FC_M2M; 584 prev = first = NULL; 585 586 for (offset = 0; offset < len; offset += xfer_count) { 587 desc = dwc_desc_get(dwc); 588 if (!desc) 589 goto err_desc_get; 590 591 ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count); 592 593 lli_write(desc, sar, src + offset); 594 lli_write(desc, dar, dest + offset); 595 lli_write(desc, ctllo, ctllo); 596 lli_write(desc, ctlhi, ctlhi); 597 desc->len = xfer_count; 598 599 if (!first) { 600 first = desc; 601 } else { 602 lli_write(prev, llp, desc->txd.phys | lms); 603 list_add_tail(&desc->desc_node, &first->tx_list); 604 } 605 prev = desc; 606 } 607 608 if (flags & DMA_PREP_INTERRUPT) 609 /* Trigger interrupt after last block */ 610 lli_set(prev, ctllo, DWC_CTLL_INT_EN); 611 612 prev->lli.llp = 0; 613 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 614 first->txd.flags = flags; 615 first->total_len = len; 616 617 return &first->txd; 618 619 err_desc_get: 620 dwc_desc_put(dwc, first); 621 return NULL; 622 } 623 624 static struct dma_async_tx_descriptor * 625 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 626 unsigned int sg_len, enum dma_transfer_direction direction, 627 unsigned long flags, void *context) 628 { 629 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 630 struct dw_dma *dw = to_dw_dma(chan->device); 631 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 632 struct dw_desc *prev; 633 struct dw_desc *first; 634 u32 ctllo, ctlhi; 635 u8 m_master = dwc->dws.m_master; 636 u8 lms = DWC_LLP_LMS(m_master); 637 dma_addr_t reg; 638 unsigned int reg_width; 639 unsigned int mem_width; 640 unsigned int data_width = dw->pdata->data_width[m_master]; 641 unsigned int i; 642 struct scatterlist *sg; 643 size_t total_len = 0; 644 645 dev_vdbg(chan2dev(chan), "%s\n", __func__); 646 647 if (unlikely(!is_slave_direction(direction) || !sg_len)) 648 return NULL; 649 650 dwc->direction = direction; 651 652 prev = first = NULL; 653 654 switch (direction) { 655 case DMA_MEM_TO_DEV: 656 reg_width = __ffs(sconfig->dst_addr_width); 657 reg = sconfig->dst_addr; 658 ctllo = dw->prepare_ctllo(dwc) 659 | DWC_CTLL_DST_WIDTH(reg_width) 660 | DWC_CTLL_DST_FIX 661 | DWC_CTLL_SRC_INC; 662 663 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 664 DWC_CTLL_FC(DW_DMA_FC_D_M2P); 665 666 for_each_sg(sgl, sg, sg_len, i) { 667 struct dw_desc *desc; 668 u32 len, mem; 669 size_t dlen; 670 671 mem = sg_dma_address(sg); 672 len = sg_dma_len(sg); 673 674 mem_width = __ffs(data_width | mem | len); 675 676 slave_sg_todev_fill_desc: 677 desc = dwc_desc_get(dwc); 678 if (!desc) 679 goto err_desc_get; 680 681 ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen); 682 683 lli_write(desc, sar, mem); 684 lli_write(desc, dar, reg); 685 lli_write(desc, ctlhi, ctlhi); 686 lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); 687 desc->len = dlen; 688 689 if (!first) { 690 first = desc; 691 } else { 692 lli_write(prev, llp, desc->txd.phys | lms); 693 list_add_tail(&desc->desc_node, &first->tx_list); 694 } 695 prev = desc; 696 697 mem += dlen; 698 len -= dlen; 699 total_len += dlen; 700 701 if (len) 702 goto slave_sg_todev_fill_desc; 703 } 704 break; 705 case DMA_DEV_TO_MEM: 706 reg_width = __ffs(sconfig->src_addr_width); 707 reg = sconfig->src_addr; 708 ctllo = dw->prepare_ctllo(dwc) 709 | DWC_CTLL_SRC_WIDTH(reg_width) 710 | DWC_CTLL_DST_INC 711 | DWC_CTLL_SRC_FIX; 712 713 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 714 DWC_CTLL_FC(DW_DMA_FC_D_P2M); 715 716 for_each_sg(sgl, sg, sg_len, i) { 717 struct dw_desc *desc; 718 u32 len, mem; 719 size_t dlen; 720 721 mem = sg_dma_address(sg); 722 len = sg_dma_len(sg); 723 724 slave_sg_fromdev_fill_desc: 725 desc = dwc_desc_get(dwc); 726 if (!desc) 727 goto err_desc_get; 728 729 ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen); 730 731 lli_write(desc, sar, reg); 732 lli_write(desc, dar, mem); 733 lli_write(desc, ctlhi, ctlhi); 734 mem_width = __ffs(data_width | mem | dlen); 735 lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); 736 desc->len = dlen; 737 738 if (!first) { 739 first = desc; 740 } else { 741 lli_write(prev, llp, desc->txd.phys | lms); 742 list_add_tail(&desc->desc_node, &first->tx_list); 743 } 744 prev = desc; 745 746 mem += dlen; 747 len -= dlen; 748 total_len += dlen; 749 750 if (len) 751 goto slave_sg_fromdev_fill_desc; 752 } 753 break; 754 default: 755 return NULL; 756 } 757 758 if (flags & DMA_PREP_INTERRUPT) 759 /* Trigger interrupt after last block */ 760 lli_set(prev, ctllo, DWC_CTLL_INT_EN); 761 762 prev->lli.llp = 0; 763 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 764 first->total_len = total_len; 765 766 return &first->txd; 767 768 err_desc_get: 769 dev_err(chan2dev(chan), 770 "not enough descriptors available. Direction %d\n", direction); 771 dwc_desc_put(dwc, first); 772 return NULL; 773 } 774 775 bool dw_dma_filter(struct dma_chan *chan, void *param) 776 { 777 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 778 struct dw_dma_slave *dws = param; 779 780 if (dws->dma_dev != chan->device->dev) 781 return false; 782 783 /* We have to copy data since dws can be temporary storage */ 784 memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); 785 786 return true; 787 } 788 EXPORT_SYMBOL_GPL(dw_dma_filter); 789 790 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) 791 { 792 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 793 struct dw_dma *dw = to_dw_dma(chan->device); 794 795 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); 796 797 dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst); 798 dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst); 799 800 return 0; 801 } 802 803 static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain) 804 { 805 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 806 unsigned int count = 20; /* timeout iterations */ 807 808 dw->suspend_chan(dwc, drain); 809 810 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) 811 udelay(2); 812 813 set_bit(DW_DMA_IS_PAUSED, &dwc->flags); 814 } 815 816 static int dwc_pause(struct dma_chan *chan) 817 { 818 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 819 unsigned long flags; 820 821 spin_lock_irqsave(&dwc->lock, flags); 822 dwc_chan_pause(dwc, false); 823 spin_unlock_irqrestore(&dwc->lock, flags); 824 825 return 0; 826 } 827 828 static inline void dwc_chan_resume(struct dw_dma_chan *dwc, bool drain) 829 { 830 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 831 832 dw->resume_chan(dwc, drain); 833 834 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); 835 } 836 837 static int dwc_resume(struct dma_chan *chan) 838 { 839 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 840 unsigned long flags; 841 842 spin_lock_irqsave(&dwc->lock, flags); 843 844 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) 845 dwc_chan_resume(dwc, false); 846 847 spin_unlock_irqrestore(&dwc->lock, flags); 848 849 return 0; 850 } 851 852 static int dwc_terminate_all(struct dma_chan *chan) 853 { 854 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 855 struct dw_dma *dw = to_dw_dma(chan->device); 856 struct dw_desc *desc, *_desc; 857 unsigned long flags; 858 LIST_HEAD(list); 859 860 spin_lock_irqsave(&dwc->lock, flags); 861 862 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 863 864 dwc_chan_pause(dwc, true); 865 866 dwc_chan_disable(dw, dwc); 867 868 dwc_chan_resume(dwc, true); 869 870 /* active_list entries will end up before queued entries */ 871 list_splice_init(&dwc->queue, &list); 872 list_splice_init(&dwc->active_list, &list); 873 874 spin_unlock_irqrestore(&dwc->lock, flags); 875 876 /* Flush all pending and queued descriptors */ 877 list_for_each_entry_safe(desc, _desc, &list, desc_node) 878 dwc_descriptor_complete(dwc, desc, false); 879 880 return 0; 881 } 882 883 static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c) 884 { 885 struct dw_desc *desc; 886 887 list_for_each_entry(desc, &dwc->active_list, desc_node) 888 if (desc->txd.cookie == c) 889 return desc; 890 891 return NULL; 892 } 893 894 static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie) 895 { 896 struct dw_desc *desc; 897 unsigned long flags; 898 u32 residue; 899 900 spin_lock_irqsave(&dwc->lock, flags); 901 902 desc = dwc_find_desc(dwc, cookie); 903 if (desc) { 904 if (desc == dwc_first_active(dwc)) { 905 residue = desc->residue; 906 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) 907 residue -= dwc_get_sent(dwc); 908 } else { 909 residue = desc->total_len; 910 } 911 } else { 912 residue = 0; 913 } 914 915 spin_unlock_irqrestore(&dwc->lock, flags); 916 return residue; 917 } 918 919 static enum dma_status 920 dwc_tx_status(struct dma_chan *chan, 921 dma_cookie_t cookie, 922 struct dma_tx_state *txstate) 923 { 924 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 925 enum dma_status ret; 926 927 ret = dma_cookie_status(chan, cookie, txstate); 928 if (ret == DMA_COMPLETE) 929 return ret; 930 931 dwc_scan_descriptors(to_dw_dma(chan->device), dwc); 932 933 ret = dma_cookie_status(chan, cookie, txstate); 934 if (ret == DMA_COMPLETE) 935 return ret; 936 937 dma_set_residue(txstate, dwc_get_residue(dwc, cookie)); 938 939 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) 940 return DMA_PAUSED; 941 942 return ret; 943 } 944 945 static void dwc_issue_pending(struct dma_chan *chan) 946 { 947 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 948 unsigned long flags; 949 950 spin_lock_irqsave(&dwc->lock, flags); 951 if (list_empty(&dwc->active_list)) 952 dwc_dostart_first_queued(dwc); 953 spin_unlock_irqrestore(&dwc->lock, flags); 954 } 955 956 /*----------------------------------------------------------------------*/ 957 958 void do_dw_dma_off(struct dw_dma *dw) 959 { 960 unsigned int i; 961 962 dma_writel(dw, CFG, 0); 963 964 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 965 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 966 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); 967 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); 968 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 969 970 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) 971 cpu_relax(); 972 973 for (i = 0; i < dw->dma.chancnt; i++) 974 clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags); 975 } 976 977 void do_dw_dma_on(struct dw_dma *dw) 978 { 979 dma_writel(dw, CFG, DW_CFG_DMA_EN); 980 } 981 982 static int dwc_alloc_chan_resources(struct dma_chan *chan) 983 { 984 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 985 struct dw_dma *dw = to_dw_dma(chan->device); 986 987 dev_vdbg(chan2dev(chan), "%s\n", __func__); 988 989 /* ASSERT: channel is idle */ 990 if (dma_readl(dw, CH_EN) & dwc->mask) { 991 dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); 992 return -EIO; 993 } 994 995 dma_cookie_init(chan); 996 997 /* 998 * NOTE: some controllers may have additional features that we 999 * need to initialize here, like "scatter-gather" (which 1000 * doesn't mean what you think it means), and status writeback. 1001 */ 1002 1003 /* 1004 * We need controller-specific data to set up slave transfers. 1005 */ 1006 if (chan->private && !dw_dma_filter(chan, chan->private)) { 1007 dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); 1008 return -EINVAL; 1009 } 1010 1011 /* Enable controller here if needed */ 1012 if (!dw->in_use) 1013 do_dw_dma_on(dw); 1014 dw->in_use |= dwc->mask; 1015 1016 return 0; 1017 } 1018 1019 static void dwc_free_chan_resources(struct dma_chan *chan) 1020 { 1021 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1022 struct dw_dma *dw = to_dw_dma(chan->device); 1023 unsigned long flags; 1024 LIST_HEAD(list); 1025 1026 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, 1027 dwc->descs_allocated); 1028 1029 /* ASSERT: channel is idle */ 1030 BUG_ON(!list_empty(&dwc->active_list)); 1031 BUG_ON(!list_empty(&dwc->queue)); 1032 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); 1033 1034 spin_lock_irqsave(&dwc->lock, flags); 1035 1036 /* Clear custom channel configuration */ 1037 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); 1038 1039 clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); 1040 1041 /* Disable interrupts */ 1042 channel_clear_bit(dw, MASK.XFER, dwc->mask); 1043 channel_clear_bit(dw, MASK.BLOCK, dwc->mask); 1044 channel_clear_bit(dw, MASK.ERROR, dwc->mask); 1045 1046 spin_unlock_irqrestore(&dwc->lock, flags); 1047 1048 /* Disable controller in case it was a last user */ 1049 dw->in_use &= ~dwc->mask; 1050 if (!dw->in_use) 1051 do_dw_dma_off(dw); 1052 1053 dev_vdbg(chan2dev(chan), "%s: done\n", __func__); 1054 } 1055 1056 int do_dma_probe(struct dw_dma_chip *chip) 1057 { 1058 struct dw_dma *dw = chip->dw; 1059 struct dw_dma_platform_data *pdata; 1060 bool autocfg = false; 1061 unsigned int dw_params; 1062 unsigned int i; 1063 int err; 1064 1065 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); 1066 if (!dw->pdata) 1067 return -ENOMEM; 1068 1069 dw->regs = chip->regs; 1070 1071 pm_runtime_get_sync(chip->dev); 1072 1073 if (!chip->pdata) { 1074 dw_params = dma_readl(dw, DW_PARAMS); 1075 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); 1076 1077 autocfg = dw_params >> DW_PARAMS_EN & 1; 1078 if (!autocfg) { 1079 err = -EINVAL; 1080 goto err_pdata; 1081 } 1082 1083 /* Reassign the platform data pointer */ 1084 pdata = dw->pdata; 1085 1086 /* Get hardware configuration parameters */ 1087 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; 1088 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; 1089 for (i = 0; i < pdata->nr_masters; i++) { 1090 pdata->data_width[i] = 1091 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3); 1092 } 1093 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); 1094 1095 /* Fill platform data with the default values */ 1096 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; 1097 pdata->chan_priority = CHAN_PRIORITY_ASCENDING; 1098 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { 1099 err = -EINVAL; 1100 goto err_pdata; 1101 } else { 1102 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); 1103 1104 /* Reassign the platform data pointer */ 1105 pdata = dw->pdata; 1106 } 1107 1108 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), 1109 GFP_KERNEL); 1110 if (!dw->chan) { 1111 err = -ENOMEM; 1112 goto err_pdata; 1113 } 1114 1115 /* Calculate all channel mask before DMA setup */ 1116 dw->all_chan_mask = (1 << pdata->nr_channels) - 1; 1117 1118 /* Force dma off, just in case */ 1119 dw->disable(dw); 1120 1121 /* Device and instance ID for IRQ and DMA pool */ 1122 dw->set_device_name(dw, chip->id); 1123 1124 /* Create a pool of consistent memory blocks for hardware descriptors */ 1125 dw->desc_pool = dmam_pool_create(dw->name, chip->dev, 1126 sizeof(struct dw_desc), 4, 0); 1127 if (!dw->desc_pool) { 1128 dev_err(chip->dev, "No memory for descriptors dma pool\n"); 1129 err = -ENOMEM; 1130 goto err_pdata; 1131 } 1132 1133 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); 1134 1135 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, 1136 dw->name, dw); 1137 if (err) 1138 goto err_pdata; 1139 1140 INIT_LIST_HEAD(&dw->dma.channels); 1141 for (i = 0; i < pdata->nr_channels; i++) { 1142 struct dw_dma_chan *dwc = &dw->chan[i]; 1143 1144 dwc->chan.device = &dw->dma; 1145 dma_cookie_init(&dwc->chan); 1146 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) 1147 list_add_tail(&dwc->chan.device_node, 1148 &dw->dma.channels); 1149 else 1150 list_add(&dwc->chan.device_node, &dw->dma.channels); 1151 1152 /* 7 is highest priority & 0 is lowest. */ 1153 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) 1154 dwc->priority = pdata->nr_channels - i - 1; 1155 else 1156 dwc->priority = i; 1157 1158 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; 1159 spin_lock_init(&dwc->lock); 1160 dwc->mask = 1 << i; 1161 1162 INIT_LIST_HEAD(&dwc->active_list); 1163 INIT_LIST_HEAD(&dwc->queue); 1164 1165 channel_clear_bit(dw, CH_EN, dwc->mask); 1166 1167 dwc->direction = DMA_TRANS_NONE; 1168 1169 /* Hardware configuration */ 1170 if (autocfg) { 1171 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; 1172 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; 1173 unsigned int dwc_params = readl(addr); 1174 1175 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, 1176 dwc_params); 1177 1178 /* 1179 * Decode maximum block size for given channel. The 1180 * stored 4 bit value represents blocks from 0x00 for 3 1181 * up to 0x0a for 4095. 1182 */ 1183 dwc->block_size = 1184 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; 1185 dwc->nollp = 1186 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; 1187 } else { 1188 dwc->block_size = pdata->block_size; 1189 dwc->nollp = !pdata->multi_block[i]; 1190 } 1191 } 1192 1193 /* Clear all interrupts on all channels. */ 1194 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); 1195 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); 1196 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); 1197 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); 1198 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); 1199 1200 /* Set capabilities */ 1201 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); 1202 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); 1203 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 1204 1205 dw->dma.dev = chip->dev; 1206 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; 1207 dw->dma.device_free_chan_resources = dwc_free_chan_resources; 1208 1209 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; 1210 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; 1211 1212 dw->dma.device_config = dwc_config; 1213 dw->dma.device_pause = dwc_pause; 1214 dw->dma.device_resume = dwc_resume; 1215 dw->dma.device_terminate_all = dwc_terminate_all; 1216 1217 dw->dma.device_tx_status = dwc_tx_status; 1218 dw->dma.device_issue_pending = dwc_issue_pending; 1219 1220 /* DMA capabilities */ 1221 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; 1222 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; 1223 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | 1224 BIT(DMA_MEM_TO_MEM); 1225 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1226 1227 err = dma_async_device_register(&dw->dma); 1228 if (err) 1229 goto err_dma_register; 1230 1231 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", 1232 pdata->nr_channels); 1233 1234 pm_runtime_put_sync_suspend(chip->dev); 1235 1236 return 0; 1237 1238 err_dma_register: 1239 free_irq(chip->irq, dw); 1240 err_pdata: 1241 pm_runtime_put_sync_suspend(chip->dev); 1242 return err; 1243 } 1244 1245 int do_dma_remove(struct dw_dma_chip *chip) 1246 { 1247 struct dw_dma *dw = chip->dw; 1248 struct dw_dma_chan *dwc, *_dwc; 1249 1250 pm_runtime_get_sync(chip->dev); 1251 1252 do_dw_dma_off(dw); 1253 dma_async_device_unregister(&dw->dma); 1254 1255 free_irq(chip->irq, dw); 1256 tasklet_kill(&dw->tasklet); 1257 1258 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, 1259 chan.device_node) { 1260 list_del(&dwc->chan.device_node); 1261 channel_clear_bit(dw, CH_EN, dwc->mask); 1262 } 1263 1264 pm_runtime_put_sync_suspend(chip->dev); 1265 return 0; 1266 } 1267 1268 int do_dw_dma_disable(struct dw_dma_chip *chip) 1269 { 1270 struct dw_dma *dw = chip->dw; 1271 1272 dw->disable(dw); 1273 return 0; 1274 } 1275 EXPORT_SYMBOL_GPL(do_dw_dma_disable); 1276 1277 int do_dw_dma_enable(struct dw_dma_chip *chip) 1278 { 1279 struct dw_dma *dw = chip->dw; 1280 1281 dw->enable(dw); 1282 return 0; 1283 } 1284 EXPORT_SYMBOL_GPL(do_dw_dma_enable); 1285 1286 MODULE_LICENSE("GPL v2"); 1287 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); 1288 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1289 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); 1290