1 /* 2 * Core driver for the Synopsys DesignWare DMA Controller 3 * 4 * Copyright (C) 2007-2008 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * Copyright (C) 2013 Intel Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/dmapool.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/mm.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/pm_runtime.h> 26 27 #include "../dmaengine.h" 28 #include "internal.h" 29 30 /* 31 * This supports the Synopsys "DesignWare AHB Central DMA Controller", 32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all 33 * of which use ARM any more). See the "Databook" from Synopsys for 34 * information beyond what licensees probably provide. 35 * 36 * The driver has been tested with the Atmel AT32AP7000, which does not 37 * support descriptor writeback. 38 */ 39 40 #define DWC_DEFAULT_CTLLO(_chan) ({ \ 41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ 42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ 43 bool _is_slave = is_slave_direction(_dwc->direction); \ 44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ 45 DW_DMA_MSIZE_16; \ 46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ 47 DW_DMA_MSIZE_16; \ 48 \ 49 (DWC_CTLL_DST_MSIZE(_dmsize) \ 50 | DWC_CTLL_SRC_MSIZE(_smsize) \ 51 | DWC_CTLL_LLP_D_EN \ 52 | DWC_CTLL_LLP_S_EN \ 53 | DWC_CTLL_DMS(_dwc->dst_master) \ 54 | DWC_CTLL_SMS(_dwc->src_master)); \ 55 }) 56 57 /* 58 * Number of descriptors to allocate for each channel. This should be 59 * made configurable somehow; preferably, the clients (at least the 60 * ones using slave transfers) should be able to give us a hint. 61 */ 62 #define NR_DESCS_PER_CHANNEL 64 63 64 /*----------------------------------------------------------------------*/ 65 66 static struct device *chan2dev(struct dma_chan *chan) 67 { 68 return &chan->dev->device; 69 } 70 71 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) 72 { 73 return to_dw_desc(dwc->active_list.next); 74 } 75 76 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) 77 { 78 struct dw_desc *desc, *_desc; 79 struct dw_desc *ret = NULL; 80 unsigned int i = 0; 81 unsigned long flags; 82 83 spin_lock_irqsave(&dwc->lock, flags); 84 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { 85 i++; 86 if (async_tx_test_ack(&desc->txd)) { 87 list_del(&desc->desc_node); 88 ret = desc; 89 break; 90 } 91 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); 92 } 93 spin_unlock_irqrestore(&dwc->lock, flags); 94 95 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); 96 97 return ret; 98 } 99 100 /* 101 * Move a descriptor, including any children, to the free list. 102 * `desc' must not be on any lists. 103 */ 104 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) 105 { 106 unsigned long flags; 107 108 if (desc) { 109 struct dw_desc *child; 110 111 spin_lock_irqsave(&dwc->lock, flags); 112 list_for_each_entry(child, &desc->tx_list, desc_node) 113 dev_vdbg(chan2dev(&dwc->chan), 114 "moving child desc %p to freelist\n", 115 child); 116 list_splice_init(&desc->tx_list, &dwc->free_list); 117 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); 118 list_add(&desc->desc_node, &dwc->free_list); 119 spin_unlock_irqrestore(&dwc->lock, flags); 120 } 121 } 122 123 static void dwc_initialize(struct dw_dma_chan *dwc) 124 { 125 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 126 struct dw_dma_slave *dws = dwc->chan.private; 127 u32 cfghi = DWC_CFGH_FIFO_MODE; 128 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); 129 130 if (dwc->initialized == true) 131 return; 132 133 if (dws) { 134 /* 135 * We need controller-specific data to set up slave 136 * transfers. 137 */ 138 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); 139 140 cfghi |= DWC_CFGH_DST_PER(dws->dst_id); 141 cfghi |= DWC_CFGH_SRC_PER(dws->src_id); 142 } else { 143 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); 144 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); 145 } 146 147 channel_writel(dwc, CFG_LO, cfglo); 148 channel_writel(dwc, CFG_HI, cfghi); 149 150 /* Enable interrupts */ 151 channel_set_bit(dw, MASK.XFER, dwc->mask); 152 channel_set_bit(dw, MASK.ERROR, dwc->mask); 153 154 dwc->initialized = true; 155 } 156 157 /*----------------------------------------------------------------------*/ 158 159 static inline unsigned int dwc_fast_fls(unsigned long long v) 160 { 161 /* 162 * We can be a lot more clever here, but this should take care 163 * of the most common optimization. 164 */ 165 if (!(v & 7)) 166 return 3; 167 else if (!(v & 3)) 168 return 2; 169 else if (!(v & 1)) 170 return 1; 171 return 0; 172 } 173 174 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) 175 { 176 dev_err(chan2dev(&dwc->chan), 177 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", 178 channel_readl(dwc, SAR), 179 channel_readl(dwc, DAR), 180 channel_readl(dwc, LLP), 181 channel_readl(dwc, CTL_HI), 182 channel_readl(dwc, CTL_LO)); 183 } 184 185 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) 186 { 187 channel_clear_bit(dw, CH_EN, dwc->mask); 188 while (dma_readl(dw, CH_EN) & dwc->mask) 189 cpu_relax(); 190 } 191 192 /*----------------------------------------------------------------------*/ 193 194 /* Perform single block transfer */ 195 static inline void dwc_do_single_block(struct dw_dma_chan *dwc, 196 struct dw_desc *desc) 197 { 198 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 199 u32 ctllo; 200 201 /* 202 * Software emulation of LLP mode relies on interrupts to continue 203 * multi block transfer. 204 */ 205 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; 206 207 channel_writel(dwc, SAR, desc->lli.sar); 208 channel_writel(dwc, DAR, desc->lli.dar); 209 channel_writel(dwc, CTL_LO, ctllo); 210 channel_writel(dwc, CTL_HI, desc->lli.ctlhi); 211 channel_set_bit(dw, CH_EN, dwc->mask); 212 213 /* Move pointer to next descriptor */ 214 dwc->tx_node_active = dwc->tx_node_active->next; 215 } 216 217 /* Called with dwc->lock held and bh disabled */ 218 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) 219 { 220 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 221 unsigned long was_soft_llp; 222 223 /* ASSERT: channel is idle */ 224 if (dma_readl(dw, CH_EN) & dwc->mask) { 225 dev_err(chan2dev(&dwc->chan), 226 "BUG: Attempted to start non-idle channel\n"); 227 dwc_dump_chan_regs(dwc); 228 229 /* The tasklet will hopefully advance the queue... */ 230 return; 231 } 232 233 if (dwc->nollp) { 234 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, 235 &dwc->flags); 236 if (was_soft_llp) { 237 dev_err(chan2dev(&dwc->chan), 238 "BUG: Attempted to start new LLP transfer inside ongoing one\n"); 239 return; 240 } 241 242 dwc_initialize(dwc); 243 244 dwc->residue = first->total_len; 245 dwc->tx_node_active = &first->tx_list; 246 247 /* Submit first block */ 248 dwc_do_single_block(dwc, first); 249 250 return; 251 } 252 253 dwc_initialize(dwc); 254 255 channel_writel(dwc, LLP, first->txd.phys); 256 channel_writel(dwc, CTL_LO, 257 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 258 channel_writel(dwc, CTL_HI, 0); 259 channel_set_bit(dw, CH_EN, dwc->mask); 260 } 261 262 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) 263 { 264 struct dw_desc *desc; 265 266 if (list_empty(&dwc->queue)) 267 return; 268 269 list_move(dwc->queue.next, &dwc->active_list); 270 desc = dwc_first_active(dwc); 271 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); 272 dwc_dostart(dwc, desc); 273 } 274 275 /*----------------------------------------------------------------------*/ 276 277 static void 278 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, 279 bool callback_required) 280 { 281 dma_async_tx_callback callback = NULL; 282 void *param = NULL; 283 struct dma_async_tx_descriptor *txd = &desc->txd; 284 struct dw_desc *child; 285 unsigned long flags; 286 287 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); 288 289 spin_lock_irqsave(&dwc->lock, flags); 290 dma_cookie_complete(txd); 291 if (callback_required) { 292 callback = txd->callback; 293 param = txd->callback_param; 294 } 295 296 /* async_tx_ack */ 297 list_for_each_entry(child, &desc->tx_list, desc_node) 298 async_tx_ack(&child->txd); 299 async_tx_ack(&desc->txd); 300 301 list_splice_init(&desc->tx_list, &dwc->free_list); 302 list_move(&desc->desc_node, &dwc->free_list); 303 304 dma_descriptor_unmap(txd); 305 spin_unlock_irqrestore(&dwc->lock, flags); 306 307 if (callback) 308 callback(param); 309 } 310 311 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) 312 { 313 struct dw_desc *desc, *_desc; 314 LIST_HEAD(list); 315 unsigned long flags; 316 317 spin_lock_irqsave(&dwc->lock, flags); 318 if (dma_readl(dw, CH_EN) & dwc->mask) { 319 dev_err(chan2dev(&dwc->chan), 320 "BUG: XFER bit set, but channel not idle!\n"); 321 322 /* Try to continue after resetting the channel... */ 323 dwc_chan_disable(dw, dwc); 324 } 325 326 /* 327 * Submit queued descriptors ASAP, i.e. before we go through 328 * the completed ones. 329 */ 330 list_splice_init(&dwc->active_list, &list); 331 dwc_dostart_first_queued(dwc); 332 333 spin_unlock_irqrestore(&dwc->lock, flags); 334 335 list_for_each_entry_safe(desc, _desc, &list, desc_node) 336 dwc_descriptor_complete(dwc, desc, true); 337 } 338 339 /* Returns how many bytes were already received from source */ 340 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) 341 { 342 u32 ctlhi = channel_readl(dwc, CTL_HI); 343 u32 ctllo = channel_readl(dwc, CTL_LO); 344 345 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); 346 } 347 348 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) 349 { 350 dma_addr_t llp; 351 struct dw_desc *desc, *_desc; 352 struct dw_desc *child; 353 u32 status_xfer; 354 unsigned long flags; 355 356 spin_lock_irqsave(&dwc->lock, flags); 357 llp = channel_readl(dwc, LLP); 358 status_xfer = dma_readl(dw, RAW.XFER); 359 360 if (status_xfer & dwc->mask) { 361 /* Everything we've submitted is done */ 362 dma_writel(dw, CLEAR.XFER, dwc->mask); 363 364 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 365 struct list_head *head, *active = dwc->tx_node_active; 366 367 /* 368 * We are inside first active descriptor. 369 * Otherwise something is really wrong. 370 */ 371 desc = dwc_first_active(dwc); 372 373 head = &desc->tx_list; 374 if (active != head) { 375 /* Update desc to reflect last sent one */ 376 if (active != head->next) 377 desc = to_dw_desc(active->prev); 378 379 dwc->residue -= desc->len; 380 381 child = to_dw_desc(active); 382 383 /* Submit next block */ 384 dwc_do_single_block(dwc, child); 385 386 spin_unlock_irqrestore(&dwc->lock, flags); 387 return; 388 } 389 390 /* We are done here */ 391 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 392 } 393 394 dwc->residue = 0; 395 396 spin_unlock_irqrestore(&dwc->lock, flags); 397 398 dwc_complete_all(dw, dwc); 399 return; 400 } 401 402 if (list_empty(&dwc->active_list)) { 403 dwc->residue = 0; 404 spin_unlock_irqrestore(&dwc->lock, flags); 405 return; 406 } 407 408 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 409 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); 410 spin_unlock_irqrestore(&dwc->lock, flags); 411 return; 412 } 413 414 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); 415 416 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { 417 /* Initial residue value */ 418 dwc->residue = desc->total_len; 419 420 /* Check first descriptors addr */ 421 if (desc->txd.phys == llp) { 422 spin_unlock_irqrestore(&dwc->lock, flags); 423 return; 424 } 425 426 /* Check first descriptors llp */ 427 if (desc->lli.llp == llp) { 428 /* This one is currently in progress */ 429 dwc->residue -= dwc_get_sent(dwc); 430 spin_unlock_irqrestore(&dwc->lock, flags); 431 return; 432 } 433 434 dwc->residue -= desc->len; 435 list_for_each_entry(child, &desc->tx_list, desc_node) { 436 if (child->lli.llp == llp) { 437 /* Currently in progress */ 438 dwc->residue -= dwc_get_sent(dwc); 439 spin_unlock_irqrestore(&dwc->lock, flags); 440 return; 441 } 442 dwc->residue -= child->len; 443 } 444 445 /* 446 * No descriptors so far seem to be in progress, i.e. 447 * this one must be done. 448 */ 449 spin_unlock_irqrestore(&dwc->lock, flags); 450 dwc_descriptor_complete(dwc, desc, true); 451 spin_lock_irqsave(&dwc->lock, flags); 452 } 453 454 dev_err(chan2dev(&dwc->chan), 455 "BUG: All descriptors done, but channel not idle!\n"); 456 457 /* Try to continue after resetting the channel... */ 458 dwc_chan_disable(dw, dwc); 459 460 dwc_dostart_first_queued(dwc); 461 spin_unlock_irqrestore(&dwc->lock, flags); 462 } 463 464 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) 465 { 466 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", 467 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); 468 } 469 470 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) 471 { 472 struct dw_desc *bad_desc; 473 struct dw_desc *child; 474 unsigned long flags; 475 476 dwc_scan_descriptors(dw, dwc); 477 478 spin_lock_irqsave(&dwc->lock, flags); 479 480 /* 481 * The descriptor currently at the head of the active list is 482 * borked. Since we don't have any way to report errors, we'll 483 * just have to scream loudly and try to carry on. 484 */ 485 bad_desc = dwc_first_active(dwc); 486 list_del_init(&bad_desc->desc_node); 487 list_move(dwc->queue.next, dwc->active_list.prev); 488 489 /* Clear the error flag and try to restart the controller */ 490 dma_writel(dw, CLEAR.ERROR, dwc->mask); 491 if (!list_empty(&dwc->active_list)) 492 dwc_dostart(dwc, dwc_first_active(dwc)); 493 494 /* 495 * WARN may seem harsh, but since this only happens 496 * when someone submits a bad physical address in a 497 * descriptor, we should consider ourselves lucky that the 498 * controller flagged an error instead of scribbling over 499 * random memory locations. 500 */ 501 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" 502 " cookie: %d\n", bad_desc->txd.cookie); 503 dwc_dump_lli(dwc, &bad_desc->lli); 504 list_for_each_entry(child, &bad_desc->tx_list, desc_node) 505 dwc_dump_lli(dwc, &child->lli); 506 507 spin_unlock_irqrestore(&dwc->lock, flags); 508 509 /* Pretend the descriptor completed successfully */ 510 dwc_descriptor_complete(dwc, bad_desc, true); 511 } 512 513 /* --------------------- Cyclic DMA API extensions -------------------- */ 514 515 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) 516 { 517 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 518 return channel_readl(dwc, SAR); 519 } 520 EXPORT_SYMBOL(dw_dma_get_src_addr); 521 522 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) 523 { 524 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 525 return channel_readl(dwc, DAR); 526 } 527 EXPORT_SYMBOL(dw_dma_get_dst_addr); 528 529 /* Called with dwc->lock held and all DMAC interrupts disabled */ 530 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, 531 u32 status_err, u32 status_xfer) 532 { 533 unsigned long flags; 534 535 if (dwc->mask) { 536 void (*callback)(void *param); 537 void *callback_param; 538 539 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", 540 channel_readl(dwc, LLP)); 541 542 callback = dwc->cdesc->period_callback; 543 callback_param = dwc->cdesc->period_callback_param; 544 545 if (callback) 546 callback(callback_param); 547 } 548 549 /* 550 * Error and transfer complete are highly unlikely, and will most 551 * likely be due to a configuration error by the user. 552 */ 553 if (unlikely(status_err & dwc->mask) || 554 unlikely(status_xfer & dwc->mask)) { 555 int i; 556 557 dev_err(chan2dev(&dwc->chan), 558 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", 559 status_xfer ? "xfer" : "error"); 560 561 spin_lock_irqsave(&dwc->lock, flags); 562 563 dwc_dump_chan_regs(dwc); 564 565 dwc_chan_disable(dw, dwc); 566 567 /* Make sure DMA does not restart by loading a new list */ 568 channel_writel(dwc, LLP, 0); 569 channel_writel(dwc, CTL_LO, 0); 570 channel_writel(dwc, CTL_HI, 0); 571 572 dma_writel(dw, CLEAR.ERROR, dwc->mask); 573 dma_writel(dw, CLEAR.XFER, dwc->mask); 574 575 for (i = 0; i < dwc->cdesc->periods; i++) 576 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); 577 578 spin_unlock_irqrestore(&dwc->lock, flags); 579 } 580 } 581 582 /* ------------------------------------------------------------------------- */ 583 584 static void dw_dma_tasklet(unsigned long data) 585 { 586 struct dw_dma *dw = (struct dw_dma *)data; 587 struct dw_dma_chan *dwc; 588 u32 status_xfer; 589 u32 status_err; 590 int i; 591 592 status_xfer = dma_readl(dw, RAW.XFER); 593 status_err = dma_readl(dw, RAW.ERROR); 594 595 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); 596 597 for (i = 0; i < dw->dma.chancnt; i++) { 598 dwc = &dw->chan[i]; 599 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) 600 dwc_handle_cyclic(dw, dwc, status_err, status_xfer); 601 else if (status_err & (1 << i)) 602 dwc_handle_error(dw, dwc); 603 else if (status_xfer & (1 << i)) 604 dwc_scan_descriptors(dw, dwc); 605 } 606 607 /* 608 * Re-enable interrupts. 609 */ 610 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); 611 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); 612 } 613 614 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) 615 { 616 struct dw_dma *dw = dev_id; 617 u32 status = dma_readl(dw, STATUS_INT); 618 619 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); 620 621 /* Check if we have any interrupt from the DMAC */ 622 if (!status) 623 return IRQ_NONE; 624 625 /* 626 * Just disable the interrupts. We'll turn them back on in the 627 * softirq handler. 628 */ 629 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 630 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 631 632 status = dma_readl(dw, STATUS_INT); 633 if (status) { 634 dev_err(dw->dma.dev, 635 "BUG: Unexpected interrupts pending: 0x%x\n", 636 status); 637 638 /* Try to recover */ 639 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); 640 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); 641 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); 642 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); 643 } 644 645 tasklet_schedule(&dw->tasklet); 646 647 return IRQ_HANDLED; 648 } 649 650 /*----------------------------------------------------------------------*/ 651 652 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) 653 { 654 struct dw_desc *desc = txd_to_dw_desc(tx); 655 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); 656 dma_cookie_t cookie; 657 unsigned long flags; 658 659 spin_lock_irqsave(&dwc->lock, flags); 660 cookie = dma_cookie_assign(tx); 661 662 /* 663 * REVISIT: We should attempt to chain as many descriptors as 664 * possible, perhaps even appending to those already submitted 665 * for DMA. But this is hard to do in a race-free manner. 666 */ 667 668 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); 669 list_add_tail(&desc->desc_node, &dwc->queue); 670 671 spin_unlock_irqrestore(&dwc->lock, flags); 672 673 return cookie; 674 } 675 676 static struct dma_async_tx_descriptor * 677 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 678 size_t len, unsigned long flags) 679 { 680 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 681 struct dw_dma *dw = to_dw_dma(chan->device); 682 struct dw_desc *desc; 683 struct dw_desc *first; 684 struct dw_desc *prev; 685 size_t xfer_count; 686 size_t offset; 687 unsigned int src_width; 688 unsigned int dst_width; 689 unsigned int data_width; 690 u32 ctllo; 691 692 dev_vdbg(chan2dev(chan), 693 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, 694 &dest, &src, len, flags); 695 696 if (unlikely(!len)) { 697 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); 698 return NULL; 699 } 700 701 dwc->direction = DMA_MEM_TO_MEM; 702 703 data_width = min_t(unsigned int, dw->data_width[dwc->src_master], 704 dw->data_width[dwc->dst_master]); 705 706 src_width = dst_width = min_t(unsigned int, data_width, 707 dwc_fast_fls(src | dest | len)); 708 709 ctllo = DWC_DEFAULT_CTLLO(chan) 710 | DWC_CTLL_DST_WIDTH(dst_width) 711 | DWC_CTLL_SRC_WIDTH(src_width) 712 | DWC_CTLL_DST_INC 713 | DWC_CTLL_SRC_INC 714 | DWC_CTLL_FC_M2M; 715 prev = first = NULL; 716 717 for (offset = 0; offset < len; offset += xfer_count << src_width) { 718 xfer_count = min_t(size_t, (len - offset) >> src_width, 719 dwc->block_size); 720 721 desc = dwc_desc_get(dwc); 722 if (!desc) 723 goto err_desc_get; 724 725 desc->lli.sar = src + offset; 726 desc->lli.dar = dest + offset; 727 desc->lli.ctllo = ctllo; 728 desc->lli.ctlhi = xfer_count; 729 desc->len = xfer_count << src_width; 730 731 if (!first) { 732 first = desc; 733 } else { 734 prev->lli.llp = desc->txd.phys; 735 list_add_tail(&desc->desc_node, 736 &first->tx_list); 737 } 738 prev = desc; 739 } 740 741 if (flags & DMA_PREP_INTERRUPT) 742 /* Trigger interrupt after last block */ 743 prev->lli.ctllo |= DWC_CTLL_INT_EN; 744 745 prev->lli.llp = 0; 746 first->txd.flags = flags; 747 first->total_len = len; 748 749 return &first->txd; 750 751 err_desc_get: 752 dwc_desc_put(dwc, first); 753 return NULL; 754 } 755 756 static struct dma_async_tx_descriptor * 757 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 758 unsigned int sg_len, enum dma_transfer_direction direction, 759 unsigned long flags, void *context) 760 { 761 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 762 struct dw_dma *dw = to_dw_dma(chan->device); 763 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 764 struct dw_desc *prev; 765 struct dw_desc *first; 766 u32 ctllo; 767 dma_addr_t reg; 768 unsigned int reg_width; 769 unsigned int mem_width; 770 unsigned int data_width; 771 unsigned int i; 772 struct scatterlist *sg; 773 size_t total_len = 0; 774 775 dev_vdbg(chan2dev(chan), "%s\n", __func__); 776 777 if (unlikely(!is_slave_direction(direction) || !sg_len)) 778 return NULL; 779 780 dwc->direction = direction; 781 782 prev = first = NULL; 783 784 switch (direction) { 785 case DMA_MEM_TO_DEV: 786 reg_width = __fls(sconfig->dst_addr_width); 787 reg = sconfig->dst_addr; 788 ctllo = (DWC_DEFAULT_CTLLO(chan) 789 | DWC_CTLL_DST_WIDTH(reg_width) 790 | DWC_CTLL_DST_FIX 791 | DWC_CTLL_SRC_INC); 792 793 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 794 DWC_CTLL_FC(DW_DMA_FC_D_M2P); 795 796 data_width = dw->data_width[dwc->src_master]; 797 798 for_each_sg(sgl, sg, sg_len, i) { 799 struct dw_desc *desc; 800 u32 len, dlen, mem; 801 802 mem = sg_dma_address(sg); 803 len = sg_dma_len(sg); 804 805 mem_width = min_t(unsigned int, 806 data_width, dwc_fast_fls(mem | len)); 807 808 slave_sg_todev_fill_desc: 809 desc = dwc_desc_get(dwc); 810 if (!desc) { 811 dev_err(chan2dev(chan), 812 "not enough descriptors available\n"); 813 goto err_desc_get; 814 } 815 816 desc->lli.sar = mem; 817 desc->lli.dar = reg; 818 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); 819 if ((len >> mem_width) > dwc->block_size) { 820 dlen = dwc->block_size << mem_width; 821 mem += dlen; 822 len -= dlen; 823 } else { 824 dlen = len; 825 len = 0; 826 } 827 828 desc->lli.ctlhi = dlen >> mem_width; 829 desc->len = dlen; 830 831 if (!first) { 832 first = desc; 833 } else { 834 prev->lli.llp = desc->txd.phys; 835 list_add_tail(&desc->desc_node, 836 &first->tx_list); 837 } 838 prev = desc; 839 total_len += dlen; 840 841 if (len) 842 goto slave_sg_todev_fill_desc; 843 } 844 break; 845 case DMA_DEV_TO_MEM: 846 reg_width = __fls(sconfig->src_addr_width); 847 reg = sconfig->src_addr; 848 ctllo = (DWC_DEFAULT_CTLLO(chan) 849 | DWC_CTLL_SRC_WIDTH(reg_width) 850 | DWC_CTLL_DST_INC 851 | DWC_CTLL_SRC_FIX); 852 853 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 854 DWC_CTLL_FC(DW_DMA_FC_D_P2M); 855 856 data_width = dw->data_width[dwc->dst_master]; 857 858 for_each_sg(sgl, sg, sg_len, i) { 859 struct dw_desc *desc; 860 u32 len, dlen, mem; 861 862 mem = sg_dma_address(sg); 863 len = sg_dma_len(sg); 864 865 mem_width = min_t(unsigned int, 866 data_width, dwc_fast_fls(mem | len)); 867 868 slave_sg_fromdev_fill_desc: 869 desc = dwc_desc_get(dwc); 870 if (!desc) { 871 dev_err(chan2dev(chan), 872 "not enough descriptors available\n"); 873 goto err_desc_get; 874 } 875 876 desc->lli.sar = reg; 877 desc->lli.dar = mem; 878 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); 879 if ((len >> reg_width) > dwc->block_size) { 880 dlen = dwc->block_size << reg_width; 881 mem += dlen; 882 len -= dlen; 883 } else { 884 dlen = len; 885 len = 0; 886 } 887 desc->lli.ctlhi = dlen >> reg_width; 888 desc->len = dlen; 889 890 if (!first) { 891 first = desc; 892 } else { 893 prev->lli.llp = desc->txd.phys; 894 list_add_tail(&desc->desc_node, 895 &first->tx_list); 896 } 897 prev = desc; 898 total_len += dlen; 899 900 if (len) 901 goto slave_sg_fromdev_fill_desc; 902 } 903 break; 904 default: 905 return NULL; 906 } 907 908 if (flags & DMA_PREP_INTERRUPT) 909 /* Trigger interrupt after last block */ 910 prev->lli.ctllo |= DWC_CTLL_INT_EN; 911 912 prev->lli.llp = 0; 913 first->total_len = total_len; 914 915 return &first->txd; 916 917 err_desc_get: 918 dwc_desc_put(dwc, first); 919 return NULL; 920 } 921 922 bool dw_dma_filter(struct dma_chan *chan, void *param) 923 { 924 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 925 struct dw_dma_slave *dws = param; 926 927 if (!dws || dws->dma_dev != chan->device->dev) 928 return false; 929 930 /* We have to copy data since dws can be temporary storage */ 931 932 dwc->src_id = dws->src_id; 933 dwc->dst_id = dws->dst_id; 934 935 dwc->src_master = dws->src_master; 936 dwc->dst_master = dws->dst_master; 937 938 return true; 939 } 940 EXPORT_SYMBOL_GPL(dw_dma_filter); 941 942 /* 943 * Fix sconfig's burst size according to dw_dmac. We need to convert them as: 944 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. 945 * 946 * NOTE: burst size 2 is not supported by controller. 947 * 948 * This can be done by finding least significant bit set: n & (n - 1) 949 */ 950 static inline void convert_burst(u32 *maxburst) 951 { 952 if (*maxburst > 1) 953 *maxburst = fls(*maxburst) - 2; 954 else 955 *maxburst = 0; 956 } 957 958 static int 959 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) 960 { 961 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 962 963 /* Check if chan will be configured for slave transfers */ 964 if (!is_slave_direction(sconfig->direction)) 965 return -EINVAL; 966 967 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); 968 dwc->direction = sconfig->direction; 969 970 convert_burst(&dwc->dma_sconfig.src_maxburst); 971 convert_burst(&dwc->dma_sconfig.dst_maxburst); 972 973 return 0; 974 } 975 976 static inline void dwc_chan_pause(struct dw_dma_chan *dwc) 977 { 978 u32 cfglo = channel_readl(dwc, CFG_LO); 979 unsigned int count = 20; /* timeout iterations */ 980 981 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); 982 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) 983 udelay(2); 984 985 dwc->paused = true; 986 } 987 988 static inline void dwc_chan_resume(struct dw_dma_chan *dwc) 989 { 990 u32 cfglo = channel_readl(dwc, CFG_LO); 991 992 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); 993 994 dwc->paused = false; 995 } 996 997 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 998 unsigned long arg) 999 { 1000 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1001 struct dw_dma *dw = to_dw_dma(chan->device); 1002 struct dw_desc *desc, *_desc; 1003 unsigned long flags; 1004 LIST_HEAD(list); 1005 1006 if (cmd == DMA_PAUSE) { 1007 spin_lock_irqsave(&dwc->lock, flags); 1008 1009 dwc_chan_pause(dwc); 1010 1011 spin_unlock_irqrestore(&dwc->lock, flags); 1012 } else if (cmd == DMA_RESUME) { 1013 if (!dwc->paused) 1014 return 0; 1015 1016 spin_lock_irqsave(&dwc->lock, flags); 1017 1018 dwc_chan_resume(dwc); 1019 1020 spin_unlock_irqrestore(&dwc->lock, flags); 1021 } else if (cmd == DMA_TERMINATE_ALL) { 1022 spin_lock_irqsave(&dwc->lock, flags); 1023 1024 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 1025 1026 dwc_chan_disable(dw, dwc); 1027 1028 dwc_chan_resume(dwc); 1029 1030 /* active_list entries will end up before queued entries */ 1031 list_splice_init(&dwc->queue, &list); 1032 list_splice_init(&dwc->active_list, &list); 1033 1034 spin_unlock_irqrestore(&dwc->lock, flags); 1035 1036 /* Flush all pending and queued descriptors */ 1037 list_for_each_entry_safe(desc, _desc, &list, desc_node) 1038 dwc_descriptor_complete(dwc, desc, false); 1039 } else if (cmd == DMA_SLAVE_CONFIG) { 1040 return set_runtime_config(chan, (struct dma_slave_config *)arg); 1041 } else { 1042 return -ENXIO; 1043 } 1044 1045 return 0; 1046 } 1047 1048 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) 1049 { 1050 unsigned long flags; 1051 u32 residue; 1052 1053 spin_lock_irqsave(&dwc->lock, flags); 1054 1055 residue = dwc->residue; 1056 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) 1057 residue -= dwc_get_sent(dwc); 1058 1059 spin_unlock_irqrestore(&dwc->lock, flags); 1060 return residue; 1061 } 1062 1063 static enum dma_status 1064 dwc_tx_status(struct dma_chan *chan, 1065 dma_cookie_t cookie, 1066 struct dma_tx_state *txstate) 1067 { 1068 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1069 enum dma_status ret; 1070 1071 ret = dma_cookie_status(chan, cookie, txstate); 1072 if (ret == DMA_COMPLETE) 1073 return ret; 1074 1075 dwc_scan_descriptors(to_dw_dma(chan->device), dwc); 1076 1077 ret = dma_cookie_status(chan, cookie, txstate); 1078 if (ret != DMA_COMPLETE) 1079 dma_set_residue(txstate, dwc_get_residue(dwc)); 1080 1081 if (dwc->paused && ret == DMA_IN_PROGRESS) 1082 return DMA_PAUSED; 1083 1084 return ret; 1085 } 1086 1087 static void dwc_issue_pending(struct dma_chan *chan) 1088 { 1089 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1090 unsigned long flags; 1091 1092 spin_lock_irqsave(&dwc->lock, flags); 1093 if (list_empty(&dwc->active_list)) 1094 dwc_dostart_first_queued(dwc); 1095 spin_unlock_irqrestore(&dwc->lock, flags); 1096 } 1097 1098 /*----------------------------------------------------------------------*/ 1099 1100 static void dw_dma_off(struct dw_dma *dw) 1101 { 1102 int i; 1103 1104 dma_writel(dw, CFG, 0); 1105 1106 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 1107 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); 1108 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); 1109 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 1110 1111 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) 1112 cpu_relax(); 1113 1114 for (i = 0; i < dw->dma.chancnt; i++) 1115 dw->chan[i].initialized = false; 1116 } 1117 1118 static void dw_dma_on(struct dw_dma *dw) 1119 { 1120 dma_writel(dw, CFG, DW_CFG_DMA_EN); 1121 } 1122 1123 static int dwc_alloc_chan_resources(struct dma_chan *chan) 1124 { 1125 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1126 struct dw_dma *dw = to_dw_dma(chan->device); 1127 struct dw_desc *desc; 1128 int i; 1129 unsigned long flags; 1130 1131 dev_vdbg(chan2dev(chan), "%s\n", __func__); 1132 1133 /* ASSERT: channel is idle */ 1134 if (dma_readl(dw, CH_EN) & dwc->mask) { 1135 dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); 1136 return -EIO; 1137 } 1138 1139 dma_cookie_init(chan); 1140 1141 /* 1142 * NOTE: some controllers may have additional features that we 1143 * need to initialize here, like "scatter-gather" (which 1144 * doesn't mean what you think it means), and status writeback. 1145 */ 1146 1147 /* Enable controller here if needed */ 1148 if (!dw->in_use) 1149 dw_dma_on(dw); 1150 dw->in_use |= dwc->mask; 1151 1152 spin_lock_irqsave(&dwc->lock, flags); 1153 i = dwc->descs_allocated; 1154 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { 1155 dma_addr_t phys; 1156 1157 spin_unlock_irqrestore(&dwc->lock, flags); 1158 1159 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); 1160 if (!desc) 1161 goto err_desc_alloc; 1162 1163 memset(desc, 0, sizeof(struct dw_desc)); 1164 1165 INIT_LIST_HEAD(&desc->tx_list); 1166 dma_async_tx_descriptor_init(&desc->txd, chan); 1167 desc->txd.tx_submit = dwc_tx_submit; 1168 desc->txd.flags = DMA_CTRL_ACK; 1169 desc->txd.phys = phys; 1170 1171 dwc_desc_put(dwc, desc); 1172 1173 spin_lock_irqsave(&dwc->lock, flags); 1174 i = ++dwc->descs_allocated; 1175 } 1176 1177 spin_unlock_irqrestore(&dwc->lock, flags); 1178 1179 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); 1180 1181 return i; 1182 1183 err_desc_alloc: 1184 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); 1185 1186 return i; 1187 } 1188 1189 static void dwc_free_chan_resources(struct dma_chan *chan) 1190 { 1191 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1192 struct dw_dma *dw = to_dw_dma(chan->device); 1193 struct dw_desc *desc, *_desc; 1194 unsigned long flags; 1195 LIST_HEAD(list); 1196 1197 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, 1198 dwc->descs_allocated); 1199 1200 /* ASSERT: channel is idle */ 1201 BUG_ON(!list_empty(&dwc->active_list)); 1202 BUG_ON(!list_empty(&dwc->queue)); 1203 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); 1204 1205 spin_lock_irqsave(&dwc->lock, flags); 1206 list_splice_init(&dwc->free_list, &list); 1207 dwc->descs_allocated = 0; 1208 dwc->initialized = false; 1209 1210 /* Disable interrupts */ 1211 channel_clear_bit(dw, MASK.XFER, dwc->mask); 1212 channel_clear_bit(dw, MASK.ERROR, dwc->mask); 1213 1214 spin_unlock_irqrestore(&dwc->lock, flags); 1215 1216 /* Disable controller in case it was a last user */ 1217 dw->in_use &= ~dwc->mask; 1218 if (!dw->in_use) 1219 dw_dma_off(dw); 1220 1221 list_for_each_entry_safe(desc, _desc, &list, desc_node) { 1222 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); 1223 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); 1224 } 1225 1226 dev_vdbg(chan2dev(chan), "%s: done\n", __func__); 1227 } 1228 1229 /* --------------------- Cyclic DMA API extensions -------------------- */ 1230 1231 /** 1232 * dw_dma_cyclic_start - start the cyclic DMA transfer 1233 * @chan: the DMA channel to start 1234 * 1235 * Must be called with soft interrupts disabled. Returns zero on success or 1236 * -errno on failure. 1237 */ 1238 int dw_dma_cyclic_start(struct dma_chan *chan) 1239 { 1240 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1241 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1242 unsigned long flags; 1243 1244 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { 1245 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); 1246 return -ENODEV; 1247 } 1248 1249 spin_lock_irqsave(&dwc->lock, flags); 1250 1251 /* Assert channel is idle */ 1252 if (dma_readl(dw, CH_EN) & dwc->mask) { 1253 dev_err(chan2dev(&dwc->chan), 1254 "BUG: Attempted to start non-idle channel\n"); 1255 dwc_dump_chan_regs(dwc); 1256 spin_unlock_irqrestore(&dwc->lock, flags); 1257 return -EBUSY; 1258 } 1259 1260 dma_writel(dw, CLEAR.ERROR, dwc->mask); 1261 dma_writel(dw, CLEAR.XFER, dwc->mask); 1262 1263 /* Setup DMAC channel registers */ 1264 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); 1265 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 1266 channel_writel(dwc, CTL_HI, 0); 1267 1268 channel_set_bit(dw, CH_EN, dwc->mask); 1269 1270 spin_unlock_irqrestore(&dwc->lock, flags); 1271 1272 return 0; 1273 } 1274 EXPORT_SYMBOL(dw_dma_cyclic_start); 1275 1276 /** 1277 * dw_dma_cyclic_stop - stop the cyclic DMA transfer 1278 * @chan: the DMA channel to stop 1279 * 1280 * Must be called with soft interrupts disabled. 1281 */ 1282 void dw_dma_cyclic_stop(struct dma_chan *chan) 1283 { 1284 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1285 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1286 unsigned long flags; 1287 1288 spin_lock_irqsave(&dwc->lock, flags); 1289 1290 dwc_chan_disable(dw, dwc); 1291 1292 spin_unlock_irqrestore(&dwc->lock, flags); 1293 } 1294 EXPORT_SYMBOL(dw_dma_cyclic_stop); 1295 1296 /** 1297 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer 1298 * @chan: the DMA channel to prepare 1299 * @buf_addr: physical DMA address where the buffer starts 1300 * @buf_len: total number of bytes for the entire buffer 1301 * @period_len: number of bytes for each period 1302 * @direction: transfer direction, to or from device 1303 * 1304 * Must be called before trying to start the transfer. Returns a valid struct 1305 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. 1306 */ 1307 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 1308 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 1309 enum dma_transfer_direction direction) 1310 { 1311 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1312 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 1313 struct dw_cyclic_desc *cdesc; 1314 struct dw_cyclic_desc *retval = NULL; 1315 struct dw_desc *desc; 1316 struct dw_desc *last = NULL; 1317 unsigned long was_cyclic; 1318 unsigned int reg_width; 1319 unsigned int periods; 1320 unsigned int i; 1321 unsigned long flags; 1322 1323 spin_lock_irqsave(&dwc->lock, flags); 1324 if (dwc->nollp) { 1325 spin_unlock_irqrestore(&dwc->lock, flags); 1326 dev_dbg(chan2dev(&dwc->chan), 1327 "channel doesn't support LLP transfers\n"); 1328 return ERR_PTR(-EINVAL); 1329 } 1330 1331 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { 1332 spin_unlock_irqrestore(&dwc->lock, flags); 1333 dev_dbg(chan2dev(&dwc->chan), 1334 "queue and/or active list are not empty\n"); 1335 return ERR_PTR(-EBUSY); 1336 } 1337 1338 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1339 spin_unlock_irqrestore(&dwc->lock, flags); 1340 if (was_cyclic) { 1341 dev_dbg(chan2dev(&dwc->chan), 1342 "channel already prepared for cyclic DMA\n"); 1343 return ERR_PTR(-EBUSY); 1344 } 1345 1346 retval = ERR_PTR(-EINVAL); 1347 1348 if (unlikely(!is_slave_direction(direction))) 1349 goto out_err; 1350 1351 dwc->direction = direction; 1352 1353 if (direction == DMA_MEM_TO_DEV) 1354 reg_width = __ffs(sconfig->dst_addr_width); 1355 else 1356 reg_width = __ffs(sconfig->src_addr_width); 1357 1358 periods = buf_len / period_len; 1359 1360 /* Check for too big/unaligned periods and unaligned DMA buffer. */ 1361 if (period_len > (dwc->block_size << reg_width)) 1362 goto out_err; 1363 if (unlikely(period_len & ((1 << reg_width) - 1))) 1364 goto out_err; 1365 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 1366 goto out_err; 1367 1368 retval = ERR_PTR(-ENOMEM); 1369 1370 if (periods > NR_DESCS_PER_CHANNEL) 1371 goto out_err; 1372 1373 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); 1374 if (!cdesc) 1375 goto out_err; 1376 1377 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); 1378 if (!cdesc->desc) 1379 goto out_err_alloc; 1380 1381 for (i = 0; i < periods; i++) { 1382 desc = dwc_desc_get(dwc); 1383 if (!desc) 1384 goto out_err_desc_get; 1385 1386 switch (direction) { 1387 case DMA_MEM_TO_DEV: 1388 desc->lli.dar = sconfig->dst_addr; 1389 desc->lli.sar = buf_addr + (period_len * i); 1390 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) 1391 | DWC_CTLL_DST_WIDTH(reg_width) 1392 | DWC_CTLL_SRC_WIDTH(reg_width) 1393 | DWC_CTLL_DST_FIX 1394 | DWC_CTLL_SRC_INC 1395 | DWC_CTLL_INT_EN); 1396 1397 desc->lli.ctllo |= sconfig->device_fc ? 1398 DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 1399 DWC_CTLL_FC(DW_DMA_FC_D_M2P); 1400 1401 break; 1402 case DMA_DEV_TO_MEM: 1403 desc->lli.dar = buf_addr + (period_len * i); 1404 desc->lli.sar = sconfig->src_addr; 1405 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) 1406 | DWC_CTLL_SRC_WIDTH(reg_width) 1407 | DWC_CTLL_DST_WIDTH(reg_width) 1408 | DWC_CTLL_DST_INC 1409 | DWC_CTLL_SRC_FIX 1410 | DWC_CTLL_INT_EN); 1411 1412 desc->lli.ctllo |= sconfig->device_fc ? 1413 DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 1414 DWC_CTLL_FC(DW_DMA_FC_D_P2M); 1415 1416 break; 1417 default: 1418 break; 1419 } 1420 1421 desc->lli.ctlhi = (period_len >> reg_width); 1422 cdesc->desc[i] = desc; 1423 1424 if (last) 1425 last->lli.llp = desc->txd.phys; 1426 1427 last = desc; 1428 } 1429 1430 /* Let's make a cyclic list */ 1431 last->lli.llp = cdesc->desc[0]->txd.phys; 1432 1433 dev_dbg(chan2dev(&dwc->chan), 1434 "cyclic prepared buf %pad len %zu period %zu periods %d\n", 1435 &buf_addr, buf_len, period_len, periods); 1436 1437 cdesc->periods = periods; 1438 dwc->cdesc = cdesc; 1439 1440 return cdesc; 1441 1442 out_err_desc_get: 1443 while (i--) 1444 dwc_desc_put(dwc, cdesc->desc[i]); 1445 out_err_alloc: 1446 kfree(cdesc); 1447 out_err: 1448 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1449 return (struct dw_cyclic_desc *)retval; 1450 } 1451 EXPORT_SYMBOL(dw_dma_cyclic_prep); 1452 1453 /** 1454 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer 1455 * @chan: the DMA channel to free 1456 */ 1457 void dw_dma_cyclic_free(struct dma_chan *chan) 1458 { 1459 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1460 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1461 struct dw_cyclic_desc *cdesc = dwc->cdesc; 1462 int i; 1463 unsigned long flags; 1464 1465 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); 1466 1467 if (!cdesc) 1468 return; 1469 1470 spin_lock_irqsave(&dwc->lock, flags); 1471 1472 dwc_chan_disable(dw, dwc); 1473 1474 dma_writel(dw, CLEAR.ERROR, dwc->mask); 1475 dma_writel(dw, CLEAR.XFER, dwc->mask); 1476 1477 spin_unlock_irqrestore(&dwc->lock, flags); 1478 1479 for (i = 0; i < cdesc->periods; i++) 1480 dwc_desc_put(dwc, cdesc->desc[i]); 1481 1482 kfree(cdesc->desc); 1483 kfree(cdesc); 1484 1485 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1486 } 1487 EXPORT_SYMBOL(dw_dma_cyclic_free); 1488 1489 /*----------------------------------------------------------------------*/ 1490 1491 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) 1492 { 1493 struct dw_dma *dw; 1494 bool autocfg; 1495 unsigned int dw_params; 1496 unsigned int nr_channels; 1497 unsigned int max_blk_size = 0; 1498 int err; 1499 int i; 1500 1501 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); 1502 if (!dw) 1503 return -ENOMEM; 1504 1505 dw->regs = chip->regs; 1506 chip->dw = dw; 1507 1508 pm_runtime_get_sync(chip->dev); 1509 1510 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); 1511 autocfg = dw_params >> DW_PARAMS_EN & 0x1; 1512 1513 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); 1514 1515 if (!pdata && autocfg) { 1516 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); 1517 if (!pdata) { 1518 err = -ENOMEM; 1519 goto err_pdata; 1520 } 1521 1522 /* Fill platform data with the default values */ 1523 pdata->is_private = true; 1524 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; 1525 pdata->chan_priority = CHAN_PRIORITY_ASCENDING; 1526 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { 1527 err = -EINVAL; 1528 goto err_pdata; 1529 } 1530 1531 if (autocfg) 1532 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; 1533 else 1534 nr_channels = pdata->nr_channels; 1535 1536 dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan), 1537 GFP_KERNEL); 1538 if (!dw->chan) { 1539 err = -ENOMEM; 1540 goto err_pdata; 1541 } 1542 1543 /* Get hardware configuration parameters */ 1544 if (autocfg) { 1545 max_blk_size = dma_readl(dw, MAX_BLK_SIZE); 1546 1547 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; 1548 for (i = 0; i < dw->nr_masters; i++) { 1549 dw->data_width[i] = 1550 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; 1551 } 1552 } else { 1553 dw->nr_masters = pdata->nr_masters; 1554 memcpy(dw->data_width, pdata->data_width, 4); 1555 } 1556 1557 /* Calculate all channel mask before DMA setup */ 1558 dw->all_chan_mask = (1 << nr_channels) - 1; 1559 1560 /* Force dma off, just in case */ 1561 dw_dma_off(dw); 1562 1563 /* Disable BLOCK interrupts as well */ 1564 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 1565 1566 /* Create a pool of consistent memory blocks for hardware descriptors */ 1567 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, 1568 sizeof(struct dw_desc), 4, 0); 1569 if (!dw->desc_pool) { 1570 dev_err(chip->dev, "No memory for descriptors dma pool\n"); 1571 err = -ENOMEM; 1572 goto err_pdata; 1573 } 1574 1575 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); 1576 1577 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, 1578 "dw_dmac", dw); 1579 if (err) 1580 goto err_pdata; 1581 1582 INIT_LIST_HEAD(&dw->dma.channels); 1583 for (i = 0; i < nr_channels; i++) { 1584 struct dw_dma_chan *dwc = &dw->chan[i]; 1585 int r = nr_channels - i - 1; 1586 1587 dwc->chan.device = &dw->dma; 1588 dma_cookie_init(&dwc->chan); 1589 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) 1590 list_add_tail(&dwc->chan.device_node, 1591 &dw->dma.channels); 1592 else 1593 list_add(&dwc->chan.device_node, &dw->dma.channels); 1594 1595 /* 7 is highest priority & 0 is lowest. */ 1596 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) 1597 dwc->priority = r; 1598 else 1599 dwc->priority = i; 1600 1601 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; 1602 spin_lock_init(&dwc->lock); 1603 dwc->mask = 1 << i; 1604 1605 INIT_LIST_HEAD(&dwc->active_list); 1606 INIT_LIST_HEAD(&dwc->queue); 1607 INIT_LIST_HEAD(&dwc->free_list); 1608 1609 channel_clear_bit(dw, CH_EN, dwc->mask); 1610 1611 dwc->direction = DMA_TRANS_NONE; 1612 1613 /* Hardware configuration */ 1614 if (autocfg) { 1615 unsigned int dwc_params; 1616 void __iomem *addr = chip->regs + r * sizeof(u32); 1617 1618 dwc_params = dma_read_byaddr(addr, DWC_PARAMS); 1619 1620 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, 1621 dwc_params); 1622 1623 /* 1624 * Decode maximum block size for given channel. The 1625 * stored 4 bit value represents blocks from 0x00 for 3 1626 * up to 0x0a for 4095. 1627 */ 1628 dwc->block_size = 1629 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; 1630 dwc->nollp = 1631 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; 1632 } else { 1633 dwc->block_size = pdata->block_size; 1634 1635 /* Check if channel supports multi block transfer */ 1636 channel_writel(dwc, LLP, 0xfffffffc); 1637 dwc->nollp = 1638 (channel_readl(dwc, LLP) & 0xfffffffc) == 0; 1639 channel_writel(dwc, LLP, 0); 1640 } 1641 } 1642 1643 /* Clear all interrupts on all channels. */ 1644 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); 1645 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); 1646 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); 1647 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); 1648 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); 1649 1650 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 1651 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); 1652 if (pdata->is_private) 1653 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); 1654 dw->dma.dev = chip->dev; 1655 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; 1656 dw->dma.device_free_chan_resources = dwc_free_chan_resources; 1657 1658 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; 1659 1660 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; 1661 dw->dma.device_control = dwc_control; 1662 1663 dw->dma.device_tx_status = dwc_tx_status; 1664 dw->dma.device_issue_pending = dwc_issue_pending; 1665 1666 err = dma_async_device_register(&dw->dma); 1667 if (err) 1668 goto err_dma_register; 1669 1670 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", 1671 nr_channels); 1672 1673 pm_runtime_put_sync_suspend(chip->dev); 1674 1675 return 0; 1676 1677 err_dma_register: 1678 free_irq(chip->irq, dw); 1679 err_pdata: 1680 pm_runtime_put_sync_suspend(chip->dev); 1681 return err; 1682 } 1683 EXPORT_SYMBOL_GPL(dw_dma_probe); 1684 1685 int dw_dma_remove(struct dw_dma_chip *chip) 1686 { 1687 struct dw_dma *dw = chip->dw; 1688 struct dw_dma_chan *dwc, *_dwc; 1689 1690 pm_runtime_get_sync(chip->dev); 1691 1692 dw_dma_off(dw); 1693 dma_async_device_unregister(&dw->dma); 1694 1695 free_irq(chip->irq, dw); 1696 tasklet_kill(&dw->tasklet); 1697 1698 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, 1699 chan.device_node) { 1700 list_del(&dwc->chan.device_node); 1701 channel_clear_bit(dw, CH_EN, dwc->mask); 1702 } 1703 1704 pm_runtime_put_sync_suspend(chip->dev); 1705 return 0; 1706 } 1707 EXPORT_SYMBOL_GPL(dw_dma_remove); 1708 1709 int dw_dma_disable(struct dw_dma_chip *chip) 1710 { 1711 struct dw_dma *dw = chip->dw; 1712 1713 dw_dma_off(dw); 1714 return 0; 1715 } 1716 EXPORT_SYMBOL_GPL(dw_dma_disable); 1717 1718 int dw_dma_enable(struct dw_dma_chip *chip) 1719 { 1720 struct dw_dma *dw = chip->dw; 1721 1722 dw_dma_on(dw); 1723 return 0; 1724 } 1725 EXPORT_SYMBOL_GPL(dw_dma_enable); 1726 1727 MODULE_LICENSE("GPL v2"); 1728 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); 1729 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1730 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 1731