1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Cai Huoqing 4 * Synopsys DesignWare HDMA v0 reg 5 * 6 * Author: Cai Huoqing <cai.huoqing@linux.dev> 7 */ 8 9 #ifndef _DW_HDMA_V0_REGS_H 10 #define _DW_HDMA_V0_REGS_H 11 12 #include <linux/dmaengine.h> 13 14 #define HDMA_V0_MAX_NR_CH 8 15 #define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6) 16 #define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5) 17 #define HDMA_V0_LOCAL_STOP_INT_EN BIT(4) 18 #define HDMA_V0_REMOTE_STOP_INT_EN BIT(3) 19 #define HDMA_V0_ABORT_INT_MASK BIT(2) 20 #define HDMA_V0_STOP_INT_MASK BIT(0) 21 #define HDMA_V0_LINKLIST_EN BIT(0) 22 #define HDMA_V0_CONSUMER_CYCLE_STAT BIT(1) 23 #define HDMA_V0_CONSUMER_CYCLE_BIT BIT(0) 24 #define HDMA_V0_DOORBELL_START BIT(0) 25 #define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0) 26 27 struct dw_hdma_v0_ch_regs { 28 u32 ch_en; /* 0x0000 */ 29 u32 doorbell; /* 0x0004 */ 30 u32 prefetch; /* 0x0008 */ 31 u32 handshake; /* 0x000c */ 32 union { 33 u64 reg; /* 0x0010..0x0014 */ 34 struct { 35 u32 lsb; /* 0x0010 */ 36 u32 msb; /* 0x0014 */ 37 }; 38 } llp; 39 u32 cycle_sync; /* 0x0018 */ 40 u32 transfer_size; /* 0x001c */ 41 union { 42 u64 reg; /* 0x0020..0x0024 */ 43 struct { 44 u32 lsb; /* 0x0020 */ 45 u32 msb; /* 0x0024 */ 46 }; 47 } sar; 48 union { 49 u64 reg; /* 0x0028..0x002c */ 50 struct { 51 u32 lsb; /* 0x0028 */ 52 u32 msb; /* 0x002c */ 53 }; 54 } dar; 55 u32 watermark_en; /* 0x0030 */ 56 u32 control1; /* 0x0034 */ 57 u32 func_num; /* 0x0038 */ 58 u32 qos; /* 0x003c */ 59 u32 padding_1[16]; /* 0x0040..0x007c */ 60 u32 ch_stat; /* 0x0080 */ 61 u32 int_stat; /* 0x0084 */ 62 u32 int_setup; /* 0x0088 */ 63 u32 int_clear; /* 0x008c */ 64 union { 65 u64 reg; /* 0x0090..0x0094 */ 66 struct { 67 u32 lsb; /* 0x0090 */ 68 u32 msb; /* 0x0094 */ 69 }; 70 } msi_stop; 71 union { 72 u64 reg; /* 0x0098..0x009c */ 73 struct { 74 u32 lsb; /* 0x0098 */ 75 u32 msb; /* 0x009c */ 76 }; 77 } msi_watermark; 78 union { 79 u64 reg; /* 0x00a0..0x00a4 */ 80 struct { 81 u32 lsb; /* 0x00a0 */ 82 u32 msb; /* 0x00a4 */ 83 }; 84 } msi_abort; 85 u32 msi_msgdata; /* 0x00a8 */ 86 u32 padding_2[21]; /* 0x00ac..0x00fc */ 87 } __packed; 88 89 struct dw_hdma_v0_ch { 90 struct dw_hdma_v0_ch_regs wr; /* 0x0000 */ 91 struct dw_hdma_v0_ch_regs rd; /* 0x0100 */ 92 } __packed; 93 94 struct dw_hdma_v0_regs { 95 struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ 96 } __packed; 97 98 struct dw_hdma_v0_lli { 99 u32 control; 100 u32 transfer_size; 101 union { 102 u64 reg; 103 struct { 104 u32 lsb; 105 u32 msb; 106 }; 107 } sar; 108 union { 109 u64 reg; 110 struct { 111 u32 lsb; 112 u32 msb; 113 }; 114 } dar; 115 } __packed; 116 117 struct dw_hdma_v0_llp { 118 u32 control; 119 u32 reserved; 120 union { 121 u64 reg; 122 struct { 123 u32 lsb; 124 u32 msb; 125 }; 126 } llp; 127 } __packed; 128 129 #endif /* _DW_HDMA_V0_REGS_H */ 130