1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare eDMA PCIe driver 5 * 6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/device.h> 13 #include <linux/dma/edma.h> 14 #include <linux/pci-epf.h> 15 #include <linux/msi.h> 16 #include <linux/bitfield.h> 17 #include <linux/sizes.h> 18 19 #include "dw-edma-core.h" 20 21 /* Synopsys */ 22 #define DW_PCIE_SYNOPSYS_VSEC_DMA_ID 0x6 23 #define DW_PCIE_SYNOPSYS_VSEC_DMA_BAR GENMASK(10, 8) 24 #define DW_PCIE_SYNOPSYS_VSEC_DMA_MAP GENMASK(2, 0) 25 #define DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH GENMASK(9, 0) 26 #define DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH GENMASK(25, 16) 27 28 /* AMD MDB (Xilinx) specific defines */ 29 #define PCI_DEVICE_ID_XILINX_B054 0xb054 30 31 #define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6 32 #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 33 #define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) 34 #define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) 35 #define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) 36 #define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) 37 38 #define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH 0xc 39 #define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW 0x8 40 #define DW_PCIE_XILINX_MDB_INVALID_ADDR (~0ULL) 41 42 #define DW_PCIE_XILINX_MDB_LL_OFF_GAP 0x200000 43 #define DW_PCIE_XILINX_MDB_LL_SIZE 0x800 44 #define DW_PCIE_XILINX_MDB_DT_OFF_GAP 0x100000 45 #define DW_PCIE_XILINX_MDB_DT_SIZE 0x800 46 47 #define DW_BLOCK(a, b, c) \ 48 { \ 49 .bar = a, \ 50 .off = b, \ 51 .sz = c, \ 52 }, 53 54 struct dw_edma_block { 55 enum pci_barno bar; 56 off_t off; 57 size_t sz; 58 }; 59 60 struct dw_edma_pcie_data { 61 /* eDMA registers location */ 62 struct dw_edma_block rg; 63 /* eDMA memory linked list location */ 64 struct dw_edma_block ll_wr[EDMA_MAX_WR_CH]; 65 struct dw_edma_block ll_rd[EDMA_MAX_RD_CH]; 66 /* eDMA memory data location */ 67 struct dw_edma_block dt_wr[EDMA_MAX_WR_CH]; 68 struct dw_edma_block dt_rd[EDMA_MAX_RD_CH]; 69 /* Other */ 70 enum dw_edma_map_format mf; 71 u8 irqs; 72 u16 wr_ch_cnt; 73 u16 rd_ch_cnt; 74 u64 devmem_phys_off; 75 }; 76 77 static const struct dw_edma_pcie_data snps_edda_data = { 78 /* eDMA registers location */ 79 .rg.bar = BAR_0, 80 .rg.off = 0x00001000, /* 4 Kbytes */ 81 .rg.sz = 0x00002000, /* 8 Kbytes */ 82 /* eDMA memory linked list location */ 83 .ll_wr = { 84 /* Channel 0 - BAR 2, offset 0 Mbytes, size 2 Kbytes */ 85 DW_BLOCK(BAR_2, 0x00000000, 0x00000800) 86 /* Channel 1 - BAR 2, offset 2 Mbytes, size 2 Kbytes */ 87 DW_BLOCK(BAR_2, 0x00200000, 0x00000800) 88 }, 89 .ll_rd = { 90 /* Channel 0 - BAR 2, offset 4 Mbytes, size 2 Kbytes */ 91 DW_BLOCK(BAR_2, 0x00400000, 0x00000800) 92 /* Channel 1 - BAR 2, offset 6 Mbytes, size 2 Kbytes */ 93 DW_BLOCK(BAR_2, 0x00600000, 0x00000800) 94 }, 95 /* eDMA memory data location */ 96 .dt_wr = { 97 /* Channel 0 - BAR 2, offset 8 Mbytes, size 2 Kbytes */ 98 DW_BLOCK(BAR_2, 0x00800000, 0x00000800) 99 /* Channel 1 - BAR 2, offset 9 Mbytes, size 2 Kbytes */ 100 DW_BLOCK(BAR_2, 0x00900000, 0x00000800) 101 }, 102 .dt_rd = { 103 /* Channel 0 - BAR 2, offset 10 Mbytes, size 2 Kbytes */ 104 DW_BLOCK(BAR_2, 0x00a00000, 0x00000800) 105 /* Channel 1 - BAR 2, offset 11 Mbytes, size 2 Kbytes */ 106 DW_BLOCK(BAR_2, 0x00b00000, 0x00000800) 107 }, 108 /* Other */ 109 .mf = EDMA_MF_EDMA_UNROLL, 110 .irqs = 1, 111 .wr_ch_cnt = 2, 112 .rd_ch_cnt = 2, 113 }; 114 115 static const struct dw_edma_pcie_data xilinx_mdb_data = { 116 /* MDB registers location */ 117 .rg.bar = BAR_0, 118 .rg.off = SZ_4K, /* 4 Kbytes */ 119 .rg.sz = SZ_8K, /* 8 Kbytes */ 120 121 /* Other */ 122 .mf = EDMA_MF_HDMA_NATIVE, 123 .irqs = 1, 124 .wr_ch_cnt = 8, 125 .rd_ch_cnt = 8, 126 }; 127 128 static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, 129 enum pci_barno bar, off_t start_off, 130 off_t ll_off_gap, size_t ll_size, 131 off_t dt_off_gap, size_t dt_size) 132 { 133 u16 wr_ch = pdata->wr_ch_cnt; 134 u16 rd_ch = pdata->rd_ch_cnt; 135 off_t off; 136 u16 i; 137 138 off = start_off; 139 140 /* Write channel LL region */ 141 for (i = 0; i < wr_ch; i++) { 142 pdata->ll_wr[i].bar = bar; 143 pdata->ll_wr[i].off = off; 144 pdata->ll_wr[i].sz = ll_size; 145 off += ll_off_gap; 146 } 147 148 /* Read channel LL region */ 149 for (i = 0; i < rd_ch; i++) { 150 pdata->ll_rd[i].bar = bar; 151 pdata->ll_rd[i].off = off; 152 pdata->ll_rd[i].sz = ll_size; 153 off += ll_off_gap; 154 } 155 156 /* Write channel data region */ 157 for (i = 0; i < wr_ch; i++) { 158 pdata->dt_wr[i].bar = bar; 159 pdata->dt_wr[i].off = off; 160 pdata->dt_wr[i].sz = dt_size; 161 off += dt_off_gap; 162 } 163 164 /* Read channel data region */ 165 for (i = 0; i < rd_ch; i++) { 166 pdata->dt_rd[i].bar = bar; 167 pdata->dt_rd[i].off = off; 168 pdata->dt_rd[i].sz = dt_size; 169 off += dt_off_gap; 170 } 171 } 172 173 static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) 174 { 175 return pci_irq_vector(to_pci_dev(dev), nr); 176 } 177 178 static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) 179 { 180 struct pci_dev *pdev = to_pci_dev(dev); 181 struct pci_bus_region region; 182 struct resource res = { 183 .flags = IORESOURCE_MEM, 184 .start = cpu_addr, 185 .end = cpu_addr, 186 }; 187 188 pcibios_resource_to_bus(pdev->bus, ®ion, &res); 189 return region.start; 190 } 191 192 static const struct dw_edma_plat_ops dw_edma_pcie_plat_ops = { 193 .irq_vector = dw_edma_pcie_irq_vector, 194 .pci_address = dw_edma_pcie_address, 195 }; 196 197 static void dw_edma_pcie_get_synopsys_dma_data(struct pci_dev *pdev, 198 struct dw_edma_pcie_data *pdata) 199 { 200 u32 val, map; 201 u16 vsec; 202 u64 off; 203 204 vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS, 205 DW_PCIE_SYNOPSYS_VSEC_DMA_ID); 206 if (!vsec) 207 return; 208 209 pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); 210 if (PCI_VNDR_HEADER_REV(val) != 0x00 || 211 PCI_VNDR_HEADER_LEN(val) != 0x18) 212 return; 213 214 pci_dbg(pdev, "Detected Synopsys PCIe Vendor-Specific Extended Capability DMA\n"); 215 pci_read_config_dword(pdev, vsec + 0x8, &val); 216 map = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_MAP, val); 217 if (map != EDMA_MF_EDMA_LEGACY && 218 map != EDMA_MF_EDMA_UNROLL && 219 map != EDMA_MF_HDMA_COMPAT && 220 map != EDMA_MF_HDMA_NATIVE) 221 return; 222 223 pdata->mf = map; 224 pdata->rg.bar = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_BAR, val); 225 226 pci_read_config_dword(pdev, vsec + 0xc, &val); 227 pdata->wr_ch_cnt = min_t(u16, pdata->wr_ch_cnt, 228 FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH, val)); 229 pdata->rd_ch_cnt = min_t(u16, pdata->rd_ch_cnt, 230 FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH, val)); 231 232 pci_read_config_dword(pdev, vsec + 0x14, &val); 233 off = val; 234 pci_read_config_dword(pdev, vsec + 0x10, &val); 235 off <<= 32; 236 off |= val; 237 pdata->rg.off = off; 238 } 239 240 static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, 241 struct dw_edma_pcie_data *pdata) 242 { 243 u32 val, map; 244 u16 vsec; 245 u64 off; 246 247 pdata->devmem_phys_off = DW_PCIE_XILINX_MDB_INVALID_ADDR; 248 249 vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, 250 DW_PCIE_XILINX_MDB_VSEC_DMA_ID); 251 if (!vsec) 252 return; 253 254 pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); 255 if (PCI_VNDR_HEADER_REV(val) != 0x00 || 256 PCI_VNDR_HEADER_LEN(val) != 0x18) 257 return; 258 259 pci_dbg(pdev, "Detected Xilinx PCIe Vendor-Specific Extended Capability DMA\n"); 260 pci_read_config_dword(pdev, vsec + 0x8, &val); 261 map = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_MAP, val); 262 if (map != EDMA_MF_HDMA_NATIVE) 263 return; 264 265 pdata->mf = map; 266 pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); 267 268 pci_read_config_dword(pdev, vsec + 0xc, &val); 269 pdata->wr_ch_cnt = min(pdata->wr_ch_cnt, 270 FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); 271 pdata->rd_ch_cnt = min(pdata->rd_ch_cnt, 272 FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH, val)); 273 274 pci_read_config_dword(pdev, vsec + 0x14, &val); 275 off = val; 276 pci_read_config_dword(pdev, vsec + 0x10, &val); 277 off <<= 32; 278 off |= val; 279 pdata->rg.off = off; 280 281 vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, 282 DW_PCIE_XILINX_MDB_VSEC_ID); 283 if (!vsec) 284 return; 285 286 pci_read_config_dword(pdev, 287 vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH, 288 &val); 289 off = val; 290 pci_read_config_dword(pdev, 291 vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW, 292 &val); 293 off <<= 32; 294 off |= val; 295 pdata->devmem_phys_off = off; 296 } 297 298 static u64 dw_edma_get_phys_addr(struct pci_dev *pdev, 299 struct dw_edma_pcie_data *pdata, 300 enum pci_barno bar) 301 { 302 if (pdev->vendor == PCI_VENDOR_ID_XILINX) 303 return pdata->devmem_phys_off; 304 return pci_bus_address(pdev, bar); 305 } 306 307 static int dw_edma_pcie_probe(struct pci_dev *pdev, 308 const struct pci_device_id *pid) 309 { 310 struct dw_edma_pcie_data *pdata = (void *)pid->driver_data; 311 struct device *dev = &pdev->dev; 312 struct dw_edma_chip *chip; 313 int err, nr_irqs; 314 int i, mask; 315 bool non_ll = false; 316 317 struct dw_edma_pcie_data *vsec_data __free(kfree) = 318 kmalloc_obj(*vsec_data); 319 if (!vsec_data) 320 return -ENOMEM; 321 322 /* Enable PCI device */ 323 err = pcim_enable_device(pdev); 324 if (err) { 325 pci_err(pdev, "enabling device failed\n"); 326 return err; 327 } 328 329 memcpy(vsec_data, pdata, sizeof(struct dw_edma_pcie_data)); 330 331 /* 332 * Tries to find if exists a PCIe Vendor-Specific Extended Capability 333 * for the DMA, if one exists, then reconfigures it. 334 */ 335 dw_edma_pcie_get_synopsys_dma_data(pdev, vsec_data); 336 337 if (pdev->vendor == PCI_VENDOR_ID_XILINX) { 338 dw_edma_pcie_get_xilinx_dma_data(pdev, vsec_data); 339 340 /* 341 * There is no valid address found for the LL memory 342 * space on the device side. In the absence of LL base 343 * address use the non-LL mode or simple mode supported by 344 * the HDMA IP. 345 */ 346 if (vsec_data->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR) 347 non_ll = true; 348 349 /* 350 * Configure the channel LL and data blocks if number of 351 * channels enabled in VSEC capability are more than the 352 * channels configured in xilinx_mdb_data. 353 */ 354 if (!non_ll) 355 dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, 356 DW_PCIE_XILINX_MDB_LL_OFF_GAP, 357 DW_PCIE_XILINX_MDB_LL_SIZE, 358 DW_PCIE_XILINX_MDB_DT_OFF_GAP, 359 DW_PCIE_XILINX_MDB_DT_SIZE); 360 } 361 362 /* Mapping PCI BAR regions */ 363 mask = BIT(vsec_data->rg.bar); 364 for (i = 0; i < vsec_data->wr_ch_cnt; i++) { 365 mask |= BIT(vsec_data->ll_wr[i].bar); 366 mask |= BIT(vsec_data->dt_wr[i].bar); 367 } 368 for (i = 0; i < vsec_data->rd_ch_cnt; i++) { 369 mask |= BIT(vsec_data->ll_rd[i].bar); 370 mask |= BIT(vsec_data->dt_rd[i].bar); 371 } 372 err = pcim_iomap_regions(pdev, mask, pci_name(pdev)); 373 if (err) { 374 pci_err(pdev, "eDMA BAR I/O remapping failed\n"); 375 return err; 376 } 377 378 pci_set_master(pdev); 379 380 /* DMA configuration */ 381 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 382 if (err) { 383 pci_err(pdev, "DMA mask 64 set failed\n"); 384 return err; 385 } 386 387 /* Data structure allocation */ 388 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 389 if (!chip) 390 return -ENOMEM; 391 392 /* IRQs allocation */ 393 nr_irqs = pci_alloc_irq_vectors(pdev, 1, vsec_data->irqs, 394 PCI_IRQ_MSI | PCI_IRQ_MSIX); 395 if (nr_irqs < 1) { 396 pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n", 397 nr_irqs); 398 return -EPERM; 399 } 400 401 /* Data structure initialization */ 402 chip->dev = dev; 403 404 chip->mf = vsec_data->mf; 405 chip->nr_irqs = nr_irqs; 406 chip->ops = &dw_edma_pcie_plat_ops; 407 chip->cfg_non_ll = non_ll; 408 409 chip->ll_wr_cnt = vsec_data->wr_ch_cnt; 410 chip->ll_rd_cnt = vsec_data->rd_ch_cnt; 411 412 chip->reg_base = pcim_iomap_table(pdev)[vsec_data->rg.bar]; 413 if (!chip->reg_base) 414 return -ENOMEM; 415 416 for (i = 0; i < chip->ll_wr_cnt && !non_ll; i++) { 417 struct dw_edma_region *ll_region = &chip->ll_region_wr[i]; 418 struct dw_edma_region *dt_region = &chip->dt_region_wr[i]; 419 struct dw_edma_block *ll_block = &vsec_data->ll_wr[i]; 420 struct dw_edma_block *dt_block = &vsec_data->dt_wr[i]; 421 422 ll_region->vaddr.io = pcim_iomap_table(pdev)[ll_block->bar]; 423 if (!ll_region->vaddr.io) 424 return -ENOMEM; 425 426 ll_region->vaddr.io += ll_block->off; 427 ll_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data, 428 ll_block->bar); 429 ll_region->paddr += ll_block->off; 430 ll_region->sz = ll_block->sz; 431 432 dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar]; 433 if (!dt_region->vaddr.io) 434 return -ENOMEM; 435 436 dt_region->vaddr.io += dt_block->off; 437 dt_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data, 438 dt_block->bar); 439 dt_region->paddr += dt_block->off; 440 dt_region->sz = dt_block->sz; 441 } 442 443 for (i = 0; i < chip->ll_rd_cnt && !non_ll; i++) { 444 struct dw_edma_region *ll_region = &chip->ll_region_rd[i]; 445 struct dw_edma_region *dt_region = &chip->dt_region_rd[i]; 446 struct dw_edma_block *ll_block = &vsec_data->ll_rd[i]; 447 struct dw_edma_block *dt_block = &vsec_data->dt_rd[i]; 448 449 ll_region->vaddr.io = pcim_iomap_table(pdev)[ll_block->bar]; 450 if (!ll_region->vaddr.io) 451 return -ENOMEM; 452 453 ll_region->vaddr.io += ll_block->off; 454 ll_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data, 455 ll_block->bar); 456 ll_region->paddr += ll_block->off; 457 ll_region->sz = ll_block->sz; 458 459 dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar]; 460 if (!dt_region->vaddr.io) 461 return -ENOMEM; 462 463 dt_region->vaddr.io += dt_block->off; 464 dt_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data, 465 dt_block->bar); 466 dt_region->paddr += dt_block->off; 467 dt_region->sz = dt_block->sz; 468 } 469 470 /* Debug info */ 471 if (chip->mf == EDMA_MF_EDMA_LEGACY) 472 pci_dbg(pdev, "Version:\teDMA Port Logic (0x%x)\n", chip->mf); 473 else if (chip->mf == EDMA_MF_EDMA_UNROLL) 474 pci_dbg(pdev, "Version:\teDMA Unroll (0x%x)\n", chip->mf); 475 else if (chip->mf == EDMA_MF_HDMA_COMPAT) 476 pci_dbg(pdev, "Version:\tHDMA Compatible (0x%x)\n", chip->mf); 477 else if (chip->mf == EDMA_MF_HDMA_NATIVE) 478 pci_dbg(pdev, "Version:\tHDMA Native (0x%x)\n", chip->mf); 479 else 480 pci_dbg(pdev, "Version:\tUnknown (0x%x)\n", chip->mf); 481 482 pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p)\n", 483 vsec_data->rg.bar, vsec_data->rg.off, vsec_data->rg.sz, 484 chip->reg_base); 485 486 487 for (i = 0; i < chip->ll_wr_cnt; i++) { 488 pci_dbg(pdev, "L. List:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 489 i, vsec_data->ll_wr[i].bar, 490 vsec_data->ll_wr[i].off, chip->ll_region_wr[i].sz, 491 chip->ll_region_wr[i].vaddr.io, &chip->ll_region_wr[i].paddr); 492 493 pci_dbg(pdev, "Data:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 494 i, vsec_data->dt_wr[i].bar, 495 vsec_data->dt_wr[i].off, chip->dt_region_wr[i].sz, 496 chip->dt_region_wr[i].vaddr.io, &chip->dt_region_wr[i].paddr); 497 } 498 499 for (i = 0; i < chip->ll_rd_cnt; i++) { 500 pci_dbg(pdev, "L. List:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 501 i, vsec_data->ll_rd[i].bar, 502 vsec_data->ll_rd[i].off, chip->ll_region_rd[i].sz, 503 chip->ll_region_rd[i].vaddr.io, &chip->ll_region_rd[i].paddr); 504 505 pci_dbg(pdev, "Data:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 506 i, vsec_data->dt_rd[i].bar, 507 vsec_data->dt_rd[i].off, chip->dt_region_rd[i].sz, 508 chip->dt_region_rd[i].vaddr.io, &chip->dt_region_rd[i].paddr); 509 } 510 511 pci_dbg(pdev, "Nr. IRQs:\t%u\n", chip->nr_irqs); 512 513 /* Validating if PCI interrupts were enabled */ 514 if (!pci_dev_msi_enabled(pdev)) { 515 pci_err(pdev, "enable interrupt failed\n"); 516 return -EPERM; 517 } 518 519 /* Starting eDMA driver */ 520 err = dw_edma_probe(chip); 521 if (err) { 522 pci_err(pdev, "eDMA probe failed\n"); 523 return err; 524 } 525 526 /* Saving data structure reference */ 527 pci_set_drvdata(pdev, chip); 528 529 return 0; 530 } 531 532 static void dw_edma_pcie_remove(struct pci_dev *pdev) 533 { 534 struct dw_edma_chip *chip = pci_get_drvdata(pdev); 535 int err; 536 537 /* Stopping eDMA driver */ 538 err = dw_edma_remove(chip); 539 if (err) 540 pci_warn(pdev, "can't remove device properly: %d\n", err); 541 542 /* Freeing IRQs */ 543 pci_free_irq_vectors(pdev); 544 } 545 546 static const struct pci_device_id dw_edma_pcie_id_table[] = { 547 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) }, 548 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054), 549 (kernel_ulong_t)&xilinx_mdb_data }, 550 { } 551 }; 552 MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table); 553 554 static struct pci_driver dw_edma_pcie_driver = { 555 .name = "dw-edma-pcie", 556 .id_table = dw_edma_pcie_id_table, 557 .probe = dw_edma_pcie_probe, 558 .remove = dw_edma_pcie_remove, 559 }; 560 561 module_pci_driver(dw_edma_pcie_driver); 562 563 MODULE_LICENSE("GPL v2"); 564 MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver"); 565 MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>"); 566