xref: /linux/drivers/dma/amd/ae4dma/ae4dma.h (revision 86f5536004a61a0c797c14a248fc976f03f55cd5)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * AMD AE4DMA driver
4  *
5  * Copyright (c) 2024, Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Author: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
9  */
10 #ifndef __AE4DMA_H__
11 #define __AE4DMA_H__
12 
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dmapool.h>
16 #include <linux/list.h>
17 #include <linux/mutex.h>
18 #include <linux/pci.h>
19 #include <linux/spinlock.h>
20 #include <linux/wait.h>
21 
22 #include "../ptdma/ptdma.h"
23 #include "../../virt-dma.h"
24 
25 #define MAX_AE4_HW_QUEUES		16
26 
27 #define AE4_DESC_COMPLETED		0x03
28 
29 #define AE4_MAX_IDX_OFF			0x08
30 #define AE4_RD_IDX_OFF			0x0c
31 #define AE4_WR_IDX_OFF			0x10
32 #define AE4_INTR_STS_OFF		0x14
33 #define AE4_Q_BASE_L_OFF		0x18
34 #define AE4_Q_BASE_H_OFF		0x1c
35 #define AE4_Q_SZ			0x20
36 
37 #define AE4_DMA_VERSION			4
38 #define CMD_AE4_DESC_DW0_VAL		2
39 
40 struct ae4_msix {
41 	int msix_count;
42 	struct msix_entry msix_entry[MAX_AE4_HW_QUEUES];
43 };
44 
45 struct ae4_cmd_queue {
46 	struct ae4_device *ae4;
47 	struct pt_cmd_queue cmd_q;
48 	struct list_head cmd;
49 	/* protect command operations */
50 	struct mutex cmd_lock;
51 	struct delayed_work p_work;
52 	struct workqueue_struct *pws;
53 	struct completion cmp;
54 	wait_queue_head_t q_w;
55 	atomic64_t intr_cnt;
56 	atomic64_t done_cnt;
57 	u64 q_cmd_count;
58 	u32 dridx;
59 	u32 tail_wi;
60 	u32 id;
61 };
62 
63 union dwou {
64 	u32 dw0;
65 	struct dword0 {
66 	u8	byte0;
67 	u8	byte1;
68 	u16	timestamp;
69 	} dws;
70 };
71 
72 struct dword1 {
73 	u8	status;
74 	u8	err_code;
75 	u16	desc_id;
76 };
77 
78 struct ae4dma_desc {
79 	union dwou dwouv;
80 	struct dword1 dw1;
81 	u32 length;
82 	u32 rsvd;
83 	u32 src_hi;
84 	u32 src_lo;
85 	u32 dst_hi;
86 	u32 dst_lo;
87 };
88 
89 struct ae4_device {
90 	struct pt_device pt;
91 	struct ae4_msix *ae4_msix;
92 	struct ae4_cmd_queue ae4cmd_q[MAX_AE4_HW_QUEUES];
93 	unsigned int ae4_irq[MAX_AE4_HW_QUEUES];
94 	unsigned int cmd_q_count;
95 };
96 
97 int ae4_core_init(struct ae4_device *ae4);
98 void ae4_destroy_work(struct ae4_device *ae4);
99 void ae4_check_status_error(struct ae4_cmd_queue *ae4cmd_q, int idx);
100 #endif
101