1 /* 2 * Copyright (c) 2006 ARM Ltd. 3 * Copyright (c) 2010 ST-Ericsson SA 4 * 5 * Author: Peter Pearse <peter.pearse@arm.com> 6 * Author: Linus Walleij <linus.walleij@stericsson.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the Free 10 * Software Foundation; either version 2 of the License, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 59 20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 * 22 * The full GNU General Public License is in this distribution in the file 23 * called COPYING. 24 * 25 * Documentation: ARM DDI 0196G == PL080 26 * Documentation: ARM DDI 0218E == PL081 27 * 28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any 29 * channel. 30 * 31 * The PL080 has 8 channels available for simultaneous use, and the PL081 32 * has only two channels. So on these DMA controllers the number of channels 33 * and the number of incoming DMA signals are two totally different things. 34 * It is usually not possible to theoretically handle all physical signals, 35 * so a multiplexing scheme with possible denial of use is necessary. 36 * 37 * The PL080 has a dual bus master, PL081 has a single master. 38 * 39 * Memory to peripheral transfer may be visualized as 40 * Get data from memory to DMAC 41 * Until no data left 42 * On burst request from peripheral 43 * Destination burst from DMAC to peripheral 44 * Clear burst request 45 * Raise terminal count interrupt 46 * 47 * For peripherals with a FIFO: 48 * Source burst size == half the depth of the peripheral FIFO 49 * Destination burst size == the depth of the peripheral FIFO 50 * 51 * (Bursts are irrelevant for mem to mem transfers - there are no burst 52 * signals, the DMA controller will simply facilitate its AHB master.) 53 * 54 * ASSUMES default (little) endianness for DMA transfers 55 * 56 * The PL08x has two flow control settings: 57 * - DMAC flow control: the transfer size defines the number of transfers 58 * which occur for the current LLI entry, and the DMAC raises TC at the 59 * end of every LLI entry. Observed behaviour shows the DMAC listening 60 * to both the BREQ and SREQ signals (contrary to documented), 61 * transferring data if either is active. The LBREQ and LSREQ signals 62 * are ignored. 63 * 64 * - Peripheral flow control: the transfer size is ignored (and should be 65 * zero). The data is transferred from the current LLI entry, until 66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC 67 * will then move to the next LLI entry. 68 * 69 * Only the former works sanely with scatter lists, so we only implement 70 * the DMAC flow control method. However, peripherals which use the LBREQ 71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through 72 * these hardware restrictions prevents them from using scatter DMA. 73 * 74 * Global TODO: 75 * - Break out common code from arch/arm/mach-s3c64xx and share 76 */ 77 #include <linux/device.h> 78 #include <linux/init.h> 79 #include <linux/module.h> 80 #include <linux/interrupt.h> 81 #include <linux/slab.h> 82 #include <linux/delay.h> 83 #include <linux/dmapool.h> 84 #include <linux/dmaengine.h> 85 #include <linux/amba/bus.h> 86 #include <linux/amba/pl08x.h> 87 #include <linux/debugfs.h> 88 #include <linux/seq_file.h> 89 90 #include <asm/hardware/pl080.h> 91 92 #define DRIVER_NAME "pl08xdmac" 93 94 /** 95 * struct vendor_data - vendor-specific config parameters for PL08x derivatives 96 * @channels: the number of channels available in this variant 97 * @dualmaster: whether this version supports dual AHB masters or not. 98 */ 99 struct vendor_data { 100 u8 channels; 101 bool dualmaster; 102 }; 103 104 /* 105 * PL08X private data structures 106 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, 107 * start & end do not - their bus bit info is in cctl. Also note that these 108 * are fixed 32-bit quantities. 109 */ 110 struct pl08x_lli { 111 u32 src; 112 u32 dst; 113 u32 lli; 114 u32 cctl; 115 }; 116 117 /** 118 * struct pl08x_driver_data - the local state holder for the PL08x 119 * @slave: slave engine for this instance 120 * @memcpy: memcpy engine for this instance 121 * @base: virtual memory base (remapped) for the PL08x 122 * @adev: the corresponding AMBA (PrimeCell) bus entry 123 * @vd: vendor data for this PL08x variant 124 * @pd: platform data passed in from the platform/machine 125 * @phy_chans: array of data for the physical channels 126 * @pool: a pool for the LLI descriptors 127 * @pool_ctr: counter of LLIs in the pool 128 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches 129 * @mem_buses: set to indicate memory transfers on AHB2. 130 * @lock: a spinlock for this struct 131 */ 132 struct pl08x_driver_data { 133 struct dma_device slave; 134 struct dma_device memcpy; 135 void __iomem *base; 136 struct amba_device *adev; 137 const struct vendor_data *vd; 138 struct pl08x_platform_data *pd; 139 struct pl08x_phy_chan *phy_chans; 140 struct dma_pool *pool; 141 int pool_ctr; 142 u8 lli_buses; 143 u8 mem_buses; 144 spinlock_t lock; 145 }; 146 147 /* 148 * PL08X specific defines 149 */ 150 151 /* 152 * Memory boundaries: the manual for PL08x says that the controller 153 * cannot read past a 1KiB boundary, so these defines are used to 154 * create transfer LLIs that do not cross such boundaries. 155 */ 156 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */ 157 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT) 158 159 /* Size (bytes) of each LLI buffer allocated for one transfer */ 160 # define PL08X_LLI_TSFR_SIZE 0x2000 161 162 /* Maximum times we call dma_pool_alloc on this pool without freeing */ 163 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) 164 #define PL08X_ALIGN 8 165 166 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) 167 { 168 return container_of(chan, struct pl08x_dma_chan, chan); 169 } 170 171 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) 172 { 173 return container_of(tx, struct pl08x_txd, tx); 174 } 175 176 /* 177 * Physical channel handling 178 */ 179 180 /* Whether a certain channel is busy or not */ 181 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) 182 { 183 unsigned int val; 184 185 val = readl(ch->base + PL080_CH_CONFIG); 186 return val & PL080_CONFIG_ACTIVE; 187 } 188 189 /* 190 * Set the initial DMA register values i.e. those for the first LLI 191 * The next LLI pointer and the configuration interrupt bit have 192 * been set when the LLIs were constructed. Poke them into the hardware 193 * and start the transfer. 194 */ 195 static void pl08x_start_txd(struct pl08x_dma_chan *plchan, 196 struct pl08x_txd *txd) 197 { 198 struct pl08x_driver_data *pl08x = plchan->host; 199 struct pl08x_phy_chan *phychan = plchan->phychan; 200 struct pl08x_lli *lli = &txd->llis_va[0]; 201 u32 val; 202 203 plchan->at = txd; 204 205 /* Wait for channel inactive */ 206 while (pl08x_phy_channel_busy(phychan)) 207 cpu_relax(); 208 209 dev_vdbg(&pl08x->adev->dev, 210 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " 211 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", 212 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, 213 txd->ccfg); 214 215 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); 216 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); 217 writel(lli->lli, phychan->base + PL080_CH_LLI); 218 writel(lli->cctl, phychan->base + PL080_CH_CONTROL); 219 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); 220 221 /* Enable the DMA channel */ 222 /* Do not access config register until channel shows as disabled */ 223 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) 224 cpu_relax(); 225 226 /* Do not access config register until channel shows as inactive */ 227 val = readl(phychan->base + PL080_CH_CONFIG); 228 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) 229 val = readl(phychan->base + PL080_CH_CONFIG); 230 231 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); 232 } 233 234 /* 235 * Pause the channel by setting the HALT bit. 236 * 237 * For M->P transfers, pause the DMAC first and then stop the peripheral - 238 * the FIFO can only drain if the peripheral is still requesting data. 239 * (note: this can still timeout if the DMAC FIFO never drains of data.) 240 * 241 * For P->M transfers, disable the peripheral first to stop it filling 242 * the DMAC FIFO, and then pause the DMAC. 243 */ 244 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) 245 { 246 u32 val; 247 int timeout; 248 249 /* Set the HALT bit and wait for the FIFO to drain */ 250 val = readl(ch->base + PL080_CH_CONFIG); 251 val |= PL080_CONFIG_HALT; 252 writel(val, ch->base + PL080_CH_CONFIG); 253 254 /* Wait for channel inactive */ 255 for (timeout = 1000; timeout; timeout--) { 256 if (!pl08x_phy_channel_busy(ch)) 257 break; 258 udelay(1); 259 } 260 if (pl08x_phy_channel_busy(ch)) 261 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); 262 } 263 264 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) 265 { 266 u32 val; 267 268 /* Clear the HALT bit */ 269 val = readl(ch->base + PL080_CH_CONFIG); 270 val &= ~PL080_CONFIG_HALT; 271 writel(val, ch->base + PL080_CH_CONFIG); 272 } 273 274 275 /* 276 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and 277 * clears any pending interrupt status. This should not be used for 278 * an on-going transfer, but as a method of shutting down a channel 279 * (eg, when it's no longer used) or terminating a transfer. 280 */ 281 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, 282 struct pl08x_phy_chan *ch) 283 { 284 u32 val = readl(ch->base + PL080_CH_CONFIG); 285 286 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | 287 PL080_CONFIG_TC_IRQ_MASK); 288 289 writel(val, ch->base + PL080_CH_CONFIG); 290 291 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); 292 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); 293 } 294 295 static inline u32 get_bytes_in_cctl(u32 cctl) 296 { 297 /* The source width defines the number of bytes */ 298 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; 299 300 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { 301 case PL080_WIDTH_8BIT: 302 break; 303 case PL080_WIDTH_16BIT: 304 bytes *= 2; 305 break; 306 case PL080_WIDTH_32BIT: 307 bytes *= 4; 308 break; 309 } 310 return bytes; 311 } 312 313 /* The channel should be paused when calling this */ 314 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) 315 { 316 struct pl08x_phy_chan *ch; 317 struct pl08x_txd *txd; 318 unsigned long flags; 319 size_t bytes = 0; 320 321 spin_lock_irqsave(&plchan->lock, flags); 322 ch = plchan->phychan; 323 txd = plchan->at; 324 325 /* 326 * Follow the LLIs to get the number of remaining 327 * bytes in the currently active transaction. 328 */ 329 if (ch && txd) { 330 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; 331 332 /* First get the remaining bytes in the active transfer */ 333 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); 334 335 if (clli) { 336 struct pl08x_lli *llis_va = txd->llis_va; 337 dma_addr_t llis_bus = txd->llis_bus; 338 int index; 339 340 BUG_ON(clli < llis_bus || clli >= llis_bus + 341 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); 342 343 /* 344 * Locate the next LLI - as this is an array, 345 * it's simple maths to find. 346 */ 347 index = (clli - llis_bus) / sizeof(struct pl08x_lli); 348 349 for (; index < MAX_NUM_TSFR_LLIS; index++) { 350 bytes += get_bytes_in_cctl(llis_va[index].cctl); 351 352 /* 353 * A LLI pointer of 0 terminates the LLI list 354 */ 355 if (!llis_va[index].lli) 356 break; 357 } 358 } 359 } 360 361 /* Sum up all queued transactions */ 362 if (!list_empty(&plchan->pend_list)) { 363 struct pl08x_txd *txdi; 364 list_for_each_entry(txdi, &plchan->pend_list, node) { 365 bytes += txdi->len; 366 } 367 } 368 369 spin_unlock_irqrestore(&plchan->lock, flags); 370 371 return bytes; 372 } 373 374 /* 375 * Allocate a physical channel for a virtual channel 376 * 377 * Try to locate a physical channel to be used for this transfer. If all 378 * are taken return NULL and the requester will have to cope by using 379 * some fallback PIO mode or retrying later. 380 */ 381 static struct pl08x_phy_chan * 382 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, 383 struct pl08x_dma_chan *virt_chan) 384 { 385 struct pl08x_phy_chan *ch = NULL; 386 unsigned long flags; 387 int i; 388 389 for (i = 0; i < pl08x->vd->channels; i++) { 390 ch = &pl08x->phy_chans[i]; 391 392 spin_lock_irqsave(&ch->lock, flags); 393 394 if (!ch->serving) { 395 ch->serving = virt_chan; 396 ch->signal = -1; 397 spin_unlock_irqrestore(&ch->lock, flags); 398 break; 399 } 400 401 spin_unlock_irqrestore(&ch->lock, flags); 402 } 403 404 if (i == pl08x->vd->channels) { 405 /* No physical channel available, cope with it */ 406 return NULL; 407 } 408 409 return ch; 410 } 411 412 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, 413 struct pl08x_phy_chan *ch) 414 { 415 unsigned long flags; 416 417 spin_lock_irqsave(&ch->lock, flags); 418 419 /* Stop the channel and clear its interrupts */ 420 pl08x_terminate_phy_chan(pl08x, ch); 421 422 /* Mark it as free */ 423 ch->serving = NULL; 424 spin_unlock_irqrestore(&ch->lock, flags); 425 } 426 427 /* 428 * LLI handling 429 */ 430 431 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) 432 { 433 switch (coded) { 434 case PL080_WIDTH_8BIT: 435 return 1; 436 case PL080_WIDTH_16BIT: 437 return 2; 438 case PL080_WIDTH_32BIT: 439 return 4; 440 default: 441 break; 442 } 443 BUG(); 444 return 0; 445 } 446 447 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, 448 size_t tsize) 449 { 450 u32 retbits = cctl; 451 452 /* Remove all src, dst and transfer size bits */ 453 retbits &= ~PL080_CONTROL_DWIDTH_MASK; 454 retbits &= ~PL080_CONTROL_SWIDTH_MASK; 455 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; 456 457 /* Then set the bits according to the parameters */ 458 switch (srcwidth) { 459 case 1: 460 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; 461 break; 462 case 2: 463 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; 464 break; 465 case 4: 466 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; 467 break; 468 default: 469 BUG(); 470 break; 471 } 472 473 switch (dstwidth) { 474 case 1: 475 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; 476 break; 477 case 2: 478 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; 479 break; 480 case 4: 481 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; 482 break; 483 default: 484 BUG(); 485 break; 486 } 487 488 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; 489 return retbits; 490 } 491 492 struct pl08x_lli_build_data { 493 struct pl08x_txd *txd; 494 struct pl08x_bus_data srcbus; 495 struct pl08x_bus_data dstbus; 496 size_t remainder; 497 u32 lli_bus; 498 }; 499 500 /* 501 * Autoselect a master bus to use for the transfer this prefers the 502 * destination bus if both available if fixed address on one bus the 503 * other will be chosen 504 */ 505 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, 506 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) 507 { 508 if (!(cctl & PL080_CONTROL_DST_INCR)) { 509 *mbus = &bd->srcbus; 510 *sbus = &bd->dstbus; 511 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { 512 *mbus = &bd->dstbus; 513 *sbus = &bd->srcbus; 514 } else { 515 if (bd->dstbus.buswidth == 4) { 516 *mbus = &bd->dstbus; 517 *sbus = &bd->srcbus; 518 } else if (bd->srcbus.buswidth == 4) { 519 *mbus = &bd->srcbus; 520 *sbus = &bd->dstbus; 521 } else if (bd->dstbus.buswidth == 2) { 522 *mbus = &bd->dstbus; 523 *sbus = &bd->srcbus; 524 } else if (bd->srcbus.buswidth == 2) { 525 *mbus = &bd->srcbus; 526 *sbus = &bd->dstbus; 527 } else { 528 /* bd->srcbus.buswidth == 1 */ 529 *mbus = &bd->dstbus; 530 *sbus = &bd->srcbus; 531 } 532 } 533 } 534 535 /* 536 * Fills in one LLI for a certain transfer descriptor and advance the counter 537 */ 538 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd, 539 int num_llis, int len, u32 cctl) 540 { 541 struct pl08x_lli *llis_va = bd->txd->llis_va; 542 dma_addr_t llis_bus = bd->txd->llis_bus; 543 544 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); 545 546 llis_va[num_llis].cctl = cctl; 547 llis_va[num_llis].src = bd->srcbus.addr; 548 llis_va[num_llis].dst = bd->dstbus.addr; 549 llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli); 550 llis_va[num_llis].lli |= bd->lli_bus; 551 552 if (cctl & PL080_CONTROL_SRC_INCR) 553 bd->srcbus.addr += len; 554 if (cctl & PL080_CONTROL_DST_INCR) 555 bd->dstbus.addr += len; 556 557 BUG_ON(bd->remainder < len); 558 559 bd->remainder -= len; 560 } 561 562 /* 563 * Return number of bytes to fill to boundary, or len. 564 * This calculation works for any value of addr. 565 */ 566 static inline size_t pl08x_pre_boundary(u32 addr, size_t len) 567 { 568 size_t boundary_len = PL08X_BOUNDARY_SIZE - 569 (addr & (PL08X_BOUNDARY_SIZE - 1)); 570 571 return min(boundary_len, len); 572 } 573 574 /* 575 * This fills in the table of LLIs for the transfer descriptor 576 * Note that we assume we never have to change the burst sizes 577 * Return 0 for error 578 */ 579 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, 580 struct pl08x_txd *txd) 581 { 582 struct pl08x_bus_data *mbus, *sbus; 583 struct pl08x_lli_build_data bd; 584 int num_llis = 0; 585 u32 cctl; 586 size_t max_bytes_per_lli; 587 size_t total_bytes = 0; 588 struct pl08x_lli *llis_va; 589 590 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, 591 &txd->llis_bus); 592 if (!txd->llis_va) { 593 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); 594 return 0; 595 } 596 597 pl08x->pool_ctr++; 598 599 /* Get the default CCTL */ 600 cctl = txd->cctl; 601 602 bd.txd = txd; 603 bd.srcbus.addr = txd->src_addr; 604 bd.dstbus.addr = txd->dst_addr; 605 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; 606 607 /* Find maximum width of the source bus */ 608 bd.srcbus.maxwidth = 609 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> 610 PL080_CONTROL_SWIDTH_SHIFT); 611 612 /* Find maximum width of the destination bus */ 613 bd.dstbus.maxwidth = 614 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> 615 PL080_CONTROL_DWIDTH_SHIFT); 616 617 /* Set up the bus widths to the maximum */ 618 bd.srcbus.buswidth = bd.srcbus.maxwidth; 619 bd.dstbus.buswidth = bd.dstbus.maxwidth; 620 621 /* 622 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths) 623 */ 624 max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) * 625 PL080_CONTROL_TRANSFER_SIZE_MASK; 626 627 /* We need to count this down to zero */ 628 bd.remainder = txd->len; 629 630 /* 631 * Choose bus to align to 632 * - prefers destination bus if both available 633 * - if fixed address on one bus chooses other 634 */ 635 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); 636 637 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu llimax=%zu\n", 638 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", 639 bd.srcbus.buswidth, 640 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", 641 bd.dstbus.buswidth, 642 bd.remainder, max_bytes_per_lli); 643 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", 644 mbus == &bd.srcbus ? "src" : "dst", 645 sbus == &bd.srcbus ? "src" : "dst"); 646 647 if (txd->len < mbus->buswidth) { 648 /* Less than a bus width available - send as single bytes */ 649 while (bd.remainder) { 650 dev_vdbg(&pl08x->adev->dev, 651 "%s single byte LLIs for a transfer of " 652 "less than a bus width (remain 0x%08x)\n", 653 __func__, bd.remainder); 654 cctl = pl08x_cctl_bits(cctl, 1, 1, 1); 655 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl); 656 total_bytes++; 657 } 658 } else { 659 /* Make one byte LLIs until master bus is aligned */ 660 while ((mbus->addr) % (mbus->buswidth)) { 661 dev_vdbg(&pl08x->adev->dev, 662 "%s adjustment lli for less than bus width " 663 "(remain 0x%08x)\n", 664 __func__, bd.remainder); 665 cctl = pl08x_cctl_bits(cctl, 1, 1, 1); 666 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl); 667 total_bytes++; 668 } 669 670 /* 671 * Master now aligned 672 * - if slave is not then we must set its width down 673 */ 674 if (sbus->addr % sbus->buswidth) { 675 dev_dbg(&pl08x->adev->dev, 676 "%s set down bus width to one byte\n", 677 __func__); 678 679 sbus->buswidth = 1; 680 } 681 682 /* 683 * Make largest possible LLIs until less than one bus 684 * width left 685 */ 686 while (bd.remainder > (mbus->buswidth - 1)) { 687 size_t lli_len, target_len, tsize, odd_bytes; 688 689 /* 690 * If enough left try to send max possible, 691 * otherwise try to send the remainder 692 */ 693 target_len = min(bd.remainder, max_bytes_per_lli); 694 695 /* 696 * Set bus lengths for incrementing buses to the 697 * number of bytes which fill to next memory boundary, 698 * limiting on the target length calculated above. 699 */ 700 if (cctl & PL080_CONTROL_SRC_INCR) 701 bd.srcbus.fill_bytes = 702 pl08x_pre_boundary(bd.srcbus.addr, 703 target_len); 704 else 705 bd.srcbus.fill_bytes = target_len; 706 707 if (cctl & PL080_CONTROL_DST_INCR) 708 bd.dstbus.fill_bytes = 709 pl08x_pre_boundary(bd.dstbus.addr, 710 target_len); 711 else 712 bd.dstbus.fill_bytes = target_len; 713 714 /* Find the nearest */ 715 lli_len = min(bd.srcbus.fill_bytes, 716 bd.dstbus.fill_bytes); 717 718 BUG_ON(lli_len > bd.remainder); 719 720 if (lli_len <= 0) { 721 dev_err(&pl08x->adev->dev, 722 "%s lli_len is %zu, <= 0\n", 723 __func__, lli_len); 724 return 0; 725 } 726 727 if (lli_len == target_len) { 728 /* 729 * Can send what we wanted. 730 * Maintain alignment 731 */ 732 lli_len = (lli_len/mbus->buswidth) * 733 mbus->buswidth; 734 odd_bytes = 0; 735 } else { 736 /* 737 * So now we know how many bytes to transfer 738 * to get to the nearest boundary. The next 739 * LLI will past the boundary. However, we 740 * may be working to a boundary on the slave 741 * bus. We need to ensure the master stays 742 * aligned, and that we are working in 743 * multiples of the bus widths. 744 */ 745 odd_bytes = lli_len % mbus->buswidth; 746 lli_len -= odd_bytes; 747 748 } 749 750 if (lli_len) { 751 /* 752 * Check against minimum bus alignment: 753 * Calculate actual transfer size in relation 754 * to bus width an get a maximum remainder of 755 * the smallest bus width - 1 756 */ 757 /* FIXME: use round_down()? */ 758 tsize = lli_len / min(mbus->buswidth, 759 sbus->buswidth); 760 lli_len = tsize * min(mbus->buswidth, 761 sbus->buswidth); 762 763 if (target_len != lli_len) { 764 dev_vdbg(&pl08x->adev->dev, 765 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n", 766 __func__, target_len, lli_len, txd->len); 767 } 768 769 cctl = pl08x_cctl_bits(cctl, 770 bd.srcbus.buswidth, 771 bd.dstbus.buswidth, 772 tsize); 773 774 dev_vdbg(&pl08x->adev->dev, 775 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n", 776 __func__, lli_len, bd.remainder); 777 pl08x_fill_lli_for_desc(&bd, num_llis++, 778 lli_len, cctl); 779 total_bytes += lli_len; 780 } 781 782 783 if (odd_bytes) { 784 /* 785 * Creep past the boundary, maintaining 786 * master alignment 787 */ 788 int j; 789 for (j = 0; (j < mbus->buswidth) 790 && (bd.remainder); j++) { 791 cctl = pl08x_cctl_bits(cctl, 1, 1, 1); 792 dev_vdbg(&pl08x->adev->dev, 793 "%s align with boundary, single byte (remain 0x%08zx)\n", 794 __func__, bd.remainder); 795 pl08x_fill_lli_for_desc(&bd, 796 num_llis++, 1, cctl); 797 total_bytes++; 798 } 799 } 800 } 801 802 /* 803 * Send any odd bytes 804 */ 805 while (bd.remainder) { 806 cctl = pl08x_cctl_bits(cctl, 1, 1, 1); 807 dev_vdbg(&pl08x->adev->dev, 808 "%s align with boundary, single odd byte (remain %zu)\n", 809 __func__, bd.remainder); 810 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl); 811 total_bytes++; 812 } 813 } 814 if (total_bytes != txd->len) { 815 dev_err(&pl08x->adev->dev, 816 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", 817 __func__, total_bytes, txd->len); 818 return 0; 819 } 820 821 if (num_llis >= MAX_NUM_TSFR_LLIS) { 822 dev_err(&pl08x->adev->dev, 823 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", 824 __func__, (u32) MAX_NUM_TSFR_LLIS); 825 return 0; 826 } 827 828 llis_va = txd->llis_va; 829 /* The final LLI terminates the LLI. */ 830 llis_va[num_llis - 1].lli = 0; 831 /* The final LLI element shall also fire an interrupt. */ 832 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; 833 834 #ifdef VERBOSE_DEBUG 835 { 836 int i; 837 838 dev_vdbg(&pl08x->adev->dev, 839 "%-3s %-9s %-10s %-10s %-10s %s\n", 840 "lli", "", "csrc", "cdst", "clli", "cctl"); 841 for (i = 0; i < num_llis; i++) { 842 dev_vdbg(&pl08x->adev->dev, 843 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", 844 i, &llis_va[i], llis_va[i].src, 845 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl 846 ); 847 } 848 } 849 #endif 850 851 return num_llis; 852 } 853 854 /* You should call this with the struct pl08x lock held */ 855 static void pl08x_free_txd(struct pl08x_driver_data *pl08x, 856 struct pl08x_txd *txd) 857 { 858 /* Free the LLI */ 859 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); 860 861 pl08x->pool_ctr--; 862 863 kfree(txd); 864 } 865 866 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, 867 struct pl08x_dma_chan *plchan) 868 { 869 struct pl08x_txd *txdi = NULL; 870 struct pl08x_txd *next; 871 872 if (!list_empty(&plchan->pend_list)) { 873 list_for_each_entry_safe(txdi, 874 next, &plchan->pend_list, node) { 875 list_del(&txdi->node); 876 pl08x_free_txd(pl08x, txdi); 877 } 878 } 879 } 880 881 /* 882 * The DMA ENGINE API 883 */ 884 static int pl08x_alloc_chan_resources(struct dma_chan *chan) 885 { 886 return 0; 887 } 888 889 static void pl08x_free_chan_resources(struct dma_chan *chan) 890 { 891 } 892 893 /* 894 * This should be called with the channel plchan->lock held 895 */ 896 static int prep_phy_channel(struct pl08x_dma_chan *plchan, 897 struct pl08x_txd *txd) 898 { 899 struct pl08x_driver_data *pl08x = plchan->host; 900 struct pl08x_phy_chan *ch; 901 int ret; 902 903 /* Check if we already have a channel */ 904 if (plchan->phychan) 905 return 0; 906 907 ch = pl08x_get_phy_channel(pl08x, plchan); 908 if (!ch) { 909 /* No physical channel available, cope with it */ 910 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); 911 return -EBUSY; 912 } 913 914 /* 915 * OK we have a physical channel: for memcpy() this is all we 916 * need, but for slaves the physical signals may be muxed! 917 * Can the platform allow us to use this channel? 918 */ 919 if (plchan->slave && 920 ch->signal < 0 && 921 pl08x->pd->get_signal) { 922 ret = pl08x->pd->get_signal(plchan); 923 if (ret < 0) { 924 dev_dbg(&pl08x->adev->dev, 925 "unable to use physical channel %d for transfer on %s due to platform restrictions\n", 926 ch->id, plchan->name); 927 /* Release physical channel & return */ 928 pl08x_put_phy_channel(pl08x, ch); 929 return -EBUSY; 930 } 931 ch->signal = ret; 932 933 /* Assign the flow control signal to this channel */ 934 if (txd->direction == DMA_TO_DEVICE) 935 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; 936 else if (txd->direction == DMA_FROM_DEVICE) 937 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; 938 } 939 940 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n", 941 ch->id, 942 ch->signal, 943 plchan->name); 944 945 plchan->phychan_hold++; 946 plchan->phychan = ch; 947 948 return 0; 949 } 950 951 static void release_phy_channel(struct pl08x_dma_chan *plchan) 952 { 953 struct pl08x_driver_data *pl08x = plchan->host; 954 955 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) { 956 pl08x->pd->put_signal(plchan); 957 plchan->phychan->signal = -1; 958 } 959 pl08x_put_phy_channel(pl08x, plchan->phychan); 960 plchan->phychan = NULL; 961 } 962 963 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) 964 { 965 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); 966 struct pl08x_txd *txd = to_pl08x_txd(tx); 967 unsigned long flags; 968 969 spin_lock_irqsave(&plchan->lock, flags); 970 971 plchan->chan.cookie += 1; 972 if (plchan->chan.cookie < 0) 973 plchan->chan.cookie = 1; 974 tx->cookie = plchan->chan.cookie; 975 976 /* Put this onto the pending list */ 977 list_add_tail(&txd->node, &plchan->pend_list); 978 979 /* 980 * If there was no physical channel available for this memcpy, 981 * stack the request up and indicate that the channel is waiting 982 * for a free physical channel. 983 */ 984 if (!plchan->slave && !plchan->phychan) { 985 /* Do this memcpy whenever there is a channel ready */ 986 plchan->state = PL08X_CHAN_WAITING; 987 plchan->waiting = txd; 988 } else { 989 plchan->phychan_hold--; 990 } 991 992 spin_unlock_irqrestore(&plchan->lock, flags); 993 994 return tx->cookie; 995 } 996 997 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( 998 struct dma_chan *chan, unsigned long flags) 999 { 1000 struct dma_async_tx_descriptor *retval = NULL; 1001 1002 return retval; 1003 } 1004 1005 /* 1006 * Code accessing dma_async_is_complete() in a tight loop may give problems. 1007 * If slaves are relying on interrupts to signal completion this function 1008 * must not be called with interrupts disabled. 1009 */ 1010 static enum dma_status 1011 pl08x_dma_tx_status(struct dma_chan *chan, 1012 dma_cookie_t cookie, 1013 struct dma_tx_state *txstate) 1014 { 1015 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1016 dma_cookie_t last_used; 1017 dma_cookie_t last_complete; 1018 enum dma_status ret; 1019 u32 bytesleft = 0; 1020 1021 last_used = plchan->chan.cookie; 1022 last_complete = plchan->lc; 1023 1024 ret = dma_async_is_complete(cookie, last_complete, last_used); 1025 if (ret == DMA_SUCCESS) { 1026 dma_set_tx_state(txstate, last_complete, last_used, 0); 1027 return ret; 1028 } 1029 1030 /* 1031 * This cookie not complete yet 1032 */ 1033 last_used = plchan->chan.cookie; 1034 last_complete = plchan->lc; 1035 1036 /* Get number of bytes left in the active transactions and queue */ 1037 bytesleft = pl08x_getbytes_chan(plchan); 1038 1039 dma_set_tx_state(txstate, last_complete, last_used, 1040 bytesleft); 1041 1042 if (plchan->state == PL08X_CHAN_PAUSED) 1043 return DMA_PAUSED; 1044 1045 /* Whether waiting or running, we're in progress */ 1046 return DMA_IN_PROGRESS; 1047 } 1048 1049 /* PrimeCell DMA extension */ 1050 struct burst_table { 1051 u32 burstwords; 1052 u32 reg; 1053 }; 1054 1055 static const struct burst_table burst_sizes[] = { 1056 { 1057 .burstwords = 256, 1058 .reg = PL080_BSIZE_256, 1059 }, 1060 { 1061 .burstwords = 128, 1062 .reg = PL080_BSIZE_128, 1063 }, 1064 { 1065 .burstwords = 64, 1066 .reg = PL080_BSIZE_64, 1067 }, 1068 { 1069 .burstwords = 32, 1070 .reg = PL080_BSIZE_32, 1071 }, 1072 { 1073 .burstwords = 16, 1074 .reg = PL080_BSIZE_16, 1075 }, 1076 { 1077 .burstwords = 8, 1078 .reg = PL080_BSIZE_8, 1079 }, 1080 { 1081 .burstwords = 4, 1082 .reg = PL080_BSIZE_4, 1083 }, 1084 { 1085 .burstwords = 0, 1086 .reg = PL080_BSIZE_1, 1087 }, 1088 }; 1089 1090 /* 1091 * Given the source and destination available bus masks, select which 1092 * will be routed to each port. We try to have source and destination 1093 * on separate ports, but always respect the allowable settings. 1094 */ 1095 static u32 pl08x_select_bus(u8 src, u8 dst) 1096 { 1097 u32 cctl = 0; 1098 1099 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) 1100 cctl |= PL080_CONTROL_DST_AHB2; 1101 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) 1102 cctl |= PL080_CONTROL_SRC_AHB2; 1103 1104 return cctl; 1105 } 1106 1107 static u32 pl08x_cctl(u32 cctl) 1108 { 1109 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | 1110 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | 1111 PL080_CONTROL_PROT_MASK); 1112 1113 /* Access the cell in privileged mode, non-bufferable, non-cacheable */ 1114 return cctl | PL080_CONTROL_PROT_SYS; 1115 } 1116 1117 static u32 pl08x_width(enum dma_slave_buswidth width) 1118 { 1119 switch (width) { 1120 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1121 return PL080_WIDTH_8BIT; 1122 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1123 return PL080_WIDTH_16BIT; 1124 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1125 return PL080_WIDTH_32BIT; 1126 default: 1127 return ~0; 1128 } 1129 } 1130 1131 static u32 pl08x_burst(u32 maxburst) 1132 { 1133 int i; 1134 1135 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) 1136 if (burst_sizes[i].burstwords <= maxburst) 1137 break; 1138 1139 return burst_sizes[i].reg; 1140 } 1141 1142 static int dma_set_runtime_config(struct dma_chan *chan, 1143 struct dma_slave_config *config) 1144 { 1145 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1146 struct pl08x_driver_data *pl08x = plchan->host; 1147 enum dma_slave_buswidth addr_width; 1148 u32 width, burst, maxburst; 1149 u32 cctl = 0; 1150 1151 if (!plchan->slave) 1152 return -EINVAL; 1153 1154 /* Transfer direction */ 1155 plchan->runtime_direction = config->direction; 1156 if (config->direction == DMA_TO_DEVICE) { 1157 addr_width = config->dst_addr_width; 1158 maxburst = config->dst_maxburst; 1159 } else if (config->direction == DMA_FROM_DEVICE) { 1160 addr_width = config->src_addr_width; 1161 maxburst = config->src_maxburst; 1162 } else { 1163 dev_err(&pl08x->adev->dev, 1164 "bad runtime_config: alien transfer direction\n"); 1165 return -EINVAL; 1166 } 1167 1168 width = pl08x_width(addr_width); 1169 if (width == ~0) { 1170 dev_err(&pl08x->adev->dev, 1171 "bad runtime_config: alien address width\n"); 1172 return -EINVAL; 1173 } 1174 1175 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; 1176 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; 1177 1178 /* 1179 * If this channel will only request single transfers, set this 1180 * down to ONE element. Also select one element if no maxburst 1181 * is specified. 1182 */ 1183 if (plchan->cd->single) 1184 maxburst = 1; 1185 1186 burst = pl08x_burst(maxburst); 1187 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; 1188 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; 1189 1190 if (plchan->runtime_direction == DMA_FROM_DEVICE) { 1191 plchan->src_addr = config->src_addr; 1192 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR | 1193 pl08x_select_bus(plchan->cd->periph_buses, 1194 pl08x->mem_buses); 1195 } else { 1196 plchan->dst_addr = config->dst_addr; 1197 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR | 1198 pl08x_select_bus(pl08x->mem_buses, 1199 plchan->cd->periph_buses); 1200 } 1201 1202 dev_dbg(&pl08x->adev->dev, 1203 "configured channel %s (%s) for %s, data width %d, " 1204 "maxburst %d words, LE, CCTL=0x%08x\n", 1205 dma_chan_name(chan), plchan->name, 1206 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", 1207 addr_width, 1208 maxburst, 1209 cctl); 1210 1211 return 0; 1212 } 1213 1214 /* 1215 * Slave transactions callback to the slave device to allow 1216 * synchronization of slave DMA signals with the DMAC enable 1217 */ 1218 static void pl08x_issue_pending(struct dma_chan *chan) 1219 { 1220 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1221 unsigned long flags; 1222 1223 spin_lock_irqsave(&plchan->lock, flags); 1224 /* Something is already active, or we're waiting for a channel... */ 1225 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) { 1226 spin_unlock_irqrestore(&plchan->lock, flags); 1227 return; 1228 } 1229 1230 /* Take the first element in the queue and execute it */ 1231 if (!list_empty(&plchan->pend_list)) { 1232 struct pl08x_txd *next; 1233 1234 next = list_first_entry(&plchan->pend_list, 1235 struct pl08x_txd, 1236 node); 1237 list_del(&next->node); 1238 plchan->state = PL08X_CHAN_RUNNING; 1239 1240 pl08x_start_txd(plchan, next); 1241 } 1242 1243 spin_unlock_irqrestore(&plchan->lock, flags); 1244 } 1245 1246 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, 1247 struct pl08x_txd *txd) 1248 { 1249 struct pl08x_driver_data *pl08x = plchan->host; 1250 unsigned long flags; 1251 int num_llis, ret; 1252 1253 num_llis = pl08x_fill_llis_for_desc(pl08x, txd); 1254 if (!num_llis) { 1255 kfree(txd); 1256 return -EINVAL; 1257 } 1258 1259 spin_lock_irqsave(&plchan->lock, flags); 1260 1261 /* 1262 * See if we already have a physical channel allocated, 1263 * else this is the time to try to get one. 1264 */ 1265 ret = prep_phy_channel(plchan, txd); 1266 if (ret) { 1267 /* 1268 * No physical channel was available. 1269 * 1270 * memcpy transfers can be sorted out at submission time. 1271 * 1272 * Slave transfers may have been denied due to platform 1273 * channel muxing restrictions. Since there is no guarantee 1274 * that this will ever be resolved, and the signal must be 1275 * acquired AFTER acquiring the physical channel, we will let 1276 * them be NACK:ed with -EBUSY here. The drivers can retry 1277 * the prep() call if they are eager on doing this using DMA. 1278 */ 1279 if (plchan->slave) { 1280 pl08x_free_txd_list(pl08x, plchan); 1281 pl08x_free_txd(pl08x, txd); 1282 spin_unlock_irqrestore(&plchan->lock, flags); 1283 return -EBUSY; 1284 } 1285 } else 1286 /* 1287 * Else we're all set, paused and ready to roll, status 1288 * will switch to PL08X_CHAN_RUNNING when we call 1289 * issue_pending(). If there is something running on the 1290 * channel already we don't change its state. 1291 */ 1292 if (plchan->state == PL08X_CHAN_IDLE) 1293 plchan->state = PL08X_CHAN_PAUSED; 1294 1295 spin_unlock_irqrestore(&plchan->lock, flags); 1296 1297 return 0; 1298 } 1299 1300 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan, 1301 unsigned long flags) 1302 { 1303 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT); 1304 1305 if (txd) { 1306 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan); 1307 txd->tx.flags = flags; 1308 txd->tx.tx_submit = pl08x_tx_submit; 1309 INIT_LIST_HEAD(&txd->node); 1310 1311 /* Always enable error and terminal interrupts */ 1312 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | 1313 PL080_CONFIG_TC_IRQ_MASK; 1314 } 1315 return txd; 1316 } 1317 1318 /* 1319 * Initialize a descriptor to be used by memcpy submit 1320 */ 1321 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( 1322 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 1323 size_t len, unsigned long flags) 1324 { 1325 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1326 struct pl08x_driver_data *pl08x = plchan->host; 1327 struct pl08x_txd *txd; 1328 int ret; 1329 1330 txd = pl08x_get_txd(plchan, flags); 1331 if (!txd) { 1332 dev_err(&pl08x->adev->dev, 1333 "%s no memory for descriptor\n", __func__); 1334 return NULL; 1335 } 1336 1337 txd->direction = DMA_NONE; 1338 txd->src_addr = src; 1339 txd->dst_addr = dest; 1340 txd->len = len; 1341 1342 /* Set platform data for m2m */ 1343 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; 1344 txd->cctl = pl08x->pd->memcpy_channel.cctl & 1345 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); 1346 1347 /* Both to be incremented or the code will break */ 1348 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; 1349 1350 if (pl08x->vd->dualmaster) 1351 txd->cctl |= pl08x_select_bus(pl08x->mem_buses, 1352 pl08x->mem_buses); 1353 1354 ret = pl08x_prep_channel_resources(plchan, txd); 1355 if (ret) 1356 return NULL; 1357 1358 return &txd->tx; 1359 } 1360 1361 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( 1362 struct dma_chan *chan, struct scatterlist *sgl, 1363 unsigned int sg_len, enum dma_data_direction direction, 1364 unsigned long flags) 1365 { 1366 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1367 struct pl08x_driver_data *pl08x = plchan->host; 1368 struct pl08x_txd *txd; 1369 int ret; 1370 1371 /* 1372 * Current implementation ASSUMES only one sg 1373 */ 1374 if (sg_len != 1) { 1375 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n", 1376 __func__); 1377 BUG(); 1378 } 1379 1380 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", 1381 __func__, sgl->length, plchan->name); 1382 1383 txd = pl08x_get_txd(plchan, flags); 1384 if (!txd) { 1385 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); 1386 return NULL; 1387 } 1388 1389 if (direction != plchan->runtime_direction) 1390 dev_err(&pl08x->adev->dev, "%s DMA setup does not match " 1391 "the direction configured for the PrimeCell\n", 1392 __func__); 1393 1394 /* 1395 * Set up addresses, the PrimeCell configured address 1396 * will take precedence since this may configure the 1397 * channel target address dynamically at runtime. 1398 */ 1399 txd->direction = direction; 1400 txd->len = sgl->length; 1401 1402 if (direction == DMA_TO_DEVICE) { 1403 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT; 1404 txd->cctl = plchan->dst_cctl; 1405 txd->src_addr = sgl->dma_address; 1406 txd->dst_addr = plchan->dst_addr; 1407 } else if (direction == DMA_FROM_DEVICE) { 1408 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; 1409 txd->cctl = plchan->src_cctl; 1410 txd->src_addr = plchan->src_addr; 1411 txd->dst_addr = sgl->dma_address; 1412 } else { 1413 dev_err(&pl08x->adev->dev, 1414 "%s direction unsupported\n", __func__); 1415 return NULL; 1416 } 1417 1418 ret = pl08x_prep_channel_resources(plchan, txd); 1419 if (ret) 1420 return NULL; 1421 1422 return &txd->tx; 1423 } 1424 1425 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 1426 unsigned long arg) 1427 { 1428 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1429 struct pl08x_driver_data *pl08x = plchan->host; 1430 unsigned long flags; 1431 int ret = 0; 1432 1433 /* Controls applicable to inactive channels */ 1434 if (cmd == DMA_SLAVE_CONFIG) { 1435 return dma_set_runtime_config(chan, 1436 (struct dma_slave_config *)arg); 1437 } 1438 1439 /* 1440 * Anything succeeds on channels with no physical allocation and 1441 * no queued transfers. 1442 */ 1443 spin_lock_irqsave(&plchan->lock, flags); 1444 if (!plchan->phychan && !plchan->at) { 1445 spin_unlock_irqrestore(&plchan->lock, flags); 1446 return 0; 1447 } 1448 1449 switch (cmd) { 1450 case DMA_TERMINATE_ALL: 1451 plchan->state = PL08X_CHAN_IDLE; 1452 1453 if (plchan->phychan) { 1454 pl08x_terminate_phy_chan(pl08x, plchan->phychan); 1455 1456 /* 1457 * Mark physical channel as free and free any slave 1458 * signal 1459 */ 1460 release_phy_channel(plchan); 1461 } 1462 /* Dequeue jobs and free LLIs */ 1463 if (plchan->at) { 1464 pl08x_free_txd(pl08x, plchan->at); 1465 plchan->at = NULL; 1466 } 1467 /* Dequeue jobs not yet fired as well */ 1468 pl08x_free_txd_list(pl08x, plchan); 1469 break; 1470 case DMA_PAUSE: 1471 pl08x_pause_phy_chan(plchan->phychan); 1472 plchan->state = PL08X_CHAN_PAUSED; 1473 break; 1474 case DMA_RESUME: 1475 pl08x_resume_phy_chan(plchan->phychan); 1476 plchan->state = PL08X_CHAN_RUNNING; 1477 break; 1478 default: 1479 /* Unknown command */ 1480 ret = -ENXIO; 1481 break; 1482 } 1483 1484 spin_unlock_irqrestore(&plchan->lock, flags); 1485 1486 return ret; 1487 } 1488 1489 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) 1490 { 1491 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1492 char *name = chan_id; 1493 1494 /* Check that the channel is not taken! */ 1495 if (!strcmp(plchan->name, name)) 1496 return true; 1497 1498 return false; 1499 } 1500 1501 /* 1502 * Just check that the device is there and active 1503 * TODO: turn this bit on/off depending on the number of physical channels 1504 * actually used, if it is zero... well shut it off. That will save some 1505 * power. Cut the clock at the same time. 1506 */ 1507 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) 1508 { 1509 u32 val; 1510 1511 val = readl(pl08x->base + PL080_CONFIG); 1512 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE); 1513 /* We implicitly clear bit 1 and that means little-endian mode */ 1514 val |= PL080_CONFIG_ENABLE; 1515 writel(val, pl08x->base + PL080_CONFIG); 1516 } 1517 1518 static void pl08x_unmap_buffers(struct pl08x_txd *txd) 1519 { 1520 struct device *dev = txd->tx.chan->device->dev; 1521 1522 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { 1523 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) 1524 dma_unmap_single(dev, txd->src_addr, txd->len, 1525 DMA_TO_DEVICE); 1526 else 1527 dma_unmap_page(dev, txd->src_addr, txd->len, 1528 DMA_TO_DEVICE); 1529 } 1530 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { 1531 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) 1532 dma_unmap_single(dev, txd->dst_addr, txd->len, 1533 DMA_FROM_DEVICE); 1534 else 1535 dma_unmap_page(dev, txd->dst_addr, txd->len, 1536 DMA_FROM_DEVICE); 1537 } 1538 } 1539 1540 static void pl08x_tasklet(unsigned long data) 1541 { 1542 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; 1543 struct pl08x_driver_data *pl08x = plchan->host; 1544 struct pl08x_txd *txd; 1545 unsigned long flags; 1546 1547 spin_lock_irqsave(&plchan->lock, flags); 1548 1549 txd = plchan->at; 1550 plchan->at = NULL; 1551 1552 if (txd) { 1553 /* Update last completed */ 1554 plchan->lc = txd->tx.cookie; 1555 } 1556 1557 /* If a new descriptor is queued, set it up plchan->at is NULL here */ 1558 if (!list_empty(&plchan->pend_list)) { 1559 struct pl08x_txd *next; 1560 1561 next = list_first_entry(&plchan->pend_list, 1562 struct pl08x_txd, 1563 node); 1564 list_del(&next->node); 1565 1566 pl08x_start_txd(plchan, next); 1567 } else if (plchan->phychan_hold) { 1568 /* 1569 * This channel is still in use - we have a new txd being 1570 * prepared and will soon be queued. Don't give up the 1571 * physical channel. 1572 */ 1573 } else { 1574 struct pl08x_dma_chan *waiting = NULL; 1575 1576 /* 1577 * No more jobs, so free up the physical channel 1578 * Free any allocated signal on slave transfers too 1579 */ 1580 release_phy_channel(plchan); 1581 plchan->state = PL08X_CHAN_IDLE; 1582 1583 /* 1584 * And NOW before anyone else can grab that free:d up 1585 * physical channel, see if there is some memcpy pending 1586 * that seriously needs to start because of being stacked 1587 * up while we were choking the physical channels with data. 1588 */ 1589 list_for_each_entry(waiting, &pl08x->memcpy.channels, 1590 chan.device_node) { 1591 if (waiting->state == PL08X_CHAN_WAITING && 1592 waiting->waiting != NULL) { 1593 int ret; 1594 1595 /* This should REALLY not fail now */ 1596 ret = prep_phy_channel(waiting, 1597 waiting->waiting); 1598 BUG_ON(ret); 1599 waiting->phychan_hold--; 1600 waiting->state = PL08X_CHAN_RUNNING; 1601 waiting->waiting = NULL; 1602 pl08x_issue_pending(&waiting->chan); 1603 break; 1604 } 1605 } 1606 } 1607 1608 spin_unlock_irqrestore(&plchan->lock, flags); 1609 1610 if (txd) { 1611 dma_async_tx_callback callback = txd->tx.callback; 1612 void *callback_param = txd->tx.callback_param; 1613 1614 /* Don't try to unmap buffers on slave channels */ 1615 if (!plchan->slave) 1616 pl08x_unmap_buffers(txd); 1617 1618 /* Free the descriptor */ 1619 spin_lock_irqsave(&plchan->lock, flags); 1620 pl08x_free_txd(pl08x, txd); 1621 spin_unlock_irqrestore(&plchan->lock, flags); 1622 1623 /* Callback to signal completion */ 1624 if (callback) 1625 callback(callback_param); 1626 } 1627 } 1628 1629 static irqreturn_t pl08x_irq(int irq, void *dev) 1630 { 1631 struct pl08x_driver_data *pl08x = dev; 1632 u32 mask = 0; 1633 u32 val; 1634 int i; 1635 1636 val = readl(pl08x->base + PL080_ERR_STATUS); 1637 if (val) { 1638 /* An error interrupt (on one or more channels) */ 1639 dev_err(&pl08x->adev->dev, 1640 "%s error interrupt, register value 0x%08x\n", 1641 __func__, val); 1642 /* 1643 * Simply clear ALL PL08X error interrupts, 1644 * regardless of channel and cause 1645 * FIXME: should be 0x00000003 on PL081 really. 1646 */ 1647 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); 1648 } 1649 val = readl(pl08x->base + PL080_INT_STATUS); 1650 for (i = 0; i < pl08x->vd->channels; i++) { 1651 if ((1 << i) & val) { 1652 /* Locate physical channel */ 1653 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; 1654 struct pl08x_dma_chan *plchan = phychan->serving; 1655 1656 /* Schedule tasklet on this channel */ 1657 tasklet_schedule(&plchan->tasklet); 1658 1659 mask |= (1 << i); 1660 } 1661 } 1662 /* Clear only the terminal interrupts on channels we processed */ 1663 writel(mask, pl08x->base + PL080_TC_CLEAR); 1664 1665 return mask ? IRQ_HANDLED : IRQ_NONE; 1666 } 1667 1668 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) 1669 { 1670 u32 cctl = pl08x_cctl(chan->cd->cctl); 1671 1672 chan->slave = true; 1673 chan->name = chan->cd->bus_id; 1674 chan->src_addr = chan->cd->addr; 1675 chan->dst_addr = chan->cd->addr; 1676 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR | 1677 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses); 1678 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR | 1679 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses); 1680 } 1681 1682 /* 1683 * Initialise the DMAC memcpy/slave channels. 1684 * Make a local wrapper to hold required data 1685 */ 1686 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, 1687 struct dma_device *dmadev, 1688 unsigned int channels, 1689 bool slave) 1690 { 1691 struct pl08x_dma_chan *chan; 1692 int i; 1693 1694 INIT_LIST_HEAD(&dmadev->channels); 1695 1696 /* 1697 * Register as many many memcpy as we have physical channels, 1698 * we won't always be able to use all but the code will have 1699 * to cope with that situation. 1700 */ 1701 for (i = 0; i < channels; i++) { 1702 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL); 1703 if (!chan) { 1704 dev_err(&pl08x->adev->dev, 1705 "%s no memory for channel\n", __func__); 1706 return -ENOMEM; 1707 } 1708 1709 chan->host = pl08x; 1710 chan->state = PL08X_CHAN_IDLE; 1711 1712 if (slave) { 1713 chan->cd = &pl08x->pd->slave_channels[i]; 1714 pl08x_dma_slave_init(chan); 1715 } else { 1716 chan->cd = &pl08x->pd->memcpy_channel; 1717 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); 1718 if (!chan->name) { 1719 kfree(chan); 1720 return -ENOMEM; 1721 } 1722 } 1723 if (chan->cd->circular_buffer) { 1724 dev_err(&pl08x->adev->dev, 1725 "channel %s: circular buffers not supported\n", 1726 chan->name); 1727 kfree(chan); 1728 continue; 1729 } 1730 dev_info(&pl08x->adev->dev, 1731 "initialize virtual channel \"%s\"\n", 1732 chan->name); 1733 1734 chan->chan.device = dmadev; 1735 chan->chan.cookie = 0; 1736 chan->lc = 0; 1737 1738 spin_lock_init(&chan->lock); 1739 INIT_LIST_HEAD(&chan->pend_list); 1740 tasklet_init(&chan->tasklet, pl08x_tasklet, 1741 (unsigned long) chan); 1742 1743 list_add_tail(&chan->chan.device_node, &dmadev->channels); 1744 } 1745 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", 1746 i, slave ? "slave" : "memcpy"); 1747 return i; 1748 } 1749 1750 static void pl08x_free_virtual_channels(struct dma_device *dmadev) 1751 { 1752 struct pl08x_dma_chan *chan = NULL; 1753 struct pl08x_dma_chan *next; 1754 1755 list_for_each_entry_safe(chan, 1756 next, &dmadev->channels, chan.device_node) { 1757 list_del(&chan->chan.device_node); 1758 kfree(chan); 1759 } 1760 } 1761 1762 #ifdef CONFIG_DEBUG_FS 1763 static const char *pl08x_state_str(enum pl08x_dma_chan_state state) 1764 { 1765 switch (state) { 1766 case PL08X_CHAN_IDLE: 1767 return "idle"; 1768 case PL08X_CHAN_RUNNING: 1769 return "running"; 1770 case PL08X_CHAN_PAUSED: 1771 return "paused"; 1772 case PL08X_CHAN_WAITING: 1773 return "waiting"; 1774 default: 1775 break; 1776 } 1777 return "UNKNOWN STATE"; 1778 } 1779 1780 static int pl08x_debugfs_show(struct seq_file *s, void *data) 1781 { 1782 struct pl08x_driver_data *pl08x = s->private; 1783 struct pl08x_dma_chan *chan; 1784 struct pl08x_phy_chan *ch; 1785 unsigned long flags; 1786 int i; 1787 1788 seq_printf(s, "PL08x physical channels:\n"); 1789 seq_printf(s, "CHANNEL:\tUSER:\n"); 1790 seq_printf(s, "--------\t-----\n"); 1791 for (i = 0; i < pl08x->vd->channels; i++) { 1792 struct pl08x_dma_chan *virt_chan; 1793 1794 ch = &pl08x->phy_chans[i]; 1795 1796 spin_lock_irqsave(&ch->lock, flags); 1797 virt_chan = ch->serving; 1798 1799 seq_printf(s, "%d\t\t%s\n", 1800 ch->id, virt_chan ? virt_chan->name : "(none)"); 1801 1802 spin_unlock_irqrestore(&ch->lock, flags); 1803 } 1804 1805 seq_printf(s, "\nPL08x virtual memcpy channels:\n"); 1806 seq_printf(s, "CHANNEL:\tSTATE:\n"); 1807 seq_printf(s, "--------\t------\n"); 1808 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) { 1809 seq_printf(s, "%s\t\t%s\n", chan->name, 1810 pl08x_state_str(chan->state)); 1811 } 1812 1813 seq_printf(s, "\nPL08x virtual slave channels:\n"); 1814 seq_printf(s, "CHANNEL:\tSTATE:\n"); 1815 seq_printf(s, "--------\t------\n"); 1816 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) { 1817 seq_printf(s, "%s\t\t%s\n", chan->name, 1818 pl08x_state_str(chan->state)); 1819 } 1820 1821 return 0; 1822 } 1823 1824 static int pl08x_debugfs_open(struct inode *inode, struct file *file) 1825 { 1826 return single_open(file, pl08x_debugfs_show, inode->i_private); 1827 } 1828 1829 static const struct file_operations pl08x_debugfs_operations = { 1830 .open = pl08x_debugfs_open, 1831 .read = seq_read, 1832 .llseek = seq_lseek, 1833 .release = single_release, 1834 }; 1835 1836 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) 1837 { 1838 /* Expose a simple debugfs interface to view all clocks */ 1839 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO, 1840 NULL, pl08x, 1841 &pl08x_debugfs_operations); 1842 } 1843 1844 #else 1845 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) 1846 { 1847 } 1848 #endif 1849 1850 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) 1851 { 1852 struct pl08x_driver_data *pl08x; 1853 const struct vendor_data *vd = id->data; 1854 int ret = 0; 1855 int i; 1856 1857 ret = amba_request_regions(adev, NULL); 1858 if (ret) 1859 return ret; 1860 1861 /* Create the driver state holder */ 1862 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL); 1863 if (!pl08x) { 1864 ret = -ENOMEM; 1865 goto out_no_pl08x; 1866 } 1867 1868 /* Initialize memcpy engine */ 1869 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); 1870 pl08x->memcpy.dev = &adev->dev; 1871 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; 1872 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; 1873 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; 1874 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; 1875 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; 1876 pl08x->memcpy.device_issue_pending = pl08x_issue_pending; 1877 pl08x->memcpy.device_control = pl08x_control; 1878 1879 /* Initialize slave engine */ 1880 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); 1881 pl08x->slave.dev = &adev->dev; 1882 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; 1883 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; 1884 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; 1885 pl08x->slave.device_tx_status = pl08x_dma_tx_status; 1886 pl08x->slave.device_issue_pending = pl08x_issue_pending; 1887 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; 1888 pl08x->slave.device_control = pl08x_control; 1889 1890 /* Get the platform data */ 1891 pl08x->pd = dev_get_platdata(&adev->dev); 1892 if (!pl08x->pd) { 1893 dev_err(&adev->dev, "no platform data supplied\n"); 1894 goto out_no_platdata; 1895 } 1896 1897 /* Assign useful pointers to the driver state */ 1898 pl08x->adev = adev; 1899 pl08x->vd = vd; 1900 1901 /* By default, AHB1 only. If dualmaster, from platform */ 1902 pl08x->lli_buses = PL08X_AHB1; 1903 pl08x->mem_buses = PL08X_AHB1; 1904 if (pl08x->vd->dualmaster) { 1905 pl08x->lli_buses = pl08x->pd->lli_buses; 1906 pl08x->mem_buses = pl08x->pd->mem_buses; 1907 } 1908 1909 /* A DMA memory pool for LLIs, align on 1-byte boundary */ 1910 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, 1911 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); 1912 if (!pl08x->pool) { 1913 ret = -ENOMEM; 1914 goto out_no_lli_pool; 1915 } 1916 1917 spin_lock_init(&pl08x->lock); 1918 1919 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); 1920 if (!pl08x->base) { 1921 ret = -ENOMEM; 1922 goto out_no_ioremap; 1923 } 1924 1925 /* Turn on the PL08x */ 1926 pl08x_ensure_on(pl08x); 1927 1928 /* Attach the interrupt handler */ 1929 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); 1930 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); 1931 1932 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, 1933 DRIVER_NAME, pl08x); 1934 if (ret) { 1935 dev_err(&adev->dev, "%s failed to request interrupt %d\n", 1936 __func__, adev->irq[0]); 1937 goto out_no_irq; 1938 } 1939 1940 /* Initialize physical channels */ 1941 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)), 1942 GFP_KERNEL); 1943 if (!pl08x->phy_chans) { 1944 dev_err(&adev->dev, "%s failed to allocate " 1945 "physical channel holders\n", 1946 __func__); 1947 goto out_no_phychans; 1948 } 1949 1950 for (i = 0; i < vd->channels; i++) { 1951 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; 1952 1953 ch->id = i; 1954 ch->base = pl08x->base + PL080_Cx_BASE(i); 1955 spin_lock_init(&ch->lock); 1956 ch->serving = NULL; 1957 ch->signal = -1; 1958 dev_info(&adev->dev, 1959 "physical channel %d is %s\n", i, 1960 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); 1961 } 1962 1963 /* Register as many memcpy channels as there are physical channels */ 1964 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, 1965 pl08x->vd->channels, false); 1966 if (ret <= 0) { 1967 dev_warn(&pl08x->adev->dev, 1968 "%s failed to enumerate memcpy channels - %d\n", 1969 __func__, ret); 1970 goto out_no_memcpy; 1971 } 1972 pl08x->memcpy.chancnt = ret; 1973 1974 /* Register slave channels */ 1975 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, 1976 pl08x->pd->num_slave_channels, 1977 true); 1978 if (ret <= 0) { 1979 dev_warn(&pl08x->adev->dev, 1980 "%s failed to enumerate slave channels - %d\n", 1981 __func__, ret); 1982 goto out_no_slave; 1983 } 1984 pl08x->slave.chancnt = ret; 1985 1986 ret = dma_async_device_register(&pl08x->memcpy); 1987 if (ret) { 1988 dev_warn(&pl08x->adev->dev, 1989 "%s failed to register memcpy as an async device - %d\n", 1990 __func__, ret); 1991 goto out_no_memcpy_reg; 1992 } 1993 1994 ret = dma_async_device_register(&pl08x->slave); 1995 if (ret) { 1996 dev_warn(&pl08x->adev->dev, 1997 "%s failed to register slave as an async device - %d\n", 1998 __func__, ret); 1999 goto out_no_slave_reg; 2000 } 2001 2002 amba_set_drvdata(adev, pl08x); 2003 init_pl08x_debugfs(pl08x); 2004 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", 2005 amba_part(adev), amba_rev(adev), 2006 (unsigned long long)adev->res.start, adev->irq[0]); 2007 return 0; 2008 2009 out_no_slave_reg: 2010 dma_async_device_unregister(&pl08x->memcpy); 2011 out_no_memcpy_reg: 2012 pl08x_free_virtual_channels(&pl08x->slave); 2013 out_no_slave: 2014 pl08x_free_virtual_channels(&pl08x->memcpy); 2015 out_no_memcpy: 2016 kfree(pl08x->phy_chans); 2017 out_no_phychans: 2018 free_irq(adev->irq[0], pl08x); 2019 out_no_irq: 2020 iounmap(pl08x->base); 2021 out_no_ioremap: 2022 dma_pool_destroy(pl08x->pool); 2023 out_no_lli_pool: 2024 out_no_platdata: 2025 kfree(pl08x); 2026 out_no_pl08x: 2027 amba_release_regions(adev); 2028 return ret; 2029 } 2030 2031 /* PL080 has 8 channels and the PL080 have just 2 */ 2032 static struct vendor_data vendor_pl080 = { 2033 .channels = 8, 2034 .dualmaster = true, 2035 }; 2036 2037 static struct vendor_data vendor_pl081 = { 2038 .channels = 2, 2039 .dualmaster = false, 2040 }; 2041 2042 static struct amba_id pl08x_ids[] = { 2043 /* PL080 */ 2044 { 2045 .id = 0x00041080, 2046 .mask = 0x000fffff, 2047 .data = &vendor_pl080, 2048 }, 2049 /* PL081 */ 2050 { 2051 .id = 0x00041081, 2052 .mask = 0x000fffff, 2053 .data = &vendor_pl081, 2054 }, 2055 /* Nomadik 8815 PL080 variant */ 2056 { 2057 .id = 0x00280880, 2058 .mask = 0x00ffffff, 2059 .data = &vendor_pl080, 2060 }, 2061 { 0, 0 }, 2062 }; 2063 2064 static struct amba_driver pl08x_amba_driver = { 2065 .drv.name = DRIVER_NAME, 2066 .id_table = pl08x_ids, 2067 .probe = pl08x_probe, 2068 }; 2069 2070 static int __init pl08x_init(void) 2071 { 2072 int retval; 2073 retval = amba_driver_register(&pl08x_amba_driver); 2074 if (retval) 2075 printk(KERN_WARNING DRIVER_NAME 2076 "failed to register as an AMBA device (%d)\n", 2077 retval); 2078 return retval; 2079 } 2080 subsys_initcall(pl08x_init); 2081