1# 2# DMA engine configuration 3# 4 5menuconfig DMADEVICES 6 bool "DMA Engine support" 7 depends on !HIGHMEM64G && HAS_DMA 8 help 9 DMA engines can do asynchronous data transfers without 10 involving the host CPU. Currently, this framework can be 11 used to offload memory copies in the network stack and 12 RAID operations in the MD driver. This menu only presents 13 DMA Device drivers supported by the configured arch, it may 14 be empty in some cases. 15 16if DMADEVICES 17 18comment "DMA Devices" 19 20config INTEL_IOATDMA 21 tristate "Intel I/OAT DMA support" 22 depends on PCI && X86 23 select DMA_ENGINE 24 select DCA 25 help 26 Enable support for the Intel(R) I/OAT DMA engine present 27 in recent Intel Xeon chipsets. 28 29 Say Y here if you have such a chipset. 30 31 If unsure, say N. 32 33config INTEL_IOP_ADMA 34 tristate "Intel IOP ADMA support" 35 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX 36 select DMA_ENGINE 37 help 38 Enable support for the Intel(R) IOP Series RAID engines. 39 40config DW_DMAC 41 tristate "Synopsys DesignWare AHB DMA support" 42 depends on AVR32 43 select DMA_ENGINE 44 default y if CPU_AT32AP7000 45 help 46 Support the Synopsys DesignWare AHB DMA controller. This 47 can be integrated in chips such as the Atmel AT32ap7000. 48 49config FSL_DMA 50 tristate "Freescale Elo and Elo Plus DMA support" 51 depends on FSL_SOC 52 select DMA_ENGINE 53 ---help--- 54 Enable support for the Freescale Elo and Elo Plus DMA controllers. 55 The Elo is the DMA controller on some 82xx and 83xx parts, and the 56 Elo Plus is the DMA controller on 85xx and 86xx parts. 57 58config MV_XOR 59 bool "Marvell XOR engine support" 60 depends on PLAT_ORION 61 select DMA_ENGINE 62 ---help--- 63 Enable support for the Marvell XOR engine. 64 65config MX3_IPU 66 bool "MX3x Image Processing Unit support" 67 depends on ARCH_MX3 68 select DMA_ENGINE 69 default y 70 help 71 If you plan to use the Image Processing unit in the i.MX3x, say 72 Y here. If unsure, select Y. 73 74config MX3_IPU_IRQS 75 int "Number of dynamically mapped interrupts for IPU" 76 depends on MX3_IPU 77 range 2 137 78 default 4 79 help 80 Out of 137 interrupt sources on i.MX31 IPU only very few are used. 81 To avoid bloating the irq_desc[] array we allocate a sufficient 82 number of IRQ slots and map them dynamically to specific sources. 83 84config TXX9_DMAC 85 tristate "Toshiba TXx9 SoC DMA support" 86 depends on MACH_TX49XX || MACH_TX39XX 87 select DMA_ENGINE 88 help 89 Support the TXx9 SoC internal DMA controller. This can be 90 integrated in chips such as the Toshiba TX4927/38/39. 91 92config DMA_ENGINE 93 bool 94 95comment "DMA Clients" 96 depends on DMA_ENGINE 97 98config NET_DMA 99 bool "Network: TCP receive copy offload" 100 depends on DMA_ENGINE && NET 101 default (INTEL_IOATDMA || FSL_DMA) 102 help 103 This enables the use of DMA engines in the network stack to 104 offload receive copy-to-user operations, freeing CPU cycles. 105 106 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise 107 say N. 108 109config ASYNC_TX_DMA 110 bool "Async_tx: Offload support for the async_tx api" 111 depends on DMA_ENGINE 112 help 113 This allows the async_tx api to take advantage of offload engines for 114 memcpy, memset, xor, and raid6 p+q operations. If your platform has 115 a dma engine that can perform raid operations and you have enabled 116 MD_RAID456 say Y. 117 118 If unsure, say N. 119 120config DMATEST 121 tristate "DMA Test client" 122 depends on DMA_ENGINE 123 help 124 Simple DMA test client. Say N unless you're debugging a 125 DMA Device driver. 126 127endif 128