1# 2# DMA engine configuration 3# 4 5menuconfig DMADEVICES 6 bool "DMA Engine support" 7 depends on HAS_DMA 8 help 9 DMA engines can do asynchronous data transfers without 10 involving the host CPU. Currently, this framework can be 11 used to offload memory copies in the network stack and 12 RAID operations in the MD driver. This menu only presents 13 DMA Device drivers supported by the configured arch, it may 14 be empty in some cases. 15 16if DMADEVICES 17 18comment "DMA Devices" 19 20config INTEL_IOATDMA 21 tristate "Intel I/OAT DMA support" 22 depends on PCI && X86 23 select DMA_ENGINE 24 select DCA 25 help 26 Enable support for the Intel(R) I/OAT DMA engine present 27 in recent Intel Xeon chipsets. 28 29 Say Y here if you have such a chipset. 30 31 If unsure, say N. 32 33config INTEL_IOP_ADMA 34 tristate "Intel IOP ADMA support" 35 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX 36 select DMA_ENGINE 37 help 38 Enable support for the Intel(R) IOP Series RAID engines. 39 40config DW_DMAC 41 tristate "Synopsys DesignWare AHB DMA support" 42 depends on AVR32 43 select DMA_ENGINE 44 default y if CPU_AT32AP7000 45 help 46 Support the Synopsys DesignWare AHB DMA controller. This 47 can be integrated in chips such as the Atmel AT32ap7000. 48 49config AT_HDMAC 50 tristate "Atmel AHB DMA support" 51 depends on ARCH_AT91SAM9RL 52 select DMA_ENGINE 53 help 54 Support the Atmel AHB DMA controller. This can be integrated in 55 chips such as the Atmel AT91SAM9RL. 56 57config FSL_DMA 58 tristate "Freescale Elo and Elo Plus DMA support" 59 depends on FSL_SOC 60 select DMA_ENGINE 61 ---help--- 62 Enable support for the Freescale Elo and Elo Plus DMA controllers. 63 The Elo is the DMA controller on some 82xx and 83xx parts, and the 64 Elo Plus is the DMA controller on 85xx and 86xx parts. 65 66config MV_XOR 67 bool "Marvell XOR engine support" 68 depends on PLAT_ORION 69 select DMA_ENGINE 70 ---help--- 71 Enable support for the Marvell XOR engine. 72 73config MX3_IPU 74 bool "MX3x Image Processing Unit support" 75 depends on ARCH_MX3 76 select DMA_ENGINE 77 default y 78 help 79 If you plan to use the Image Processing unit in the i.MX3x, say 80 Y here. If unsure, select Y. 81 82config MX3_IPU_IRQS 83 int "Number of dynamically mapped interrupts for IPU" 84 depends on MX3_IPU 85 range 2 137 86 default 4 87 help 88 Out of 137 interrupt sources on i.MX31 IPU only very few are used. 89 To avoid bloating the irq_desc[] array we allocate a sufficient 90 number of IRQ slots and map them dynamically to specific sources. 91 92config TXX9_DMAC 93 tristate "Toshiba TXx9 SoC DMA support" 94 depends on MACH_TX49XX || MACH_TX39XX 95 select DMA_ENGINE 96 help 97 Support the TXx9 SoC internal DMA controller. This can be 98 integrated in chips such as the Toshiba TX4927/38/39. 99 100config DMA_ENGINE 101 bool 102 103comment "DMA Clients" 104 depends on DMA_ENGINE 105 106config NET_DMA 107 bool "Network: TCP receive copy offload" 108 depends on DMA_ENGINE && NET 109 default (INTEL_IOATDMA || FSL_DMA) 110 help 111 This enables the use of DMA engines in the network stack to 112 offload receive copy-to-user operations, freeing CPU cycles. 113 114 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise 115 say N. 116 117config ASYNC_TX_DMA 118 bool "Async_tx: Offload support for the async_tx api" 119 depends on DMA_ENGINE && !HIGHMEM64G 120 help 121 This allows the async_tx api to take advantage of offload engines for 122 memcpy, memset, xor, and raid6 p+q operations. If your platform has 123 a dma engine that can perform raid operations and you have enabled 124 MD_RAID456 say Y. 125 126 If unsure, say N. 127 128config DMATEST 129 tristate "DMA Test client" 130 depends on DMA_ENGINE 131 help 132 Simple DMA test client. Say N unless you're debugging a 133 DMA Device driver. 134 135endif 136