123601752SDmitry Osipenko // SPDX-License-Identifier: GPL-2.0-only 223601752SDmitry Osipenko /* 323601752SDmitry Osipenko * A devfreq driver for NVIDIA Tegra SoCs 423601752SDmitry Osipenko * 523601752SDmitry Osipenko * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved. 623601752SDmitry Osipenko * Copyright (C) 2014 Google, Inc 723601752SDmitry Osipenko */ 823601752SDmitry Osipenko 923601752SDmitry Osipenko #include <linux/clk.h> 1023601752SDmitry Osipenko #include <linux/cpufreq.h> 1123601752SDmitry Osipenko #include <linux/devfreq.h> 1223601752SDmitry Osipenko #include <linux/interrupt.h> 1323601752SDmitry Osipenko #include <linux/io.h> 14d49eeb1eSDmitry Osipenko #include <linux/irq.h> 1523601752SDmitry Osipenko #include <linux/module.h> 169cff2177SDmitry Osipenko #include <linux/of_device.h> 1723601752SDmitry Osipenko #include <linux/platform_device.h> 1823601752SDmitry Osipenko #include <linux/pm_opp.h> 1923601752SDmitry Osipenko #include <linux/reset.h> 2011eb6ec5SDmitry Osipenko #include <linux/workqueue.h> 2123601752SDmitry Osipenko 2223601752SDmitry Osipenko #include "governor.h" 2323601752SDmitry Osipenko 2423601752SDmitry Osipenko #define ACTMON_GLB_STATUS 0x0 2523601752SDmitry Osipenko #define ACTMON_GLB_PERIOD_CTRL 0x4 2623601752SDmitry Osipenko 2723601752SDmitry Osipenko #define ACTMON_DEV_CTRL 0x0 2823601752SDmitry Osipenko #define ACTMON_DEV_CTRL_K_VAL_SHIFT 10 2923601752SDmitry Osipenko #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18) 3023601752SDmitry Osipenko #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20) 3123601752SDmitry Osipenko #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21) 3223601752SDmitry Osipenko #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT 23 3323601752SDmitry Osipenko #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT 26 3423601752SDmitry Osipenko #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29) 3523601752SDmitry Osipenko #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30) 3623601752SDmitry Osipenko #define ACTMON_DEV_CTRL_ENB BIT(31) 3723601752SDmitry Osipenko 3811eb6ec5SDmitry Osipenko #define ACTMON_DEV_CTRL_STOP 0x00000000 3911eb6ec5SDmitry Osipenko 4023601752SDmitry Osipenko #define ACTMON_DEV_UPPER_WMARK 0x4 4123601752SDmitry Osipenko #define ACTMON_DEV_LOWER_WMARK 0x8 4223601752SDmitry Osipenko #define ACTMON_DEV_INIT_AVG 0xc 4323601752SDmitry Osipenko #define ACTMON_DEV_AVG_UPPER_WMARK 0x10 4423601752SDmitry Osipenko #define ACTMON_DEV_AVG_LOWER_WMARK 0x14 4523601752SDmitry Osipenko #define ACTMON_DEV_COUNT_WEIGHT 0x18 4623601752SDmitry Osipenko #define ACTMON_DEV_AVG_COUNT 0x20 4723601752SDmitry Osipenko #define ACTMON_DEV_INTR_STATUS 0x24 4823601752SDmitry Osipenko 4923601752SDmitry Osipenko #define ACTMON_INTR_STATUS_CLEAR 0xffffffff 5023601752SDmitry Osipenko 5123601752SDmitry Osipenko #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31) 5223601752SDmitry Osipenko #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30) 5323601752SDmitry Osipenko 5423601752SDmitry Osipenko #define ACTMON_ABOVE_WMARK_WINDOW 1 5523601752SDmitry Osipenko #define ACTMON_BELOW_WMARK_WINDOW 3 5623601752SDmitry Osipenko #define ACTMON_BOOST_FREQ_STEP 16000 5723601752SDmitry Osipenko 5823601752SDmitry Osipenko /* 5923601752SDmitry Osipenko * Activity counter is incremented every 256 memory transactions, and each 6023601752SDmitry Osipenko * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is 6123601752SDmitry Osipenko * 4 * 256 = 1024. 6223601752SDmitry Osipenko */ 6323601752SDmitry Osipenko #define ACTMON_COUNT_WEIGHT 0x400 6423601752SDmitry Osipenko 6523601752SDmitry Osipenko /* 6623601752SDmitry Osipenko * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which 6723601752SDmitry Osipenko * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128 6823601752SDmitry Osipenko */ 6923601752SDmitry Osipenko #define ACTMON_AVERAGE_WINDOW_LOG2 6 7023601752SDmitry Osipenko #define ACTMON_SAMPLING_PERIOD 12 /* ms */ 7123601752SDmitry Osipenko #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */ 7223601752SDmitry Osipenko 7323601752SDmitry Osipenko #define KHZ 1000 7423601752SDmitry Osipenko 7553b4b2aeSDmitry Osipenko #define KHZ_MAX (ULONG_MAX / KHZ) 7653b4b2aeSDmitry Osipenko 7723601752SDmitry Osipenko /* Assume that the bus is saturated if the utilization is 25% */ 7823601752SDmitry Osipenko #define BUS_SATURATION_RATIO 25 7923601752SDmitry Osipenko 8023601752SDmitry Osipenko /** 8123601752SDmitry Osipenko * struct tegra_devfreq_device_config - configuration specific to an ACTMON 8223601752SDmitry Osipenko * device 8323601752SDmitry Osipenko * 8423601752SDmitry Osipenko * Coefficients and thresholds are percentages unless otherwise noted 8523601752SDmitry Osipenko */ 8623601752SDmitry Osipenko struct tegra_devfreq_device_config { 8723601752SDmitry Osipenko u32 offset; 8823601752SDmitry Osipenko u32 irq_mask; 8923601752SDmitry Osipenko 9023601752SDmitry Osipenko /* Factors applied to boost_freq every consecutive watermark breach */ 9123601752SDmitry Osipenko unsigned int boost_up_coeff; 9223601752SDmitry Osipenko unsigned int boost_down_coeff; 9323601752SDmitry Osipenko 9423601752SDmitry Osipenko /* Define the watermark bounds when applied to the current avg */ 9523601752SDmitry Osipenko unsigned int boost_up_threshold; 9623601752SDmitry Osipenko unsigned int boost_down_threshold; 9723601752SDmitry Osipenko 9823601752SDmitry Osipenko /* 9928615e37SDmitry Osipenko * Threshold of activity (cycles translated to kHz) below which the 10028615e37SDmitry Osipenko * CPU frequency isn't to be taken into account. This is to avoid 10128615e37SDmitry Osipenko * increasing the EMC frequency when the CPU is very busy but not 10228615e37SDmitry Osipenko * accessing the bus often. 10323601752SDmitry Osipenko */ 10423601752SDmitry Osipenko u32 avg_dependency_threshold; 10523601752SDmitry Osipenko }; 10623601752SDmitry Osipenko 10723601752SDmitry Osipenko enum tegra_actmon_device { 10823601752SDmitry Osipenko MCALL = 0, 10923601752SDmitry Osipenko MCCPU, 11023601752SDmitry Osipenko }; 11123601752SDmitry Osipenko 112b87dea3bSDmitry Osipenko static const struct tegra_devfreq_device_config actmon_device_configs[] = { 11323601752SDmitry Osipenko { 11423601752SDmitry Osipenko /* MCALL: All memory accesses (including from the CPUs) */ 11523601752SDmitry Osipenko .offset = 0x1c0, 11623601752SDmitry Osipenko .irq_mask = 1 << 26, 11723601752SDmitry Osipenko .boost_up_coeff = 200, 11823601752SDmitry Osipenko .boost_down_coeff = 50, 11923601752SDmitry Osipenko .boost_up_threshold = 60, 12023601752SDmitry Osipenko .boost_down_threshold = 40, 12123601752SDmitry Osipenko }, 12223601752SDmitry Osipenko { 12323601752SDmitry Osipenko /* MCCPU: memory accesses from the CPUs */ 12423601752SDmitry Osipenko .offset = 0x200, 12523601752SDmitry Osipenko .irq_mask = 1 << 25, 12623601752SDmitry Osipenko .boost_up_coeff = 800, 127*fee22854SDmitry Osipenko .boost_down_coeff = 40, 12823601752SDmitry Osipenko .boost_up_threshold = 27, 12923601752SDmitry Osipenko .boost_down_threshold = 10, 13028615e37SDmitry Osipenko .avg_dependency_threshold = 16000, /* 16MHz in kHz units */ 13123601752SDmitry Osipenko }, 13223601752SDmitry Osipenko }; 13323601752SDmitry Osipenko 13423601752SDmitry Osipenko /** 13523601752SDmitry Osipenko * struct tegra_devfreq_device - state specific to an ACTMON device 13623601752SDmitry Osipenko * 13723601752SDmitry Osipenko * Frequencies are in kHz. 13823601752SDmitry Osipenko */ 13923601752SDmitry Osipenko struct tegra_devfreq_device { 14023601752SDmitry Osipenko const struct tegra_devfreq_device_config *config; 14123601752SDmitry Osipenko void __iomem *regs; 14223601752SDmitry Osipenko 14323601752SDmitry Osipenko /* Average event count sampled in the last interrupt */ 14423601752SDmitry Osipenko u32 avg_count; 14523601752SDmitry Osipenko 14623601752SDmitry Osipenko /* 14723601752SDmitry Osipenko * Extra frequency to increase the target by due to consecutive 14823601752SDmitry Osipenko * watermark breaches. 14923601752SDmitry Osipenko */ 15023601752SDmitry Osipenko unsigned long boost_freq; 15123601752SDmitry Osipenko 15223601752SDmitry Osipenko /* Optimal frequency calculated from the stats for this device */ 15323601752SDmitry Osipenko unsigned long target_freq; 15423601752SDmitry Osipenko }; 15523601752SDmitry Osipenko 15623601752SDmitry Osipenko struct tegra_devfreq { 15723601752SDmitry Osipenko struct devfreq *devfreq; 15823601752SDmitry Osipenko 15923601752SDmitry Osipenko struct reset_control *reset; 16023601752SDmitry Osipenko struct clk *clock; 16123601752SDmitry Osipenko void __iomem *regs; 16223601752SDmitry Osipenko 16323601752SDmitry Osipenko struct clk *emc_clock; 16423601752SDmitry Osipenko unsigned long max_freq; 16523601752SDmitry Osipenko unsigned long cur_freq; 16611eb6ec5SDmitry Osipenko struct notifier_block clk_rate_change_nb; 16711eb6ec5SDmitry Osipenko 16811eb6ec5SDmitry Osipenko struct delayed_work cpufreq_update_work; 16911eb6ec5SDmitry Osipenko struct notifier_block cpu_rate_change_nb; 17023601752SDmitry Osipenko 17123601752SDmitry Osipenko struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)]; 17223601752SDmitry Osipenko 173dccdea01SDmitry Osipenko unsigned int irq; 174f61ee201SDmitry Osipenko 175f61ee201SDmitry Osipenko bool started; 17623601752SDmitry Osipenko }; 17723601752SDmitry Osipenko 17823601752SDmitry Osipenko struct tegra_actmon_emc_ratio { 17923601752SDmitry Osipenko unsigned long cpu_freq; 18023601752SDmitry Osipenko unsigned long emc_freq; 18123601752SDmitry Osipenko }; 18223601752SDmitry Osipenko 183b87dea3bSDmitry Osipenko static const struct tegra_actmon_emc_ratio actmon_emc_ratios[] = { 18453b4b2aeSDmitry Osipenko { 1400000, KHZ_MAX }, 18523601752SDmitry Osipenko { 1200000, 750000 }, 18623601752SDmitry Osipenko { 1100000, 600000 }, 18723601752SDmitry Osipenko { 1000000, 500000 }, 18823601752SDmitry Osipenko { 800000, 375000 }, 18923601752SDmitry Osipenko { 500000, 200000 }, 19023601752SDmitry Osipenko { 250000, 100000 }, 19123601752SDmitry Osipenko }; 19223601752SDmitry Osipenko 19323601752SDmitry Osipenko static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset) 19423601752SDmitry Osipenko { 19523601752SDmitry Osipenko return readl_relaxed(tegra->regs + offset); 19623601752SDmitry Osipenko } 19723601752SDmitry Osipenko 19823601752SDmitry Osipenko static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset) 19923601752SDmitry Osipenko { 20023601752SDmitry Osipenko writel_relaxed(val, tegra->regs + offset); 20123601752SDmitry Osipenko } 20223601752SDmitry Osipenko 20323601752SDmitry Osipenko static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset) 20423601752SDmitry Osipenko { 20523601752SDmitry Osipenko return readl_relaxed(dev->regs + offset); 20623601752SDmitry Osipenko } 20723601752SDmitry Osipenko 20823601752SDmitry Osipenko static void device_writel(struct tegra_devfreq_device *dev, u32 val, 20923601752SDmitry Osipenko u32 offset) 21023601752SDmitry Osipenko { 21123601752SDmitry Osipenko writel_relaxed(val, dev->regs + offset); 21223601752SDmitry Osipenko } 21323601752SDmitry Osipenko 214f61ee201SDmitry Osipenko static unsigned long do_percent(unsigned long long val, unsigned int pct) 21523601752SDmitry Osipenko { 216f61ee201SDmitry Osipenko val = val * pct; 217f61ee201SDmitry Osipenko do_div(val, 100); 218f61ee201SDmitry Osipenko 219f61ee201SDmitry Osipenko /* 220f61ee201SDmitry Osipenko * High freq + high boosting percent + large polling interval are 221f61ee201SDmitry Osipenko * resulting in integer overflow when watermarks are calculated. 222f61ee201SDmitry Osipenko */ 223f61ee201SDmitry Osipenko return min_t(u64, val, U32_MAX); 22423601752SDmitry Osipenko } 22523601752SDmitry Osipenko 22623601752SDmitry Osipenko static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra, 22723601752SDmitry Osipenko struct tegra_devfreq_device *dev) 22823601752SDmitry Osipenko { 22923601752SDmitry Osipenko u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; 230f61ee201SDmitry Osipenko u32 band = avg_band_freq * tegra->devfreq->profile->polling_ms; 231f61ee201SDmitry Osipenko u32 avg; 23223601752SDmitry Osipenko 233f61ee201SDmitry Osipenko avg = min(dev->avg_count, U32_MAX - band); 23423601752SDmitry Osipenko device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK); 23523601752SDmitry Osipenko 23623601752SDmitry Osipenko avg = max(dev->avg_count, band); 23723601752SDmitry Osipenko device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK); 23823601752SDmitry Osipenko } 23923601752SDmitry Osipenko 24023601752SDmitry Osipenko static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra, 24123601752SDmitry Osipenko struct tegra_devfreq_device *dev) 24223601752SDmitry Osipenko { 243f61ee201SDmitry Osipenko u32 val = tegra->cur_freq * tegra->devfreq->profile->polling_ms; 24423601752SDmitry Osipenko 24523601752SDmitry Osipenko device_writel(dev, do_percent(val, dev->config->boost_up_threshold), 24623601752SDmitry Osipenko ACTMON_DEV_UPPER_WMARK); 24723601752SDmitry Osipenko 24823601752SDmitry Osipenko device_writel(dev, do_percent(val, dev->config->boost_down_threshold), 24923601752SDmitry Osipenko ACTMON_DEV_LOWER_WMARK); 25023601752SDmitry Osipenko } 25123601752SDmitry Osipenko 25223601752SDmitry Osipenko static void actmon_isr_device(struct tegra_devfreq *tegra, 25323601752SDmitry Osipenko struct tegra_devfreq_device *dev) 25423601752SDmitry Osipenko { 25523601752SDmitry Osipenko u32 intr_status, dev_ctrl; 25623601752SDmitry Osipenko 25723601752SDmitry Osipenko dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT); 25823601752SDmitry Osipenko tegra_devfreq_update_avg_wmark(tegra, dev); 25923601752SDmitry Osipenko 26023601752SDmitry Osipenko intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS); 26123601752SDmitry Osipenko dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL); 26223601752SDmitry Osipenko 26323601752SDmitry Osipenko if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) { 26423601752SDmitry Osipenko /* 26523601752SDmitry Osipenko * new_boost = min(old_boost * up_coef + step, max_freq) 26623601752SDmitry Osipenko */ 26723601752SDmitry Osipenko dev->boost_freq = do_percent(dev->boost_freq, 26823601752SDmitry Osipenko dev->config->boost_up_coeff); 26923601752SDmitry Osipenko dev->boost_freq += ACTMON_BOOST_FREQ_STEP; 27023601752SDmitry Osipenko 27123601752SDmitry Osipenko dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; 27223601752SDmitry Osipenko 27388ec8164SDmitry Osipenko if (dev->boost_freq >= tegra->max_freq) { 27488ec8164SDmitry Osipenko dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; 27523601752SDmitry Osipenko dev->boost_freq = tegra->max_freq; 27688ec8164SDmitry Osipenko } 27723601752SDmitry Osipenko } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) { 27823601752SDmitry Osipenko /* 27923601752SDmitry Osipenko * new_boost = old_boost * down_coef 28023601752SDmitry Osipenko * or 0 if (old_boost * down_coef < step / 2) 28123601752SDmitry Osipenko */ 28223601752SDmitry Osipenko dev->boost_freq = do_percent(dev->boost_freq, 28323601752SDmitry Osipenko dev->config->boost_down_coeff); 28423601752SDmitry Osipenko 28523601752SDmitry Osipenko dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; 28623601752SDmitry Osipenko 28788ec8164SDmitry Osipenko if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1)) { 28888ec8164SDmitry Osipenko dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; 28923601752SDmitry Osipenko dev->boost_freq = 0; 29023601752SDmitry Osipenko } 29123601752SDmitry Osipenko } 29223601752SDmitry Osipenko 29323601752SDmitry Osipenko device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL); 29423601752SDmitry Osipenko 29523601752SDmitry Osipenko device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); 29623601752SDmitry Osipenko } 29723601752SDmitry Osipenko 29823601752SDmitry Osipenko static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra, 29923601752SDmitry Osipenko unsigned long cpu_freq) 30023601752SDmitry Osipenko { 30123601752SDmitry Osipenko unsigned int i; 302b87dea3bSDmitry Osipenko const struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios; 30323601752SDmitry Osipenko 30423601752SDmitry Osipenko for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) { 30523601752SDmitry Osipenko if (cpu_freq >= ratio->cpu_freq) { 30623601752SDmitry Osipenko if (ratio->emc_freq >= tegra->max_freq) 30723601752SDmitry Osipenko return tegra->max_freq; 30823601752SDmitry Osipenko else 30923601752SDmitry Osipenko return ratio->emc_freq; 31023601752SDmitry Osipenko } 31123601752SDmitry Osipenko } 31223601752SDmitry Osipenko 31323601752SDmitry Osipenko return 0; 31423601752SDmitry Osipenko } 31523601752SDmitry Osipenko 31611eb6ec5SDmitry Osipenko static unsigned long actmon_device_target_freq(struct tegra_devfreq *tegra, 31711eb6ec5SDmitry Osipenko struct tegra_devfreq_device *dev) 31811eb6ec5SDmitry Osipenko { 31911eb6ec5SDmitry Osipenko unsigned int avg_sustain_coef; 32011eb6ec5SDmitry Osipenko unsigned long target_freq; 32111eb6ec5SDmitry Osipenko 322f61ee201SDmitry Osipenko target_freq = dev->avg_count / tegra->devfreq->profile->polling_ms; 32311eb6ec5SDmitry Osipenko avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold; 32411eb6ec5SDmitry Osipenko target_freq = do_percent(target_freq, avg_sustain_coef); 32511eb6ec5SDmitry Osipenko 32611eb6ec5SDmitry Osipenko return target_freq; 32711eb6ec5SDmitry Osipenko } 32811eb6ec5SDmitry Osipenko 32923601752SDmitry Osipenko static void actmon_update_target(struct tegra_devfreq *tegra, 33023601752SDmitry Osipenko struct tegra_devfreq_device *dev) 33123601752SDmitry Osipenko { 33223601752SDmitry Osipenko unsigned long cpu_freq = 0; 33323601752SDmitry Osipenko unsigned long static_cpu_emc_freq = 0; 33423601752SDmitry Osipenko 33511eb6ec5SDmitry Osipenko dev->target_freq = actmon_device_target_freq(tegra, dev); 33623601752SDmitry Osipenko 33728615e37SDmitry Osipenko if (dev->config->avg_dependency_threshold && 33828615e37SDmitry Osipenko dev->config->avg_dependency_threshold <= dev->target_freq) { 33928615e37SDmitry Osipenko cpu_freq = cpufreq_quick_get(0); 34028615e37SDmitry Osipenko static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq); 34128615e37SDmitry Osipenko 34228615e37SDmitry Osipenko dev->target_freq += dev->boost_freq; 34323601752SDmitry Osipenko dev->target_freq = max(dev->target_freq, static_cpu_emc_freq); 34428615e37SDmitry Osipenko } else { 34528615e37SDmitry Osipenko dev->target_freq += dev->boost_freq; 34628615e37SDmitry Osipenko } 34723601752SDmitry Osipenko } 34823601752SDmitry Osipenko 34923601752SDmitry Osipenko static irqreturn_t actmon_thread_isr(int irq, void *data) 35023601752SDmitry Osipenko { 35123601752SDmitry Osipenko struct tegra_devfreq *tegra = data; 35223601752SDmitry Osipenko bool handled = false; 35323601752SDmitry Osipenko unsigned int i; 35423601752SDmitry Osipenko u32 val; 35523601752SDmitry Osipenko 35623601752SDmitry Osipenko mutex_lock(&tegra->devfreq->lock); 35723601752SDmitry Osipenko 35823601752SDmitry Osipenko val = actmon_readl(tegra, ACTMON_GLB_STATUS); 35923601752SDmitry Osipenko for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { 36023601752SDmitry Osipenko if (val & tegra->devices[i].config->irq_mask) { 36123601752SDmitry Osipenko actmon_isr_device(tegra, tegra->devices + i); 36223601752SDmitry Osipenko handled = true; 36323601752SDmitry Osipenko } 36423601752SDmitry Osipenko } 36523601752SDmitry Osipenko 36623601752SDmitry Osipenko if (handled) 36723601752SDmitry Osipenko update_devfreq(tegra->devfreq); 36823601752SDmitry Osipenko 36923601752SDmitry Osipenko mutex_unlock(&tegra->devfreq->lock); 37023601752SDmitry Osipenko 37123601752SDmitry Osipenko return handled ? IRQ_HANDLED : IRQ_NONE; 37223601752SDmitry Osipenko } 37323601752SDmitry Osipenko 37411eb6ec5SDmitry Osipenko static int tegra_actmon_clk_notify_cb(struct notifier_block *nb, 37523601752SDmitry Osipenko unsigned long action, void *ptr) 37623601752SDmitry Osipenko { 37723601752SDmitry Osipenko struct clk_notifier_data *data = ptr; 37823601752SDmitry Osipenko struct tegra_devfreq *tegra; 37923601752SDmitry Osipenko struct tegra_devfreq_device *dev; 38023601752SDmitry Osipenko unsigned int i; 38123601752SDmitry Osipenko 38223601752SDmitry Osipenko if (action != POST_RATE_CHANGE) 38323601752SDmitry Osipenko return NOTIFY_OK; 38423601752SDmitry Osipenko 38511eb6ec5SDmitry Osipenko tegra = container_of(nb, struct tegra_devfreq, clk_rate_change_nb); 38623601752SDmitry Osipenko 38723601752SDmitry Osipenko tegra->cur_freq = data->new_rate / KHZ; 38823601752SDmitry Osipenko 38923601752SDmitry Osipenko for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { 39023601752SDmitry Osipenko dev = &tegra->devices[i]; 39123601752SDmitry Osipenko 39223601752SDmitry Osipenko tegra_devfreq_update_wmark(tegra, dev); 39323601752SDmitry Osipenko } 39423601752SDmitry Osipenko 39523601752SDmitry Osipenko return NOTIFY_OK; 39623601752SDmitry Osipenko } 39723601752SDmitry Osipenko 39811eb6ec5SDmitry Osipenko static void tegra_actmon_delayed_update(struct work_struct *work) 39911eb6ec5SDmitry Osipenko { 40011eb6ec5SDmitry Osipenko struct tegra_devfreq *tegra = container_of(work, struct tegra_devfreq, 40111eb6ec5SDmitry Osipenko cpufreq_update_work.work); 40211eb6ec5SDmitry Osipenko 40311eb6ec5SDmitry Osipenko mutex_lock(&tegra->devfreq->lock); 40411eb6ec5SDmitry Osipenko update_devfreq(tegra->devfreq); 40511eb6ec5SDmitry Osipenko mutex_unlock(&tegra->devfreq->lock); 40611eb6ec5SDmitry Osipenko } 40711eb6ec5SDmitry Osipenko 40811eb6ec5SDmitry Osipenko static unsigned long 40911eb6ec5SDmitry Osipenko tegra_actmon_cpufreq_contribution(struct tegra_devfreq *tegra, 41011eb6ec5SDmitry Osipenko unsigned int cpu_freq) 41111eb6ec5SDmitry Osipenko { 41228615e37SDmitry Osipenko struct tegra_devfreq_device *actmon_dev = &tegra->devices[MCCPU]; 41311eb6ec5SDmitry Osipenko unsigned long static_cpu_emc_freq, dev_freq; 41411eb6ec5SDmitry Osipenko 41528615e37SDmitry Osipenko dev_freq = actmon_device_target_freq(tegra, actmon_dev); 41628615e37SDmitry Osipenko 41711eb6ec5SDmitry Osipenko /* check whether CPU's freq is taken into account at all */ 41828615e37SDmitry Osipenko if (dev_freq < actmon_dev->config->avg_dependency_threshold) 41911eb6ec5SDmitry Osipenko return 0; 42011eb6ec5SDmitry Osipenko 42111eb6ec5SDmitry Osipenko static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq); 42211eb6ec5SDmitry Osipenko 42311eb6ec5SDmitry Osipenko if (dev_freq >= static_cpu_emc_freq) 42411eb6ec5SDmitry Osipenko return 0; 42511eb6ec5SDmitry Osipenko 42611eb6ec5SDmitry Osipenko return static_cpu_emc_freq; 42711eb6ec5SDmitry Osipenko } 42811eb6ec5SDmitry Osipenko 42911eb6ec5SDmitry Osipenko static int tegra_actmon_cpu_notify_cb(struct notifier_block *nb, 43011eb6ec5SDmitry Osipenko unsigned long action, void *ptr) 43111eb6ec5SDmitry Osipenko { 43211eb6ec5SDmitry Osipenko struct cpufreq_freqs *freqs = ptr; 43311eb6ec5SDmitry Osipenko struct tegra_devfreq *tegra; 43411eb6ec5SDmitry Osipenko unsigned long old, new, delay; 43511eb6ec5SDmitry Osipenko 43611eb6ec5SDmitry Osipenko if (action != CPUFREQ_POSTCHANGE) 43711eb6ec5SDmitry Osipenko return NOTIFY_OK; 43811eb6ec5SDmitry Osipenko 43911eb6ec5SDmitry Osipenko tegra = container_of(nb, struct tegra_devfreq, cpu_rate_change_nb); 44011eb6ec5SDmitry Osipenko 44111eb6ec5SDmitry Osipenko /* 44211eb6ec5SDmitry Osipenko * Quickly check whether CPU frequency should be taken into account 44311eb6ec5SDmitry Osipenko * at all, without blocking CPUFreq's core. 44411eb6ec5SDmitry Osipenko */ 44511eb6ec5SDmitry Osipenko if (mutex_trylock(&tegra->devfreq->lock)) { 44611eb6ec5SDmitry Osipenko old = tegra_actmon_cpufreq_contribution(tegra, freqs->old); 44711eb6ec5SDmitry Osipenko new = tegra_actmon_cpufreq_contribution(tegra, freqs->new); 44811eb6ec5SDmitry Osipenko mutex_unlock(&tegra->devfreq->lock); 44911eb6ec5SDmitry Osipenko 45011eb6ec5SDmitry Osipenko /* 45111eb6ec5SDmitry Osipenko * If CPU's frequency shouldn't be taken into account at 45211eb6ec5SDmitry Osipenko * the moment, then there is no need to update the devfreq's 45311eb6ec5SDmitry Osipenko * state because ISR will re-check CPU's frequency on the 45411eb6ec5SDmitry Osipenko * next interrupt. 45511eb6ec5SDmitry Osipenko */ 45611eb6ec5SDmitry Osipenko if (old == new) 45711eb6ec5SDmitry Osipenko return NOTIFY_OK; 45811eb6ec5SDmitry Osipenko } 45911eb6ec5SDmitry Osipenko 46011eb6ec5SDmitry Osipenko /* 46111eb6ec5SDmitry Osipenko * CPUFreq driver should support CPUFREQ_ASYNC_NOTIFICATION in order 46211eb6ec5SDmitry Osipenko * to allow asynchronous notifications. This means we can't block 46311eb6ec5SDmitry Osipenko * here for too long, otherwise CPUFreq's core will complain with a 46411eb6ec5SDmitry Osipenko * warning splat. 46511eb6ec5SDmitry Osipenko */ 46611eb6ec5SDmitry Osipenko delay = msecs_to_jiffies(ACTMON_SAMPLING_PERIOD); 46711eb6ec5SDmitry Osipenko schedule_delayed_work(&tegra->cpufreq_update_work, delay); 46811eb6ec5SDmitry Osipenko 46911eb6ec5SDmitry Osipenko return NOTIFY_OK; 47011eb6ec5SDmitry Osipenko } 47111eb6ec5SDmitry Osipenko 47223601752SDmitry Osipenko static void tegra_actmon_configure_device(struct tegra_devfreq *tegra, 47323601752SDmitry Osipenko struct tegra_devfreq_device *dev) 47423601752SDmitry Osipenko { 47523601752SDmitry Osipenko u32 val = 0; 47623601752SDmitry Osipenko 47714266558SDmitry Osipenko /* reset boosting on governor's restart */ 47814266558SDmitry Osipenko dev->boost_freq = 0; 47914266558SDmitry Osipenko 48023601752SDmitry Osipenko dev->target_freq = tegra->cur_freq; 48123601752SDmitry Osipenko 482f61ee201SDmitry Osipenko dev->avg_count = tegra->cur_freq * tegra->devfreq->profile->polling_ms; 48323601752SDmitry Osipenko device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG); 48423601752SDmitry Osipenko 48523601752SDmitry Osipenko tegra_devfreq_update_avg_wmark(tegra, dev); 48623601752SDmitry Osipenko tegra_devfreq_update_wmark(tegra, dev); 48723601752SDmitry Osipenko 48823601752SDmitry Osipenko device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT); 48923601752SDmitry Osipenko device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); 49023601752SDmitry Osipenko 49123601752SDmitry Osipenko val |= ACTMON_DEV_CTRL_ENB_PERIODIC; 49223601752SDmitry Osipenko val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1) 49323601752SDmitry Osipenko << ACTMON_DEV_CTRL_K_VAL_SHIFT; 49423601752SDmitry Osipenko val |= (ACTMON_BELOW_WMARK_WINDOW - 1) 49523601752SDmitry Osipenko << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT; 49623601752SDmitry Osipenko val |= (ACTMON_ABOVE_WMARK_WINDOW - 1) 49723601752SDmitry Osipenko << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT; 49823601752SDmitry Osipenko val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN; 49923601752SDmitry Osipenko val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN; 50023601752SDmitry Osipenko val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; 50123601752SDmitry Osipenko val |= ACTMON_DEV_CTRL_ENB; 50223601752SDmitry Osipenko 50323601752SDmitry Osipenko device_writel(dev, val, ACTMON_DEV_CTRL); 50423601752SDmitry Osipenko } 50523601752SDmitry Osipenko 50611eb6ec5SDmitry Osipenko static void tegra_actmon_stop_devices(struct tegra_devfreq *tegra) 50711eb6ec5SDmitry Osipenko { 50811eb6ec5SDmitry Osipenko struct tegra_devfreq_device *dev = tegra->devices; 50911eb6ec5SDmitry Osipenko unsigned int i; 51011eb6ec5SDmitry Osipenko 51111eb6ec5SDmitry Osipenko for (i = 0; i < ARRAY_SIZE(tegra->devices); i++, dev++) { 51211eb6ec5SDmitry Osipenko device_writel(dev, ACTMON_DEV_CTRL_STOP, ACTMON_DEV_CTRL); 51311eb6ec5SDmitry Osipenko device_writel(dev, ACTMON_INTR_STATUS_CLEAR, 51411eb6ec5SDmitry Osipenko ACTMON_DEV_INTR_STATUS); 51511eb6ec5SDmitry Osipenko } 51611eb6ec5SDmitry Osipenko } 51711eb6ec5SDmitry Osipenko 518f61ee201SDmitry Osipenko static int tegra_actmon_resume(struct tegra_devfreq *tegra) 51923601752SDmitry Osipenko { 52023601752SDmitry Osipenko unsigned int i; 52111eb6ec5SDmitry Osipenko int err; 52223601752SDmitry Osipenko 523f61ee201SDmitry Osipenko if (!tegra->devfreq->profile->polling_ms || !tegra->started) 524f61ee201SDmitry Osipenko return 0; 525f61ee201SDmitry Osipenko 526f61ee201SDmitry Osipenko actmon_writel(tegra, tegra->devfreq->profile->polling_ms - 1, 52723601752SDmitry Osipenko ACTMON_GLB_PERIOD_CTRL); 52823601752SDmitry Osipenko 5296f2a35d6SDmitry Osipenko /* 5306f2a35d6SDmitry Osipenko * CLK notifications are needed in order to reconfigure the upper 5316f2a35d6SDmitry Osipenko * consecutive watermark in accordance to the actual clock rate 5326f2a35d6SDmitry Osipenko * to avoid unnecessary upper interrupts. 5336f2a35d6SDmitry Osipenko */ 5346f2a35d6SDmitry Osipenko err = clk_notifier_register(tegra->emc_clock, 5356f2a35d6SDmitry Osipenko &tegra->clk_rate_change_nb); 5366f2a35d6SDmitry Osipenko if (err) { 5376f2a35d6SDmitry Osipenko dev_err(tegra->devfreq->dev.parent, 5386f2a35d6SDmitry Osipenko "Failed to register rate change notifier\n"); 5396f2a35d6SDmitry Osipenko return err; 5406f2a35d6SDmitry Osipenko } 5416f2a35d6SDmitry Osipenko 5426f2a35d6SDmitry Osipenko tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ; 5436f2a35d6SDmitry Osipenko 54423601752SDmitry Osipenko for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) 54523601752SDmitry Osipenko tegra_actmon_configure_device(tegra, &tegra->devices[i]); 54623601752SDmitry Osipenko 54711eb6ec5SDmitry Osipenko /* 54811eb6ec5SDmitry Osipenko * We are estimating CPU's memory bandwidth requirement based on 54911eb6ec5SDmitry Osipenko * amount of memory accesses and system's load, judging by CPU's 55011eb6ec5SDmitry Osipenko * frequency. We also don't want to receive events about CPU's 55111eb6ec5SDmitry Osipenko * frequency transaction when governor is stopped, hence notifier 55211eb6ec5SDmitry Osipenko * is registered dynamically. 55311eb6ec5SDmitry Osipenko */ 55411eb6ec5SDmitry Osipenko err = cpufreq_register_notifier(&tegra->cpu_rate_change_nb, 55511eb6ec5SDmitry Osipenko CPUFREQ_TRANSITION_NOTIFIER); 55611eb6ec5SDmitry Osipenko if (err) { 55711eb6ec5SDmitry Osipenko dev_err(tegra->devfreq->dev.parent, 55811eb6ec5SDmitry Osipenko "Failed to register rate change notifier: %d\n", err); 55911eb6ec5SDmitry Osipenko goto err_stop; 56011eb6ec5SDmitry Osipenko } 56111eb6ec5SDmitry Osipenko 56223601752SDmitry Osipenko enable_irq(tegra->irq); 56311eb6ec5SDmitry Osipenko 56411eb6ec5SDmitry Osipenko return 0; 56511eb6ec5SDmitry Osipenko 56611eb6ec5SDmitry Osipenko err_stop: 56711eb6ec5SDmitry Osipenko tegra_actmon_stop_devices(tegra); 56811eb6ec5SDmitry Osipenko 5696f2a35d6SDmitry Osipenko clk_notifier_unregister(tegra->emc_clock, &tegra->clk_rate_change_nb); 5706f2a35d6SDmitry Osipenko 57111eb6ec5SDmitry Osipenko return err; 57223601752SDmitry Osipenko } 57323601752SDmitry Osipenko 574f61ee201SDmitry Osipenko static int tegra_actmon_start(struct tegra_devfreq *tegra) 57523601752SDmitry Osipenko { 576f61ee201SDmitry Osipenko int ret = 0; 577f61ee201SDmitry Osipenko 578f61ee201SDmitry Osipenko if (!tegra->started) { 579f61ee201SDmitry Osipenko tegra->started = true; 580f61ee201SDmitry Osipenko 581f61ee201SDmitry Osipenko ret = tegra_actmon_resume(tegra); 582f61ee201SDmitry Osipenko if (ret) 583f61ee201SDmitry Osipenko tegra->started = false; 584f61ee201SDmitry Osipenko } 585f61ee201SDmitry Osipenko 586f61ee201SDmitry Osipenko return ret; 587f61ee201SDmitry Osipenko } 588f61ee201SDmitry Osipenko 589f61ee201SDmitry Osipenko static void tegra_actmon_pause(struct tegra_devfreq *tegra) 590f61ee201SDmitry Osipenko { 591f61ee201SDmitry Osipenko if (!tegra->devfreq->profile->polling_ms || !tegra->started) 592f61ee201SDmitry Osipenko return; 593f61ee201SDmitry Osipenko 59423601752SDmitry Osipenko disable_irq(tegra->irq); 59523601752SDmitry Osipenko 59611eb6ec5SDmitry Osipenko cpufreq_unregister_notifier(&tegra->cpu_rate_change_nb, 59711eb6ec5SDmitry Osipenko CPUFREQ_TRANSITION_NOTIFIER); 59811eb6ec5SDmitry Osipenko 59911eb6ec5SDmitry Osipenko cancel_delayed_work_sync(&tegra->cpufreq_update_work); 60011eb6ec5SDmitry Osipenko 60111eb6ec5SDmitry Osipenko tegra_actmon_stop_devices(tegra); 6026f2a35d6SDmitry Osipenko 6036f2a35d6SDmitry Osipenko clk_notifier_unregister(tegra->emc_clock, &tegra->clk_rate_change_nb); 60423601752SDmitry Osipenko } 60523601752SDmitry Osipenko 606f61ee201SDmitry Osipenko static void tegra_actmon_stop(struct tegra_devfreq *tegra) 607f61ee201SDmitry Osipenko { 608f61ee201SDmitry Osipenko tegra_actmon_pause(tegra); 609f61ee201SDmitry Osipenko tegra->started = false; 610f61ee201SDmitry Osipenko } 611f61ee201SDmitry Osipenko 61223601752SDmitry Osipenko static int tegra_devfreq_target(struct device *dev, unsigned long *freq, 61323601752SDmitry Osipenko u32 flags) 61423601752SDmitry Osipenko { 61523601752SDmitry Osipenko struct tegra_devfreq *tegra = dev_get_drvdata(dev); 61623601752SDmitry Osipenko struct devfreq *devfreq = tegra->devfreq; 61723601752SDmitry Osipenko struct dev_pm_opp *opp; 61823601752SDmitry Osipenko unsigned long rate; 61923601752SDmitry Osipenko int err; 62023601752SDmitry Osipenko 62123601752SDmitry Osipenko opp = devfreq_recommended_opp(dev, freq, flags); 62223601752SDmitry Osipenko if (IS_ERR(opp)) { 62323601752SDmitry Osipenko dev_err(dev, "Failed to find opp for %lu Hz\n", *freq); 62423601752SDmitry Osipenko return PTR_ERR(opp); 62523601752SDmitry Osipenko } 62623601752SDmitry Osipenko rate = dev_pm_opp_get_freq(opp); 62723601752SDmitry Osipenko dev_pm_opp_put(opp); 62823601752SDmitry Osipenko 6290ce38846SDmitry Osipenko err = clk_set_min_rate(tegra->emc_clock, rate * KHZ); 63023601752SDmitry Osipenko if (err) 63123601752SDmitry Osipenko return err; 63223601752SDmitry Osipenko 63323601752SDmitry Osipenko err = clk_set_rate(tegra->emc_clock, 0); 63423601752SDmitry Osipenko if (err) 63523601752SDmitry Osipenko goto restore_min_rate; 63623601752SDmitry Osipenko 63723601752SDmitry Osipenko return 0; 63823601752SDmitry Osipenko 63923601752SDmitry Osipenko restore_min_rate: 64023601752SDmitry Osipenko clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq); 64123601752SDmitry Osipenko 64223601752SDmitry Osipenko return err; 64323601752SDmitry Osipenko } 64423601752SDmitry Osipenko 64523601752SDmitry Osipenko static int tegra_devfreq_get_dev_status(struct device *dev, 64623601752SDmitry Osipenko struct devfreq_dev_status *stat) 64723601752SDmitry Osipenko { 64823601752SDmitry Osipenko struct tegra_devfreq *tegra = dev_get_drvdata(dev); 64923601752SDmitry Osipenko struct tegra_devfreq_device *actmon_dev; 65023601752SDmitry Osipenko unsigned long cur_freq; 65123601752SDmitry Osipenko 65223601752SDmitry Osipenko cur_freq = READ_ONCE(tegra->cur_freq); 65323601752SDmitry Osipenko 65423601752SDmitry Osipenko /* To be used by the tegra governor */ 65523601752SDmitry Osipenko stat->private_data = tegra; 65623601752SDmitry Osipenko 65723601752SDmitry Osipenko /* The below are to be used by the other governors */ 6580ce38846SDmitry Osipenko stat->current_frequency = cur_freq; 65923601752SDmitry Osipenko 66023601752SDmitry Osipenko actmon_dev = &tegra->devices[MCALL]; 66123601752SDmitry Osipenko 66223601752SDmitry Osipenko /* Number of cycles spent on memory access */ 66323601752SDmitry Osipenko stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT); 66423601752SDmitry Osipenko 66523601752SDmitry Osipenko /* The bus can be considered to be saturated way before 100% */ 66623601752SDmitry Osipenko stat->busy_time *= 100 / BUS_SATURATION_RATIO; 66723601752SDmitry Osipenko 66823601752SDmitry Osipenko /* Number of cycles in a sampling period */ 669f61ee201SDmitry Osipenko stat->total_time = tegra->devfreq->profile->polling_ms * cur_freq; 67023601752SDmitry Osipenko 67123601752SDmitry Osipenko stat->busy_time = min(stat->busy_time, stat->total_time); 67223601752SDmitry Osipenko 67323601752SDmitry Osipenko return 0; 67423601752SDmitry Osipenko } 67523601752SDmitry Osipenko 67623601752SDmitry Osipenko static struct devfreq_dev_profile tegra_devfreq_profile = { 677f61ee201SDmitry Osipenko .polling_ms = ACTMON_SAMPLING_PERIOD, 67823601752SDmitry Osipenko .target = tegra_devfreq_target, 67923601752SDmitry Osipenko .get_dev_status = tegra_devfreq_get_dev_status, 68023601752SDmitry Osipenko }; 68123601752SDmitry Osipenko 68223601752SDmitry Osipenko static int tegra_governor_get_target(struct devfreq *devfreq, 68323601752SDmitry Osipenko unsigned long *freq) 68423601752SDmitry Osipenko { 68523601752SDmitry Osipenko struct devfreq_dev_status *stat; 68623601752SDmitry Osipenko struct tegra_devfreq *tegra; 68723601752SDmitry Osipenko struct tegra_devfreq_device *dev; 68823601752SDmitry Osipenko unsigned long target_freq = 0; 68923601752SDmitry Osipenko unsigned int i; 69023601752SDmitry Osipenko int err; 69123601752SDmitry Osipenko 69223601752SDmitry Osipenko err = devfreq_update_stats(devfreq); 69323601752SDmitry Osipenko if (err) 69423601752SDmitry Osipenko return err; 69523601752SDmitry Osipenko 69623601752SDmitry Osipenko stat = &devfreq->last_status; 69723601752SDmitry Osipenko 69823601752SDmitry Osipenko tegra = stat->private_data; 69923601752SDmitry Osipenko 70023601752SDmitry Osipenko for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { 70123601752SDmitry Osipenko dev = &tegra->devices[i]; 70223601752SDmitry Osipenko 70323601752SDmitry Osipenko actmon_update_target(tegra, dev); 70423601752SDmitry Osipenko 70523601752SDmitry Osipenko target_freq = max(target_freq, dev->target_freq); 70623601752SDmitry Osipenko } 70723601752SDmitry Osipenko 7080ce38846SDmitry Osipenko *freq = target_freq; 70923601752SDmitry Osipenko 71023601752SDmitry Osipenko return 0; 71123601752SDmitry Osipenko } 71223601752SDmitry Osipenko 71323601752SDmitry Osipenko static int tegra_governor_event_handler(struct devfreq *devfreq, 71423601752SDmitry Osipenko unsigned int event, void *data) 71523601752SDmitry Osipenko { 71623601752SDmitry Osipenko struct tegra_devfreq *tegra = dev_get_drvdata(devfreq->dev.parent); 717f61ee201SDmitry Osipenko unsigned int *new_delay = data; 71811eb6ec5SDmitry Osipenko int ret = 0; 71923601752SDmitry Osipenko 720d49eeb1eSDmitry Osipenko /* 721d49eeb1eSDmitry Osipenko * Couple devfreq-device with the governor early because it is 722d49eeb1eSDmitry Osipenko * needed at the moment of governor's start (used by ISR). 723d49eeb1eSDmitry Osipenko */ 724d49eeb1eSDmitry Osipenko tegra->devfreq = devfreq; 725d49eeb1eSDmitry Osipenko 72623601752SDmitry Osipenko switch (event) { 72723601752SDmitry Osipenko case DEVFREQ_GOV_START: 72823601752SDmitry Osipenko devfreq_monitor_start(devfreq); 72911eb6ec5SDmitry Osipenko ret = tegra_actmon_start(tegra); 73023601752SDmitry Osipenko break; 73123601752SDmitry Osipenko 73223601752SDmitry Osipenko case DEVFREQ_GOV_STOP: 73323601752SDmitry Osipenko tegra_actmon_stop(tegra); 73423601752SDmitry Osipenko devfreq_monitor_stop(devfreq); 73523601752SDmitry Osipenko break; 73623601752SDmitry Osipenko 737f61ee201SDmitry Osipenko case DEVFREQ_GOV_INTERVAL: 738f61ee201SDmitry Osipenko /* 739f61ee201SDmitry Osipenko * ACTMON hardware supports up to 256 milliseconds for the 740f61ee201SDmitry Osipenko * sampling period. 741f61ee201SDmitry Osipenko */ 742f61ee201SDmitry Osipenko if (*new_delay > 256) { 743f61ee201SDmitry Osipenko ret = -EINVAL; 744f61ee201SDmitry Osipenko break; 745f61ee201SDmitry Osipenko } 746f61ee201SDmitry Osipenko 747f61ee201SDmitry Osipenko tegra_actmon_pause(tegra); 748f61ee201SDmitry Osipenko devfreq_interval_update(devfreq, new_delay); 749f61ee201SDmitry Osipenko ret = tegra_actmon_resume(tegra); 750f61ee201SDmitry Osipenko break; 751f61ee201SDmitry Osipenko 75223601752SDmitry Osipenko case DEVFREQ_GOV_SUSPEND: 75323601752SDmitry Osipenko tegra_actmon_stop(tegra); 75423601752SDmitry Osipenko devfreq_monitor_suspend(devfreq); 75523601752SDmitry Osipenko break; 75623601752SDmitry Osipenko 75723601752SDmitry Osipenko case DEVFREQ_GOV_RESUME: 75823601752SDmitry Osipenko devfreq_monitor_resume(devfreq); 75911eb6ec5SDmitry Osipenko ret = tegra_actmon_start(tegra); 76023601752SDmitry Osipenko break; 76123601752SDmitry Osipenko } 76223601752SDmitry Osipenko 76311eb6ec5SDmitry Osipenko return ret; 76423601752SDmitry Osipenko } 76523601752SDmitry Osipenko 76623601752SDmitry Osipenko static struct devfreq_governor tegra_devfreq_governor = { 76723601752SDmitry Osipenko .name = "tegra_actmon", 76823601752SDmitry Osipenko .get_target_freq = tegra_governor_get_target, 76923601752SDmitry Osipenko .event_handler = tegra_governor_event_handler, 77023601752SDmitry Osipenko .immutable = true, 771f61ee201SDmitry Osipenko .interrupt_driven = true, 77223601752SDmitry Osipenko }; 77323601752SDmitry Osipenko 77423601752SDmitry Osipenko static int tegra_devfreq_probe(struct platform_device *pdev) 77523601752SDmitry Osipenko { 77623601752SDmitry Osipenko struct tegra_devfreq_device *dev; 777d49eeb1eSDmitry Osipenko struct tegra_devfreq *tegra; 778d49eeb1eSDmitry Osipenko struct devfreq *devfreq; 779d49eeb1eSDmitry Osipenko unsigned int i; 7807296443bSDmitry Osipenko long rate; 78123601752SDmitry Osipenko int err; 78223601752SDmitry Osipenko 78323601752SDmitry Osipenko tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 78423601752SDmitry Osipenko if (!tegra) 78523601752SDmitry Osipenko return -ENOMEM; 78623601752SDmitry Osipenko 78723601752SDmitry Osipenko tegra->regs = devm_platform_ioremap_resource(pdev, 0); 78823601752SDmitry Osipenko if (IS_ERR(tegra->regs)) 78923601752SDmitry Osipenko return PTR_ERR(tegra->regs); 79023601752SDmitry Osipenko 79123601752SDmitry Osipenko tegra->reset = devm_reset_control_get(&pdev->dev, "actmon"); 79223601752SDmitry Osipenko if (IS_ERR(tegra->reset)) { 79323601752SDmitry Osipenko dev_err(&pdev->dev, "Failed to get reset\n"); 79423601752SDmitry Osipenko return PTR_ERR(tegra->reset); 79523601752SDmitry Osipenko } 79623601752SDmitry Osipenko 79723601752SDmitry Osipenko tegra->clock = devm_clk_get(&pdev->dev, "actmon"); 79823601752SDmitry Osipenko if (IS_ERR(tegra->clock)) { 79923601752SDmitry Osipenko dev_err(&pdev->dev, "Failed to get actmon clock\n"); 80023601752SDmitry Osipenko return PTR_ERR(tegra->clock); 80123601752SDmitry Osipenko } 80223601752SDmitry Osipenko 80323601752SDmitry Osipenko tegra->emc_clock = devm_clk_get(&pdev->dev, "emc"); 80423601752SDmitry Osipenko if (IS_ERR(tegra->emc_clock)) { 80523601752SDmitry Osipenko dev_err(&pdev->dev, "Failed to get emc clock\n"); 80623601752SDmitry Osipenko return PTR_ERR(tegra->emc_clock); 80723601752SDmitry Osipenko } 80823601752SDmitry Osipenko 809dccdea01SDmitry Osipenko err = platform_get_irq(pdev, 0); 810dccdea01SDmitry Osipenko if (err < 0) { 81123601752SDmitry Osipenko dev_err(&pdev->dev, "Failed to get IRQ: %d\n", err); 81223601752SDmitry Osipenko return err; 81323601752SDmitry Osipenko } 814dccdea01SDmitry Osipenko tegra->irq = err; 81523601752SDmitry Osipenko 816d49eeb1eSDmitry Osipenko irq_set_status_flags(tegra->irq, IRQ_NOAUTOEN); 817d49eeb1eSDmitry Osipenko 818d49eeb1eSDmitry Osipenko err = devm_request_threaded_irq(&pdev->dev, tegra->irq, NULL, 819d49eeb1eSDmitry Osipenko actmon_thread_isr, IRQF_ONESHOT, 820d49eeb1eSDmitry Osipenko "tegra-devfreq", tegra); 821d49eeb1eSDmitry Osipenko if (err) { 822d49eeb1eSDmitry Osipenko dev_err(&pdev->dev, "Interrupt request failed: %d\n", err); 823d49eeb1eSDmitry Osipenko return err; 824d49eeb1eSDmitry Osipenko } 825d49eeb1eSDmitry Osipenko 82623601752SDmitry Osipenko reset_control_assert(tegra->reset); 82723601752SDmitry Osipenko 82823601752SDmitry Osipenko err = clk_prepare_enable(tegra->clock); 82923601752SDmitry Osipenko if (err) { 83023601752SDmitry Osipenko dev_err(&pdev->dev, 83123601752SDmitry Osipenko "Failed to prepare and enable ACTMON clock\n"); 83223601752SDmitry Osipenko return err; 83323601752SDmitry Osipenko } 83423601752SDmitry Osipenko 83523601752SDmitry Osipenko reset_control_deassert(tegra->reset); 83623601752SDmitry Osipenko 8377296443bSDmitry Osipenko rate = clk_round_rate(tegra->emc_clock, ULONG_MAX); 8387296443bSDmitry Osipenko if (rate < 0) { 8397296443bSDmitry Osipenko dev_err(&pdev->dev, "Failed to round clock rate: %ld\n", rate); 8407296443bSDmitry Osipenko return rate; 8417296443bSDmitry Osipenko } 8427296443bSDmitry Osipenko 8437296443bSDmitry Osipenko tegra->max_freq = rate / KHZ; 84423601752SDmitry Osipenko 84523601752SDmitry Osipenko for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) { 84623601752SDmitry Osipenko dev = tegra->devices + i; 84723601752SDmitry Osipenko dev->config = actmon_device_configs + i; 84823601752SDmitry Osipenko dev->regs = tegra->regs + dev->config->offset; 84923601752SDmitry Osipenko } 85023601752SDmitry Osipenko 85123601752SDmitry Osipenko for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) { 85223601752SDmitry Osipenko rate = clk_round_rate(tegra->emc_clock, rate); 85323601752SDmitry Osipenko 8547296443bSDmitry Osipenko if (rate < 0) { 8557296443bSDmitry Osipenko dev_err(&pdev->dev, 8567296443bSDmitry Osipenko "Failed to round clock rate: %ld\n", rate); 8577296443bSDmitry Osipenko err = rate; 8587296443bSDmitry Osipenko goto remove_opps; 8597296443bSDmitry Osipenko } 8607296443bSDmitry Osipenko 8610ce38846SDmitry Osipenko err = dev_pm_opp_add(&pdev->dev, rate / KHZ, 0); 86223601752SDmitry Osipenko if (err) { 86323601752SDmitry Osipenko dev_err(&pdev->dev, "Failed to add OPP: %d\n", err); 86423601752SDmitry Osipenko goto remove_opps; 86523601752SDmitry Osipenko } 86623601752SDmitry Osipenko } 86723601752SDmitry Osipenko 86823601752SDmitry Osipenko platform_set_drvdata(pdev, tegra); 86923601752SDmitry Osipenko 8706f2a35d6SDmitry Osipenko tegra->clk_rate_change_nb.notifier_call = tegra_actmon_clk_notify_cb; 87111eb6ec5SDmitry Osipenko tegra->cpu_rate_change_nb.notifier_call = tegra_actmon_cpu_notify_cb; 87211eb6ec5SDmitry Osipenko 87311eb6ec5SDmitry Osipenko INIT_DELAYED_WORK(&tegra->cpufreq_update_work, 87411eb6ec5SDmitry Osipenko tegra_actmon_delayed_update); 87511eb6ec5SDmitry Osipenko 87623601752SDmitry Osipenko err = devfreq_add_governor(&tegra_devfreq_governor); 87723601752SDmitry Osipenko if (err) { 87823601752SDmitry Osipenko dev_err(&pdev->dev, "Failed to add governor: %d\n", err); 8796f2a35d6SDmitry Osipenko goto remove_opps; 88023601752SDmitry Osipenko } 88123601752SDmitry Osipenko 8826f2a35d6SDmitry Osipenko tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock); 8836f2a35d6SDmitry Osipenko tegra_devfreq_profile.initial_freq /= KHZ; 8840ce38846SDmitry Osipenko 885d49eeb1eSDmitry Osipenko devfreq = devfreq_add_device(&pdev->dev, &tegra_devfreq_profile, 886d49eeb1eSDmitry Osipenko "tegra_actmon", NULL); 887d49eeb1eSDmitry Osipenko if (IS_ERR(devfreq)) { 888d49eeb1eSDmitry Osipenko err = PTR_ERR(devfreq); 88923601752SDmitry Osipenko goto remove_governor; 89023601752SDmitry Osipenko } 89123601752SDmitry Osipenko 89223601752SDmitry Osipenko return 0; 89323601752SDmitry Osipenko 89423601752SDmitry Osipenko remove_governor: 89523601752SDmitry Osipenko devfreq_remove_governor(&tegra_devfreq_governor); 89623601752SDmitry Osipenko 89723601752SDmitry Osipenko remove_opps: 89823601752SDmitry Osipenko dev_pm_opp_remove_all_dynamic(&pdev->dev); 89923601752SDmitry Osipenko 90023601752SDmitry Osipenko reset_control_reset(tegra->reset); 90123601752SDmitry Osipenko clk_disable_unprepare(tegra->clock); 90223601752SDmitry Osipenko 90323601752SDmitry Osipenko return err; 90423601752SDmitry Osipenko } 90523601752SDmitry Osipenko 90623601752SDmitry Osipenko static int tegra_devfreq_remove(struct platform_device *pdev) 90723601752SDmitry Osipenko { 90823601752SDmitry Osipenko struct tegra_devfreq *tegra = platform_get_drvdata(pdev); 90923601752SDmitry Osipenko 91023601752SDmitry Osipenko devfreq_remove_device(tegra->devfreq); 91123601752SDmitry Osipenko devfreq_remove_governor(&tegra_devfreq_governor); 91223601752SDmitry Osipenko 91323601752SDmitry Osipenko dev_pm_opp_remove_all_dynamic(&pdev->dev); 91423601752SDmitry Osipenko 91523601752SDmitry Osipenko reset_control_reset(tegra->reset); 91623601752SDmitry Osipenko clk_disable_unprepare(tegra->clock); 91723601752SDmitry Osipenko 91823601752SDmitry Osipenko return 0; 91923601752SDmitry Osipenko } 92023601752SDmitry Osipenko 92123601752SDmitry Osipenko static const struct of_device_id tegra_devfreq_of_match[] = { 92223601752SDmitry Osipenko { .compatible = "nvidia,tegra30-actmon" }, 92323601752SDmitry Osipenko { .compatible = "nvidia,tegra124-actmon" }, 92423601752SDmitry Osipenko { }, 92523601752SDmitry Osipenko }; 92623601752SDmitry Osipenko 92723601752SDmitry Osipenko MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match); 92823601752SDmitry Osipenko 92923601752SDmitry Osipenko static struct platform_driver tegra_devfreq_driver = { 93023601752SDmitry Osipenko .probe = tegra_devfreq_probe, 93123601752SDmitry Osipenko .remove = tegra_devfreq_remove, 93223601752SDmitry Osipenko .driver = { 93323601752SDmitry Osipenko .name = "tegra-devfreq", 93423601752SDmitry Osipenko .of_match_table = tegra_devfreq_of_match, 93523601752SDmitry Osipenko }, 93623601752SDmitry Osipenko }; 93723601752SDmitry Osipenko module_platform_driver(tegra_devfreq_driver); 93823601752SDmitry Osipenko 93923601752SDmitry Osipenko MODULE_LICENSE("GPL v2"); 94023601752SDmitry Osipenko MODULE_DESCRIPTION("Tegra devfreq driver"); 94123601752SDmitry Osipenko MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>"); 942