xref: /linux/drivers/devfreq/Kconfig (revision 7da2fdaaa1e6062686ac96a9f096c2d7847533e4)
1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
2a3c98b8bSMyungJoo Hammenuconfig PM_DEVFREQ
3a3c98b8bSMyungJoo Ham	bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
4b9c69e04SChanwoo Choi	select PM_OPP
5a3c98b8bSMyungJoo Ham	help
66c81f905SMyungJoo Ham	  A device may have a list of frequencies and voltages available.
76c81f905SMyungJoo Ham	  devfreq, a generic DVFS framework can be registered for a device
86c81f905SMyungJoo Ham	  in order to let the governor provided to devfreq choose an
96c81f905SMyungJoo Ham	  operating frequency based on the device driver's policy.
10a3c98b8bSMyungJoo Ham
116c81f905SMyungJoo Ham	  Each device may have its own governor and policy. Devfreq can
12a3c98b8bSMyungJoo Ham	  reevaluate the device state periodically and/or based on the
136c81f905SMyungJoo Ham	  notification to "nb", a notifier block, of devfreq.
14a3c98b8bSMyungJoo Ham
156c81f905SMyungJoo Ham	  Like some CPUs with CPUfreq, a device may have multiple clocks.
16a3c98b8bSMyungJoo Ham	  However, because the clock frequencies of a single device are
176c81f905SMyungJoo Ham	  determined by the single device's state, an instance of devfreq
18a3c98b8bSMyungJoo Ham	  is attached to a single device and returns a "representative"
196c81f905SMyungJoo Ham	  clock frequency of the device, which is also attached
206c81f905SMyungJoo Ham	  to a device by 1-to-1. The device registering devfreq takes the
216b2aac42SMasanari Iida	  responsibility to "interpret" the representative frequency and
22a3c98b8bSMyungJoo Ham	  to set its every clock accordingly with the "target" callback
236c81f905SMyungJoo Ham	  given to devfreq.
246c81f905SMyungJoo Ham
256c81f905SMyungJoo Ham	  When OPP is used with the devfreq device, it is recommended to
266c81f905SMyungJoo Ham	  register devfreq's nb to the OPP's notifier head.  If OPP is
276c81f905SMyungJoo Ham	  used with the devfreq device, you may use OPP helper
286c81f905SMyungJoo Ham	  functions defined in devfreq.h.
29a3c98b8bSMyungJoo Ham
30a3c98b8bSMyungJoo Hamif PM_DEVFREQ
31a3c98b8bSMyungJoo Ham
32ce26c5bbSMyungJoo Hamcomment "DEVFREQ Governors"
33ce26c5bbSMyungJoo Ham
34ce26c5bbSMyungJoo Hamconfig DEVFREQ_GOV_SIMPLE_ONDEMAND
35eff607fdSNishanth Menon	tristate "Simple Ondemand"
36ce26c5bbSMyungJoo Ham	help
37ce26c5bbSMyungJoo Ham	  Chooses frequency based on the recent load on the device. Works
38ce26c5bbSMyungJoo Ham	  similar as ONDEMAND governor of CPUFREQ does. A device with
39ce26c5bbSMyungJoo Ham	  Simple-Ondemand should be able to provide busy/total counter
40ce26c5bbSMyungJoo Ham	  values that imply the usage rate. A device may provide tuned
41ce26c5bbSMyungJoo Ham	  values to the governor with data field at devfreq_add_device().
42ce26c5bbSMyungJoo Ham
43ce26c5bbSMyungJoo Hamconfig DEVFREQ_GOV_PERFORMANCE
44eff607fdSNishanth Menon	tristate "Performance"
45ce26c5bbSMyungJoo Ham	help
46ce26c5bbSMyungJoo Ham	  Sets the frequency at the maximum available frequency.
47ce26c5bbSMyungJoo Ham	  This governor always returns UINT_MAX as frequency so that
48ce26c5bbSMyungJoo Ham	  the DEVFREQ framework returns the highest frequency available
49ce26c5bbSMyungJoo Ham	  at any time.
50ce26c5bbSMyungJoo Ham
51ce26c5bbSMyungJoo Hamconfig DEVFREQ_GOV_POWERSAVE
52eff607fdSNishanth Menon	tristate "Powersave"
53ce26c5bbSMyungJoo Ham	help
54ce26c5bbSMyungJoo Ham	  Sets the frequency at the minimum available frequency.
55ce26c5bbSMyungJoo Ham	  This governor always returns 0 as frequency so that
56ce26c5bbSMyungJoo Ham	  the DEVFREQ framework returns the lowest frequency available
57ce26c5bbSMyungJoo Ham	  at any time.
58ce26c5bbSMyungJoo Ham
59ce26c5bbSMyungJoo Hamconfig DEVFREQ_GOV_USERSPACE
60eff607fdSNishanth Menon	tristate "Userspace"
61ce26c5bbSMyungJoo Ham	help
62ce26c5bbSMyungJoo Ham	  Sets the frequency at the user specified one.
63ce26c5bbSMyungJoo Ham	  This governor returns the user configured frequency if there
645f104f9fSDong Aisheng	  has been an input to /sys/devices/.../userspace/set_freq.
65027b6934SGeert Uytterhoeven	  Otherwise, the governor does not change the frequency
66ce26c5bbSMyungJoo Ham	  given at the initialization.
67ce26c5bbSMyungJoo Ham
6899613311SChanwoo Choiconfig DEVFREQ_GOV_PASSIVE
6999613311SChanwoo Choi	tristate "Passive"
7099613311SChanwoo Choi	help
7199613311SChanwoo Choi	  Sets the frequency based on the frequency of its parent devfreq
7299613311SChanwoo Choi	  device. This governor does not change the frequency by itself
7399613311SChanwoo Choi	  through sysfs entries. The passive governor recommends that
7499613311SChanwoo Choi	  devfreq device uses the OPP table to get the frequency/voltage.
7599613311SChanwoo Choi
76a3c98b8bSMyungJoo Hamcomment "DEVFREQ Drivers"
77a3c98b8bSMyungJoo Ham
780722249aSChanwoo Choiconfig ARM_EXYNOS_BUS_DEVFREQ
7991d7f3f8SKrzysztof Kozlowski	tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
80797da559SKrzysztof Kozlowski	depends on ARCH_EXYNOS || COMPILE_TEST
810722249aSChanwoo Choi	select DEVFREQ_GOV_SIMPLE_ONDEMAND
82403e0689SChanwoo Choi	select DEVFREQ_GOV_PASSIVE
830722249aSChanwoo Choi	select DEVFREQ_EVENT_EXYNOS_PPMU
840722249aSChanwoo Choi	select PM_DEVFREQ_EVENT
850722249aSChanwoo Choi	help
860722249aSChanwoo Choi	  This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
870722249aSChanwoo Choi	  Memory bus has one more group of memory bus (e.g, MIF and INT block).
880722249aSChanwoo Choi	  Each memory bus group could contain many memoby bus block. It reads
890722249aSChanwoo Choi	  PPMU counters of memory controllers by using DEVFREQ-event device
900722249aSChanwoo Choi	  and adjusts the operating frequencies and voltages with OPP support.
910722249aSChanwoo Choi	  This does not yet operate with optimal voltages.
920722249aSChanwoo Choi
93*7da2fdaaSJie Zhanconfig ARM_HISI_UNCORE_DEVFREQ
94*7da2fdaaSJie Zhan	tristate "HiSilicon uncore DEVFREQ Driver"
95*7da2fdaaSJie Zhan	depends on ACPI && ACPI_PPTT && PCC
96*7da2fdaaSJie Zhan	select DEVFREQ_GOV_PERFORMANCE
97*7da2fdaaSJie Zhan	select DEVFREQ_GOV_USERSPACE
98*7da2fdaaSJie Zhan	help
99*7da2fdaaSJie Zhan	  This adds a DEVFREQ driver that manages uncore frequency scaling for
100*7da2fdaaSJie Zhan	  HiSilicon Kunpeng SoCs. This enables runtime management of uncore
101*7da2fdaaSJie Zhan	  frequency scaling from kernel and userspace. The uncore domain
102*7da2fdaaSJie Zhan	  contains system interconnects and L3 cache.
103*7da2fdaaSJie Zhan
1045173a975SLeonard Crestezconfig ARM_IMX_BUS_DEVFREQ
1055173a975SLeonard Crestez	tristate "i.MX Generic Bus DEVFREQ Driver"
1065173a975SLeonard Crestez	depends on ARCH_MXC || COMPILE_TEST
1075173a975SLeonard Crestez	select DEVFREQ_GOV_USERSPACE
1085173a975SLeonard Crestez	help
1095173a975SLeonard Crestez	  This adds the generic DEVFREQ driver for i.MX interconnects. It
1105173a975SLeonard Crestez	  allows adjusting NIC/NOC frequency.
1115173a975SLeonard Crestez
1125af744ebSLeonard Crestezconfig ARM_IMX8M_DDRC_DEVFREQ
1135af744ebSLeonard Crestez	tristate "i.MX8M DDRC DEVFREQ Driver"
1145af744ebSLeonard Crestez	depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \
1155af744ebSLeonard Crestez		(COMPILE_TEST && HAVE_ARM_SMCCC)
1165af744ebSLeonard Crestez	select DEVFREQ_GOV_USERSPACE
1175af744ebSLeonard Crestez	help
1185af744ebSLeonard Crestez	  This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
1195af744ebSLeonard Crestez	  adjusting DRAM frequency.
1205af744ebSLeonard Crestez
1216234f380STomeu Vizosoconfig ARM_TEGRA_DEVFREQ
1221ac34748SDmitry Osipenko	tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
1231ac34748SDmitry Osipenko	depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
1241ac34748SDmitry Osipenko		ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
12535f8dbc7SDmitry Osipenko		ARCH_TEGRA_210_SOC || \
12635f8dbc7SDmitry Osipenko		COMPILE_TEST
1275fdb0684SArnd Bergmann	depends on COMMON_CLK
1286234f380STomeu Vizoso	help
1296234f380STomeu Vizoso	  This adds the DEVFREQ driver for the Tegra family of SoCs.
1306234f380STomeu Vizoso	  It reads ACTMON counters of memory controllers and adjusts the
1316234f380STomeu Vizoso	  operating frequencies and voltages with OPP support.
1326234f380STomeu Vizoso
13386d231b1SJohnson Wangconfig ARM_MEDIATEK_CCI_DEVFREQ
13486d231b1SJohnson Wang	tristate "MEDIATEK CCI DEVFREQ Driver"
13586d231b1SJohnson Wang	depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
13686d231b1SJohnson Wang	select DEVFREQ_GOV_PASSIVE
13786d231b1SJohnson Wang	help
13886d231b1SJohnson Wang	  This adds a devfreq driver for MediaTek Cache Coherent Interconnect
13986d231b1SJohnson Wang	  which is shared the same regulators with the cpu cluster. It can track
14086d231b1SJohnson Wang	  buck voltages and update a proper CCI frequency. Use the notification
14186d231b1SJohnson Wang	  to get the regulator status.
14286d231b1SJohnson Wang
1435a893e31SLin Huangconfig ARM_RK3399_DMC_DEVFREQ
1445a893e31SLin Huang	tristate "ARM RK3399 DMC DEVFREQ Driver"
145eff5d31fSChanwoo Choi	depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
146eff5d31fSChanwoo Choi		(COMPILE_TEST && HAVE_ARM_SMCCC)
1475a893e31SLin Huang	select DEVFREQ_EVENT_ROCKCHIP_DFI
1485a893e31SLin Huang	select DEVFREQ_GOV_SIMPLE_ONDEMAND
14954dec69bSArnd Bergmann	select PM_DEVFREQ_EVENT
1505a893e31SLin Huang	help
1515a893e31SLin Huang	  This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
1525a893e31SLin Huang	  It sets the frequency for the memory controller and reads the usage counts
1535a893e31SLin Huang	  from hardware.
1545a893e31SLin Huang
1558bfd4858SSamuel Hollandconfig ARM_SUN8I_A33_MBUS_DEVFREQ
1568bfd4858SSamuel Holland	tristate "sun8i/sun50i MBUS DEVFREQ Driver"
1578bfd4858SSamuel Holland	depends on ARCH_SUNXI || COMPILE_TEST
158a4b3c62fSArnd Bergmann	depends on COMMON_CLK
1598bfd4858SSamuel Holland	select DEVFREQ_GOV_SIMPLE_ONDEMAND
1608bfd4858SSamuel Holland	help
1618bfd4858SSamuel Holland	  This adds the DEVFREQ driver for the MBUS controller in some
1628bfd4858SSamuel Holland	  Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
1638bfd4858SSamuel Holland
164f262f28cSChanwoo Choisource "drivers/devfreq/event/Kconfig"
165f262f28cSChanwoo Choi
166a3c98b8bSMyungJoo Hamendif # PM_DEVFREQ
167