1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3 #include <linux/device.h> 4 #include <linux/module.h> 5 #include <linux/slab.h> 6 7 #include "cxlmem.h" 8 #include "cxlpci.h" 9 10 /** 11 * DOC: cxl port 12 * 13 * The port driver enumerates dport via PCI and scans for HDM 14 * (Host-managed-Device-Memory) decoder resources via the 15 * @component_reg_phys value passed in by the agent that registered the 16 * port. All descendant ports of a CXL root port (described by platform 17 * firmware) are managed in this drivers context. Each driver instance 18 * is responsible for tearing down the driver context of immediate 19 * descendant ports. The locking for this is validated by 20 * CONFIG_PROVE_CXL_LOCKING. 21 * 22 * The primary service this driver provides is presenting APIs to other 23 * drivers to utilize the decoders, and indicating to userspace (via bind 24 * status) the connectivity of the CXL.mem protocol throughout the 25 * PCIe topology. 26 */ 27 28 static void schedule_detach(void *cxlmd) 29 { 30 schedule_cxl_memdev_detach(cxlmd); 31 } 32 33 static int discover_region(struct device *dev, void *root) 34 { 35 struct cxl_endpoint_decoder *cxled; 36 int rc; 37 38 if (!is_endpoint_decoder(dev)) 39 return 0; 40 41 cxled = to_cxl_endpoint_decoder(dev); 42 if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0) 43 return 0; 44 45 if (cxled->state != CXL_DECODER_STATE_AUTO) 46 return 0; 47 48 /* 49 * Region enumeration is opportunistic, if this add-event fails, 50 * continue to the next endpoint decoder. 51 */ 52 rc = cxl_add_to_region(root, cxled); 53 if (rc) 54 dev_dbg(dev, "failed to add to region: %#llx-%#llx\n", 55 cxled->cxld.hpa_range.start, cxled->cxld.hpa_range.end); 56 57 return 0; 58 } 59 60 static int cxl_switch_port_probe(struct cxl_port *port) 61 { 62 struct cxl_hdm *cxlhdm; 63 int rc; 64 65 rc = devm_cxl_port_enumerate_dports(port); 66 if (rc < 0) 67 return rc; 68 69 if (rc == 1) 70 return devm_cxl_add_passthrough_decoder(port); 71 72 cxlhdm = devm_cxl_setup_hdm(port); 73 if (IS_ERR(cxlhdm)) 74 return PTR_ERR(cxlhdm); 75 76 return devm_cxl_enumerate_decoders(cxlhdm); 77 } 78 79 static int cxl_endpoint_port_probe(struct cxl_port *port) 80 { 81 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport); 82 struct cxl_dev_state *cxlds = cxlmd->cxlds; 83 struct cxl_hdm *cxlhdm; 84 struct cxl_port *root; 85 int rc; 86 87 cxlhdm = devm_cxl_setup_hdm(port); 88 if (IS_ERR(cxlhdm)) 89 return PTR_ERR(cxlhdm); 90 91 /* Cache the data early to ensure is_visible() works */ 92 read_cdat_data(port); 93 94 get_device(&cxlmd->dev); 95 rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd); 96 if (rc) 97 return rc; 98 99 rc = cxl_hdm_decode_init(cxlds, cxlhdm); 100 if (rc) 101 return rc; 102 103 rc = cxl_await_media_ready(cxlds); 104 if (rc) { 105 dev_err(&port->dev, "Media not active (%d)\n", rc); 106 return rc; 107 } 108 109 rc = devm_cxl_enumerate_decoders(cxlhdm); 110 if (rc) 111 return rc; 112 113 /* 114 * This can't fail in practice as CXL root exit unregisters all 115 * descendant ports and that in turn synchronizes with cxl_port_probe() 116 */ 117 root = find_cxl_root(&cxlmd->dev); 118 119 /* 120 * Now that all endpoint decoders are successfully enumerated, try to 121 * assemble regions from committed decoders 122 */ 123 device_for_each_child(&port->dev, root, discover_region); 124 put_device(&root->dev); 125 126 return 0; 127 } 128 129 static int cxl_port_probe(struct device *dev) 130 { 131 struct cxl_port *port = to_cxl_port(dev); 132 133 if (is_cxl_endpoint(port)) 134 return cxl_endpoint_port_probe(port); 135 return cxl_switch_port_probe(port); 136 } 137 138 static ssize_t CDAT_read(struct file *filp, struct kobject *kobj, 139 struct bin_attribute *bin_attr, char *buf, 140 loff_t offset, size_t count) 141 { 142 struct device *dev = kobj_to_dev(kobj); 143 struct cxl_port *port = to_cxl_port(dev); 144 145 if (!port->cdat_available) 146 return -ENXIO; 147 148 if (!port->cdat.table) 149 return 0; 150 151 return memory_read_from_buffer(buf, count, &offset, 152 port->cdat.table, 153 port->cdat.length); 154 } 155 156 static BIN_ATTR_ADMIN_RO(CDAT, 0); 157 158 static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj, 159 struct bin_attribute *attr, int i) 160 { 161 struct device *dev = kobj_to_dev(kobj); 162 struct cxl_port *port = to_cxl_port(dev); 163 164 if ((attr == &bin_attr_CDAT) && port->cdat_available) 165 return attr->attr.mode; 166 167 return 0; 168 } 169 170 static struct bin_attribute *cxl_cdat_bin_attributes[] = { 171 &bin_attr_CDAT, 172 NULL, 173 }; 174 175 static struct attribute_group cxl_cdat_attribute_group = { 176 .bin_attrs = cxl_cdat_bin_attributes, 177 .is_bin_visible = cxl_port_bin_attr_is_visible, 178 }; 179 180 static const struct attribute_group *cxl_port_attribute_groups[] = { 181 &cxl_cdat_attribute_group, 182 NULL, 183 }; 184 185 static struct cxl_driver cxl_port_driver = { 186 .name = "cxl_port", 187 .probe = cxl_port_probe, 188 .id = CXL_DEVICE_PORT, 189 .drv = { 190 .dev_groups = cxl_port_attribute_groups, 191 }, 192 }; 193 194 module_cxl_driver(cxl_port_driver); 195 MODULE_LICENSE("GPL v2"); 196 MODULE_IMPORT_NS(CXL); 197 MODULE_ALIAS_CXL(CXL_DEVICE_PORT); 198