1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 3 #include <linux/io-64-nonatomic-lo-hi.h> 4 #include <linux/moduleparam.h> 5 #include <linux/module.h> 6 #include <linux/delay.h> 7 #include <linux/sizes.h> 8 #include <linux/mutex.h> 9 #include <linux/list.h> 10 #include <linux/pci.h> 11 #include <linux/aer.h> 12 #include <linux/io.h> 13 #include "cxlmem.h" 14 #include "cxlpci.h" 15 #include "cxl.h" 16 #include "pmu.h" 17 18 /** 19 * DOC: cxl pci 20 * 21 * This implements the PCI exclusive functionality for a CXL device as it is 22 * defined by the Compute Express Link specification. CXL devices may surface 23 * certain functionality even if it isn't CXL enabled. While this driver is 24 * focused around the PCI specific aspects of a CXL device, it binds to the 25 * specific CXL memory device class code, and therefore the implementation of 26 * cxl_pci is focused around CXL memory devices. 27 * 28 * The driver has several responsibilities, mainly: 29 * - Create the memX device and register on the CXL bus. 30 * - Enumerate device's register interface and map them. 31 * - Registers nvdimm bridge device with cxl_core. 32 * - Registers a CXL mailbox with cxl_core. 33 */ 34 35 #define cxl_doorbell_busy(cxlds) \ 36 (readl((cxlds)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ 37 CXLDEV_MBOX_CTRL_DOORBELL) 38 39 /* CXL 2.0 - 8.2.8.4 */ 40 #define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) 41 42 /* 43 * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to 44 * dictate how long to wait for the mailbox to become ready. The new 45 * field allows the device to tell software the amount of time to wait 46 * before mailbox ready. This field per the spec theoretically allows 47 * for up to 255 seconds. 255 seconds is unreasonably long, its longer 48 * than the maximum SATA port link recovery wait. Default to 60 seconds 49 * until someone builds a CXL device that needs more time in practice. 50 */ 51 static unsigned short mbox_ready_timeout = 60; 52 module_param(mbox_ready_timeout, ushort, 0644); 53 MODULE_PARM_DESC(mbox_ready_timeout, "seconds to wait for mailbox ready"); 54 55 static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) 56 { 57 const unsigned long start = jiffies; 58 unsigned long end = start; 59 60 while (cxl_doorbell_busy(cxlds)) { 61 end = jiffies; 62 63 if (time_after(end, start + CXL_MAILBOX_TIMEOUT_MS)) { 64 /* Check again in case preempted before timeout test */ 65 if (!cxl_doorbell_busy(cxlds)) 66 break; 67 return -ETIMEDOUT; 68 } 69 cpu_relax(); 70 } 71 72 dev_dbg(cxlds->dev, "Doorbell wait took %dms", 73 jiffies_to_msecs(end) - jiffies_to_msecs(start)); 74 return 0; 75 } 76 77 #define cxl_err(dev, status, msg) \ 78 dev_err_ratelimited(dev, msg ", device state %s%s\n", \ 79 status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 80 status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 81 82 #define cxl_cmd_err(dev, cmd, status, msg) \ 83 dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \ 84 (cmd)->opcode, \ 85 status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 86 status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 87 88 struct cxl_dev_id { 89 struct cxl_dev_state *cxlds; 90 }; 91 92 static int cxl_request_irq(struct cxl_dev_state *cxlds, int irq, 93 irq_handler_t handler, irq_handler_t thread_fn) 94 { 95 struct device *dev = cxlds->dev; 96 struct cxl_dev_id *dev_id; 97 98 /* dev_id must be globally unique and must contain the cxlds */ 99 dev_id = devm_kzalloc(dev, sizeof(*dev_id), GFP_KERNEL); 100 if (!dev_id) 101 return -ENOMEM; 102 dev_id->cxlds = cxlds; 103 104 return devm_request_threaded_irq(dev, irq, handler, thread_fn, 105 IRQF_SHARED | IRQF_ONESHOT, 106 NULL, dev_id); 107 } 108 109 static bool cxl_mbox_background_complete(struct cxl_dev_state *cxlds) 110 { 111 u64 reg; 112 113 reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 114 return FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK, reg) == 100; 115 } 116 117 static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) 118 { 119 u64 reg; 120 u16 opcode; 121 struct cxl_dev_id *dev_id = id; 122 struct cxl_dev_state *cxlds = dev_id->cxlds; 123 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 124 125 if (!cxl_mbox_background_complete(cxlds)) 126 return IRQ_NONE; 127 128 reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 129 opcode = FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK, reg); 130 if (opcode == CXL_MBOX_OP_SANITIZE) { 131 if (mds->security.sanitize_node) 132 sysfs_notify_dirent(mds->security.sanitize_node); 133 134 dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 135 } else { 136 /* short-circuit the wait in __cxl_pci_mbox_send_cmd() */ 137 rcuwait_wake_up(&mds->mbox_wait); 138 } 139 140 return IRQ_HANDLED; 141 } 142 143 /* 144 * Sanitization operation polling mode. 145 */ 146 static void cxl_mbox_sanitize_work(struct work_struct *work) 147 { 148 struct cxl_memdev_state *mds = 149 container_of(work, typeof(*mds), security.poll_dwork.work); 150 struct cxl_dev_state *cxlds = &mds->cxlds; 151 152 mutex_lock(&mds->mbox_mutex); 153 if (cxl_mbox_background_complete(cxlds)) { 154 mds->security.poll_tmo_secs = 0; 155 put_device(cxlds->dev); 156 157 if (mds->security.sanitize_node) 158 sysfs_notify_dirent(mds->security.sanitize_node); 159 160 dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 161 } else { 162 int timeout = mds->security.poll_tmo_secs + 10; 163 164 mds->security.poll_tmo_secs = min(15 * 60, timeout); 165 queue_delayed_work(system_wq, &mds->security.poll_dwork, 166 timeout * HZ); 167 } 168 mutex_unlock(&mds->mbox_mutex); 169 } 170 171 /** 172 * __cxl_pci_mbox_send_cmd() - Execute a mailbox command 173 * @mds: The memory device driver data 174 * @mbox_cmd: Command to send to the memory device. 175 * 176 * Context: Any context. Expects mbox_mutex to be held. 177 * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. 178 * Caller should check the return code in @mbox_cmd to make sure it 179 * succeeded. 180 * 181 * This is a generic form of the CXL mailbox send command thus only using the 182 * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory 183 * devices, and perhaps other types of CXL devices may have further information 184 * available upon error conditions. Driver facilities wishing to send mailbox 185 * commands should use the wrapper command. 186 * 187 * The CXL spec allows for up to two mailboxes. The intention is for the primary 188 * mailbox to be OS controlled and the secondary mailbox to be used by system 189 * firmware. This allows the OS and firmware to communicate with the device and 190 * not need to coordinate with each other. The driver only uses the primary 191 * mailbox. 192 */ 193 static int __cxl_pci_mbox_send_cmd(struct cxl_memdev_state *mds, 194 struct cxl_mbox_cmd *mbox_cmd) 195 { 196 struct cxl_dev_state *cxlds = &mds->cxlds; 197 void __iomem *payload = cxlds->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; 198 struct device *dev = cxlds->dev; 199 u64 cmd_reg, status_reg; 200 size_t out_len; 201 int rc; 202 203 lockdep_assert_held(&mds->mbox_mutex); 204 205 /* 206 * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. 207 * 1. Caller reads MB Control Register to verify doorbell is clear 208 * 2. Caller writes Command Register 209 * 3. Caller writes Command Payload Registers if input payload is non-empty 210 * 4. Caller writes MB Control Register to set doorbell 211 * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured 212 * 6. Caller reads MB Status Register to fetch Return code 213 * 7. If command successful, Caller reads Command Register to get Payload Length 214 * 8. If output payload is non-empty, host reads Command Payload Registers 215 * 216 * Hardware is free to do whatever it wants before the doorbell is rung, 217 * and isn't allowed to change anything after it clears the doorbell. As 218 * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can 219 * also happen in any order (though some orders might not make sense). 220 */ 221 222 /* #1 */ 223 if (cxl_doorbell_busy(cxlds)) { 224 u64 md_status = 225 readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 226 227 cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, 228 "mailbox queue busy"); 229 return -EBUSY; 230 } 231 232 /* 233 * With sanitize polling, hardware might be done and the poller still 234 * not be in sync. Ensure no new command comes in until so. Keep the 235 * hardware semantics and only allow device health status. 236 */ 237 if (mds->security.poll_tmo_secs > 0) { 238 if (mbox_cmd->opcode != CXL_MBOX_OP_GET_HEALTH_INFO) 239 return -EBUSY; 240 } 241 242 cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, 243 mbox_cmd->opcode); 244 if (mbox_cmd->size_in) { 245 if (WARN_ON(!mbox_cmd->payload_in)) 246 return -EINVAL; 247 248 cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, 249 mbox_cmd->size_in); 250 memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); 251 } 252 253 /* #2, #3 */ 254 writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 255 256 /* #4 */ 257 dev_dbg(dev, "Sending command: 0x%04x\n", mbox_cmd->opcode); 258 writel(CXLDEV_MBOX_CTRL_DOORBELL, 259 cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 260 261 /* #5 */ 262 rc = cxl_pci_mbox_wait_for_doorbell(cxlds); 263 if (rc == -ETIMEDOUT) { 264 u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 265 266 cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout"); 267 return rc; 268 } 269 270 /* #6 */ 271 status_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); 272 mbox_cmd->return_code = 273 FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); 274 275 /* 276 * Handle the background command in a synchronous manner. 277 * 278 * All other mailbox commands will serialize/queue on the mbox_mutex, 279 * which we currently hold. Furthermore this also guarantees that 280 * cxl_mbox_background_complete() checks are safe amongst each other, 281 * in that no new bg operation can occur in between. 282 * 283 * Background operations are timesliced in accordance with the nature 284 * of the command. In the event of timeout, the mailbox state is 285 * indeterminate until the next successful command submission and the 286 * driver can get back in sync with the hardware state. 287 */ 288 if (mbox_cmd->return_code == CXL_MBOX_CMD_RC_BACKGROUND) { 289 u64 bg_status_reg; 290 int i, timeout; 291 292 /* 293 * Sanitization is a special case which monopolizes the device 294 * and cannot be timesliced. Handle asynchronously instead, 295 * and allow userspace to poll(2) for completion. 296 */ 297 if (mbox_cmd->opcode == CXL_MBOX_OP_SANITIZE) { 298 if (mds->security.poll) { 299 /* hold the device throughout */ 300 get_device(cxlds->dev); 301 302 /* give first timeout a second */ 303 timeout = 1; 304 mds->security.poll_tmo_secs = timeout; 305 queue_delayed_work(system_wq, 306 &mds->security.poll_dwork, 307 timeout * HZ); 308 } 309 310 dev_dbg(dev, "Sanitization operation started\n"); 311 goto success; 312 } 313 314 dev_dbg(dev, "Mailbox background operation (0x%04x) started\n", 315 mbox_cmd->opcode); 316 317 timeout = mbox_cmd->poll_interval_ms; 318 for (i = 0; i < mbox_cmd->poll_count; i++) { 319 if (rcuwait_wait_event_timeout(&mds->mbox_wait, 320 cxl_mbox_background_complete(cxlds), 321 TASK_UNINTERRUPTIBLE, 322 msecs_to_jiffies(timeout)) > 0) 323 break; 324 } 325 326 if (!cxl_mbox_background_complete(cxlds)) { 327 dev_err(dev, "timeout waiting for background (%d ms)\n", 328 timeout * mbox_cmd->poll_count); 329 return -ETIMEDOUT; 330 } 331 332 bg_status_reg = readq(cxlds->regs.mbox + 333 CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 334 mbox_cmd->return_code = 335 FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK, 336 bg_status_reg); 337 dev_dbg(dev, 338 "Mailbox background operation (0x%04x) completed\n", 339 mbox_cmd->opcode); 340 } 341 342 if (mbox_cmd->return_code != CXL_MBOX_CMD_RC_SUCCESS) { 343 dev_dbg(dev, "Mailbox operation had an error: %s\n", 344 cxl_mbox_cmd_rc2str(mbox_cmd)); 345 return 0; /* completed but caller must check return_code */ 346 } 347 348 success: 349 /* #7 */ 350 cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 351 out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); 352 353 /* #8 */ 354 if (out_len && mbox_cmd->payload_out) { 355 /* 356 * Sanitize the copy. If hardware misbehaves, out_len per the 357 * spec can actually be greater than the max allowed size (21 358 * bits available but spec defined 1M max). The caller also may 359 * have requested less data than the hardware supplied even 360 * within spec. 361 */ 362 size_t n; 363 364 n = min3(mbox_cmd->size_out, mds->payload_size, out_len); 365 memcpy_fromio(mbox_cmd->payload_out, payload, n); 366 mbox_cmd->size_out = n; 367 } else { 368 mbox_cmd->size_out = 0; 369 } 370 371 return 0; 372 } 373 374 static int cxl_pci_mbox_send(struct cxl_memdev_state *mds, 375 struct cxl_mbox_cmd *cmd) 376 { 377 int rc; 378 379 mutex_lock_io(&mds->mbox_mutex); 380 rc = __cxl_pci_mbox_send_cmd(mds, cmd); 381 mutex_unlock(&mds->mbox_mutex); 382 383 return rc; 384 } 385 386 static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds) 387 { 388 struct cxl_dev_state *cxlds = &mds->cxlds; 389 const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); 390 struct device *dev = cxlds->dev; 391 unsigned long timeout; 392 u64 md_status; 393 394 timeout = jiffies + mbox_ready_timeout * HZ; 395 do { 396 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 397 if (md_status & CXLMDEV_MBOX_IF_READY) 398 break; 399 if (msleep_interruptible(100)) 400 break; 401 } while (!time_after(jiffies, timeout)); 402 403 if (!(md_status & CXLMDEV_MBOX_IF_READY)) { 404 cxl_err(dev, md_status, "timeout awaiting mailbox ready"); 405 return -ETIMEDOUT; 406 } 407 408 /* 409 * A command may be in flight from a previous driver instance, 410 * think kexec, do one doorbell wait so that 411 * __cxl_pci_mbox_send_cmd() can assume that it is the only 412 * source for future doorbell busy events. 413 */ 414 if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) { 415 cxl_err(dev, md_status, "timeout awaiting mailbox idle"); 416 return -ETIMEDOUT; 417 } 418 419 mds->mbox_send = cxl_pci_mbox_send; 420 mds->payload_size = 421 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); 422 423 /* 424 * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register 425 * 426 * If the size is too small, mandatory commands will not work and so 427 * there's no point in going forward. If the size is too large, there's 428 * no harm is soft limiting it. 429 */ 430 mds->payload_size = min_t(size_t, mds->payload_size, SZ_1M); 431 if (mds->payload_size < 256) { 432 dev_err(dev, "Mailbox is too small (%zub)", 433 mds->payload_size); 434 return -ENXIO; 435 } 436 437 dev_dbg(dev, "Mailbox payload sized %zu", mds->payload_size); 438 439 rcuwait_init(&mds->mbox_wait); 440 441 if (cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ) { 442 u32 ctrl; 443 int irq, msgnum; 444 struct pci_dev *pdev = to_pci_dev(cxlds->dev); 445 446 msgnum = FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); 447 irq = pci_irq_vector(pdev, msgnum); 448 if (irq < 0) 449 goto mbox_poll; 450 451 if (cxl_request_irq(cxlds, irq, cxl_pci_mbox_irq, NULL)) 452 goto mbox_poll; 453 454 /* enable background command mbox irq support */ 455 ctrl = readl(cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 456 ctrl |= CXLDEV_MBOX_CTRL_BG_CMD_IRQ; 457 writel(ctrl, cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 458 459 return 0; 460 } 461 462 mbox_poll: 463 mds->security.poll = true; 464 INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mbox_sanitize_work); 465 466 dev_dbg(cxlds->dev, "Mailbox interrupts are unsupported"); 467 return 0; 468 } 469 470 /* 471 * Assume that any RCIEP that emits the CXL memory expander class code 472 * is an RCD 473 */ 474 static bool is_cxl_restricted(struct pci_dev *pdev) 475 { 476 return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; 477 } 478 479 static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, 480 struct cxl_register_map *map) 481 { 482 struct cxl_port *port; 483 struct cxl_dport *dport; 484 resource_size_t component_reg_phys; 485 486 *map = (struct cxl_register_map) { 487 .dev = &pdev->dev, 488 .resource = CXL_RESOURCE_NONE, 489 }; 490 491 port = cxl_pci_find_port(pdev, &dport); 492 if (!port) 493 return -EPROBE_DEFER; 494 495 component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); 496 497 put_device(&port->dev); 498 499 if (component_reg_phys == CXL_RESOURCE_NONE) 500 return -ENXIO; 501 502 map->resource = component_reg_phys; 503 map->reg_type = CXL_REGLOC_RBI_COMPONENT; 504 map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; 505 506 return 0; 507 } 508 509 static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, 510 struct cxl_register_map *map) 511 { 512 int rc; 513 514 rc = cxl_find_regblock(pdev, type, map); 515 516 /* 517 * If the Register Locator DVSEC does not exist, check if it 518 * is an RCH and try to extract the Component Registers from 519 * an RCRB. 520 */ 521 if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) 522 rc = cxl_rcrb_get_comp_regs(pdev, map); 523 524 if (rc) 525 return rc; 526 527 return cxl_setup_regs(map); 528 } 529 530 static int cxl_pci_ras_unmask(struct pci_dev *pdev) 531 { 532 struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 533 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 534 void __iomem *addr; 535 u32 orig_val, val, mask; 536 u16 cap; 537 int rc; 538 539 if (!cxlds->regs.ras) { 540 dev_dbg(&pdev->dev, "No RAS registers.\n"); 541 return 0; 542 } 543 544 /* BIOS has CXL error control */ 545 if (!host_bridge->native_cxl_error) 546 return -ENXIO; 547 548 rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); 549 if (rc) 550 return rc; 551 552 if (cap & PCI_EXP_DEVCTL_URRE) { 553 addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; 554 orig_val = readl(addr); 555 556 mask = CXL_RAS_UNCORRECTABLE_MASK_MASK | 557 CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; 558 val = orig_val & ~mask; 559 writel(val, addr); 560 dev_dbg(&pdev->dev, 561 "Uncorrectable RAS Errors Mask: %#x -> %#x\n", 562 orig_val, val); 563 } 564 565 if (cap & PCI_EXP_DEVCTL_CERE) { 566 addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_MASK_OFFSET; 567 orig_val = readl(addr); 568 val = orig_val & ~CXL_RAS_CORRECTABLE_MASK_MASK; 569 writel(val, addr); 570 dev_dbg(&pdev->dev, "Correctable RAS Errors Mask: %#x -> %#x\n", 571 orig_val, val); 572 } 573 574 return 0; 575 } 576 577 static void free_event_buf(void *buf) 578 { 579 kvfree(buf); 580 } 581 582 /* 583 * There is a single buffer for reading event logs from the mailbox. All logs 584 * share this buffer protected by the mds->event_log_lock. 585 */ 586 static int cxl_mem_alloc_event_buf(struct cxl_memdev_state *mds) 587 { 588 struct cxl_get_event_payload *buf; 589 590 buf = kvmalloc(mds->payload_size, GFP_KERNEL); 591 if (!buf) 592 return -ENOMEM; 593 mds->event.buf = buf; 594 595 return devm_add_action_or_reset(mds->cxlds.dev, free_event_buf, buf); 596 } 597 598 static int cxl_alloc_irq_vectors(struct pci_dev *pdev) 599 { 600 int nvecs; 601 602 /* 603 * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must 604 * not generate INTx messages if that function participates in 605 * CXL.cache or CXL.mem. 606 * 607 * Additionally pci_alloc_irq_vectors() handles calling 608 * pci_free_irq_vectors() automatically despite not being called 609 * pcim_*. See pci_setup_msi_context(). 610 */ 611 nvecs = pci_alloc_irq_vectors(pdev, 1, CXL_PCI_DEFAULT_MAX_VECTORS, 612 PCI_IRQ_MSIX | PCI_IRQ_MSI); 613 if (nvecs < 1) { 614 dev_dbg(&pdev->dev, "Failed to alloc irq vectors: %d\n", nvecs); 615 return -ENXIO; 616 } 617 return 0; 618 } 619 620 static irqreturn_t cxl_event_thread(int irq, void *id) 621 { 622 struct cxl_dev_id *dev_id = id; 623 struct cxl_dev_state *cxlds = dev_id->cxlds; 624 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 625 u32 status; 626 627 do { 628 /* 629 * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status; 630 * ignore the reserved upper 32 bits 631 */ 632 status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET); 633 /* Ignore logs unknown to the driver */ 634 status &= CXLDEV_EVENT_STATUS_ALL; 635 if (!status) 636 break; 637 cxl_mem_get_event_records(mds, status); 638 cond_resched(); 639 } while (status); 640 641 return IRQ_HANDLED; 642 } 643 644 static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) 645 { 646 struct pci_dev *pdev = to_pci_dev(cxlds->dev); 647 int irq; 648 649 if (FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting) != CXL_INT_MSI_MSIX) 650 return -ENXIO; 651 652 irq = pci_irq_vector(pdev, 653 FIELD_GET(CXLDEV_EVENT_INT_MSGNUM_MASK, setting)); 654 if (irq < 0) 655 return irq; 656 657 return cxl_request_irq(cxlds, irq, NULL, cxl_event_thread); 658 } 659 660 static int cxl_event_get_int_policy(struct cxl_memdev_state *mds, 661 struct cxl_event_interrupt_policy *policy) 662 { 663 struct cxl_mbox_cmd mbox_cmd = { 664 .opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY, 665 .payload_out = policy, 666 .size_out = sizeof(*policy), 667 }; 668 int rc; 669 670 rc = cxl_internal_send_cmd(mds, &mbox_cmd); 671 if (rc < 0) 672 dev_err(mds->cxlds.dev, 673 "Failed to get event interrupt policy : %d", rc); 674 675 return rc; 676 } 677 678 static int cxl_event_config_msgnums(struct cxl_memdev_state *mds, 679 struct cxl_event_interrupt_policy *policy) 680 { 681 struct cxl_mbox_cmd mbox_cmd; 682 int rc; 683 684 *policy = (struct cxl_event_interrupt_policy) { 685 .info_settings = CXL_INT_MSI_MSIX, 686 .warn_settings = CXL_INT_MSI_MSIX, 687 .failure_settings = CXL_INT_MSI_MSIX, 688 .fatal_settings = CXL_INT_MSI_MSIX, 689 }; 690 691 mbox_cmd = (struct cxl_mbox_cmd) { 692 .opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY, 693 .payload_in = policy, 694 .size_in = sizeof(*policy), 695 }; 696 697 rc = cxl_internal_send_cmd(mds, &mbox_cmd); 698 if (rc < 0) { 699 dev_err(mds->cxlds.dev, "Failed to set event interrupt policy : %d", 700 rc); 701 return rc; 702 } 703 704 /* Retrieve final interrupt settings */ 705 return cxl_event_get_int_policy(mds, policy); 706 } 707 708 static int cxl_event_irqsetup(struct cxl_memdev_state *mds) 709 { 710 struct cxl_dev_state *cxlds = &mds->cxlds; 711 struct cxl_event_interrupt_policy policy; 712 int rc; 713 714 rc = cxl_event_config_msgnums(mds, &policy); 715 if (rc) 716 return rc; 717 718 rc = cxl_event_req_irq(cxlds, policy.info_settings); 719 if (rc) { 720 dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n"); 721 return rc; 722 } 723 724 rc = cxl_event_req_irq(cxlds, policy.warn_settings); 725 if (rc) { 726 dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n"); 727 return rc; 728 } 729 730 rc = cxl_event_req_irq(cxlds, policy.failure_settings); 731 if (rc) { 732 dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n"); 733 return rc; 734 } 735 736 rc = cxl_event_req_irq(cxlds, policy.fatal_settings); 737 if (rc) { 738 dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n"); 739 return rc; 740 } 741 742 return 0; 743 } 744 745 static bool cxl_event_int_is_fw(u8 setting) 746 { 747 u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting); 748 749 return mode == CXL_INT_FW; 750 } 751 752 static int cxl_event_config(struct pci_host_bridge *host_bridge, 753 struct cxl_memdev_state *mds) 754 { 755 struct cxl_event_interrupt_policy policy; 756 int rc; 757 758 /* 759 * When BIOS maintains CXL error reporting control, it will process 760 * event records. Only one agent can do so. 761 */ 762 if (!host_bridge->native_cxl_error) 763 return 0; 764 765 rc = cxl_mem_alloc_event_buf(mds); 766 if (rc) 767 return rc; 768 769 rc = cxl_event_get_int_policy(mds, &policy); 770 if (rc) 771 return rc; 772 773 if (cxl_event_int_is_fw(policy.info_settings) || 774 cxl_event_int_is_fw(policy.warn_settings) || 775 cxl_event_int_is_fw(policy.failure_settings) || 776 cxl_event_int_is_fw(policy.fatal_settings)) { 777 dev_err(mds->cxlds.dev, 778 "FW still in control of Event Logs despite _OSC settings\n"); 779 return -EBUSY; 780 } 781 782 rc = cxl_event_irqsetup(mds); 783 if (rc) 784 return rc; 785 786 cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL); 787 788 return 0; 789 } 790 791 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 792 { 793 struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 794 struct cxl_memdev_state *mds; 795 struct cxl_dev_state *cxlds; 796 struct cxl_register_map map; 797 struct cxl_memdev *cxlmd; 798 int i, rc, pmu_count; 799 800 /* 801 * Double check the anonymous union trickery in struct cxl_regs 802 * FIXME switch to struct_group() 803 */ 804 BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != 805 offsetof(struct cxl_regs, device_regs.memdev)); 806 807 rc = pcim_enable_device(pdev); 808 if (rc) 809 return rc; 810 pci_set_master(pdev); 811 812 mds = cxl_memdev_state_create(&pdev->dev); 813 if (IS_ERR(mds)) 814 return PTR_ERR(mds); 815 cxlds = &mds->cxlds; 816 pci_set_drvdata(pdev, cxlds); 817 818 cxlds->rcd = is_cxl_restricted(pdev); 819 cxlds->serial = pci_get_dsn(pdev); 820 cxlds->cxl_dvsec = pci_find_dvsec_capability( 821 pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); 822 if (!cxlds->cxl_dvsec) 823 dev_warn(&pdev->dev, 824 "Device DVSEC not present, skip CXL.mem init\n"); 825 826 rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); 827 if (rc) 828 return rc; 829 830 rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); 831 if (rc) 832 return rc; 833 834 /* 835 * If the component registers can't be found, the cxl_pci driver may 836 * still be useful for management functions so don't return an error. 837 */ 838 cxlds->component_reg_phys = CXL_RESOURCE_NONE; 839 rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); 840 if (rc) 841 dev_warn(&pdev->dev, "No component registers (%d)\n", rc); 842 else if (!map.component_map.ras.valid) 843 dev_dbg(&pdev->dev, "RAS registers not found\n"); 844 845 cxlds->component_reg_phys = map.resource; 846 847 rc = cxl_map_component_regs(&map, &cxlds->regs.component, 848 BIT(CXL_CM_CAP_CAP_ID_RAS)); 849 if (rc) 850 dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); 851 852 rc = cxl_await_media_ready(cxlds); 853 if (rc == 0) 854 cxlds->media_ready = true; 855 else 856 dev_warn(&pdev->dev, "Media not active (%d)\n", rc); 857 858 rc = cxl_alloc_irq_vectors(pdev); 859 if (rc) 860 return rc; 861 862 rc = cxl_pci_setup_mailbox(mds); 863 if (rc) 864 return rc; 865 866 rc = cxl_enumerate_cmds(mds); 867 if (rc) 868 return rc; 869 870 rc = cxl_set_timestamp(mds); 871 if (rc) 872 return rc; 873 874 rc = cxl_poison_state_init(mds); 875 if (rc) 876 return rc; 877 878 rc = cxl_dev_state_identify(mds); 879 if (rc) 880 return rc; 881 882 rc = cxl_mem_create_range_info(mds); 883 if (rc) 884 return rc; 885 886 cxlmd = devm_cxl_add_memdev(cxlds); 887 if (IS_ERR(cxlmd)) 888 return PTR_ERR(cxlmd); 889 890 rc = cxl_memdev_setup_fw_upload(mds); 891 if (rc) 892 return rc; 893 894 pmu_count = cxl_count_regblock(pdev, CXL_REGLOC_RBI_PMU); 895 for (i = 0; i < pmu_count; i++) { 896 struct cxl_pmu_regs pmu_regs; 897 898 rc = cxl_find_regblock_instance(pdev, CXL_REGLOC_RBI_PMU, &map, i); 899 if (rc) { 900 dev_dbg(&pdev->dev, "Could not find PMU regblock\n"); 901 break; 902 } 903 904 rc = cxl_map_pmu_regs(pdev, &pmu_regs, &map); 905 if (rc) { 906 dev_dbg(&pdev->dev, "Could not map PMU regs\n"); 907 break; 908 } 909 910 rc = devm_cxl_pmu_add(cxlds->dev, &pmu_regs, cxlmd->id, i, CXL_PMU_MEMDEV); 911 if (rc) { 912 dev_dbg(&pdev->dev, "Could not add PMU instance\n"); 913 break; 914 } 915 } 916 917 rc = cxl_event_config(host_bridge, mds); 918 if (rc) 919 return rc; 920 921 rc = cxl_pci_ras_unmask(pdev); 922 if (rc) 923 dev_dbg(&pdev->dev, "No RAS reporting unmasked\n"); 924 925 pci_save_state(pdev); 926 927 return rc; 928 } 929 930 static const struct pci_device_id cxl_mem_pci_tbl[] = { 931 /* PCI class code for CXL.mem Type-3 Devices */ 932 { PCI_DEVICE_CLASS((PCI_CLASS_MEMORY_CXL << 8 | CXL_MEMORY_PROGIF), ~0)}, 933 { /* terminate list */ }, 934 }; 935 MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl); 936 937 static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev) 938 { 939 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 940 struct cxl_memdev *cxlmd = cxlds->cxlmd; 941 struct device *dev = &cxlmd->dev; 942 943 dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n", 944 dev_name(dev)); 945 pci_restore_state(pdev); 946 if (device_attach(dev) <= 0) 947 return PCI_ERS_RESULT_DISCONNECT; 948 return PCI_ERS_RESULT_RECOVERED; 949 } 950 951 static void cxl_error_resume(struct pci_dev *pdev) 952 { 953 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 954 struct cxl_memdev *cxlmd = cxlds->cxlmd; 955 struct device *dev = &cxlmd->dev; 956 957 dev_info(&pdev->dev, "%s: error resume %s\n", dev_name(dev), 958 dev->driver ? "successful" : "failed"); 959 } 960 961 static const struct pci_error_handlers cxl_error_handlers = { 962 .error_detected = cxl_error_detected, 963 .slot_reset = cxl_slot_reset, 964 .resume = cxl_error_resume, 965 .cor_error_detected = cxl_cor_error_detected, 966 }; 967 968 static struct pci_driver cxl_pci_driver = { 969 .name = KBUILD_MODNAME, 970 .id_table = cxl_mem_pci_tbl, 971 .probe = cxl_pci_probe, 972 .err_handler = &cxl_error_handlers, 973 .driver = { 974 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 975 }, 976 }; 977 978 MODULE_LICENSE("GPL v2"); 979 module_pci_driver(cxl_pci_driver); 980 MODULE_IMPORT_NS(CXL); 981