1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 3 #ifndef __CXL_PCI_H__ 4 #define __CXL_PCI_H__ 5 #include <linux/pci.h> 6 #include "cxl.h" 7 8 #define CXL_MEMORY_PROGIF 0x10 9 10 /* 11 * NOTE: Currently all the functions which are enabled for CXL require their 12 * vectors to be in the first 16. Use this as the default max. 13 */ 14 #define CXL_PCI_DEFAULT_MAX_VECTORS 16 15 16 /* 17 * Table Access DOE, CDAT Read Entry Response 18 * 19 * Spec refs: 20 * 21 * CXL 3.1 8.1.11, Table 8-14: Read Entry Response 22 * CDAT Specification 1.03: 2 CDAT Data Structures 23 */ 24 25 struct cdat_header { 26 __le32 length; 27 u8 revision; 28 u8 checksum; 29 u8 reserved[6]; 30 __le32 sequence; 31 } __packed; 32 33 struct cdat_entry_header { 34 u8 type; 35 u8 reserved; 36 __le16 length; 37 } __packed; 38 39 /* 40 * The DOE CDAT read response contains a CDAT read entry (either the 41 * CDAT header or a structure). 42 */ 43 union cdat_data { 44 struct cdat_header header; 45 struct cdat_entry_header entry; 46 } __packed; 47 48 /* There is an additional CDAT response header of 4 bytes. */ 49 struct cdat_doe_rsp { 50 __le32 doe_header; 51 u8 data[]; 52 } __packed; 53 54 /* 55 * CXL v3.0 6.2.3 Table 6-4 56 * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits 57 * mode, otherwise it's 68B flits mode. 58 */ 59 static inline bool cxl_pci_flit_256(struct pci_dev *pdev) 60 { 61 u16 lnksta2; 62 63 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2); 64 return lnksta2 & PCI_EXP_LNKSTA2_FLIT; 65 } 66 67 /* 68 * Assume that the caller has already validated that @pdev has CXL 69 * capabilities, any RCiEP with CXL capabilities is treated as a 70 * Restricted CXL Device (RCD) and finds upstream port and endpoint 71 * registers in a Root Complex Register Block (RCRB). 72 */ 73 static inline bool is_cxl_restricted(struct pci_dev *pdev) 74 { 75 return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; 76 } 77 78 struct cxl_dev_state; 79 void read_cdat_data(struct cxl_port *port); 80 81 #ifdef CONFIG_CXL_RAS 82 void cxl_cor_error_detected(struct pci_dev *pdev); 83 pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, 84 pci_channel_state_t state); 85 void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport); 86 void devm_cxl_port_ras_setup(struct cxl_port *port); 87 #else 88 static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } 89 90 static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, 91 pci_channel_state_t state) 92 { 93 return PCI_ERS_RESULT_NONE; 94 } 95 96 static inline void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport) 97 { 98 } 99 100 static inline void devm_cxl_port_ras_setup(struct cxl_port *port) 101 { 102 } 103 #endif 104 105 #endif /* __CXL_PCI_H__ */ 106