1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include "cxl.h" 8 9 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 10 #define CXLMDEV_STATUS_OFFSET 0x0 11 #define CXLMDEV_DEV_FATAL BIT(0) 12 #define CXLMDEV_FW_HALT BIT(1) 13 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 14 #define CXLMDEV_MS_NOT_READY 0 15 #define CXLMDEV_MS_READY 1 16 #define CXLMDEV_MS_ERROR 2 17 #define CXLMDEV_MS_DISABLED 3 18 #define CXLMDEV_READY(status) \ 19 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 20 CXLMDEV_MS_READY) 21 #define CXLMDEV_MBOX_IF_READY BIT(4) 22 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 23 #define CXLMDEV_RESET_NEEDED_NOT 0 24 #define CXLMDEV_RESET_NEEDED_COLD 1 25 #define CXLMDEV_RESET_NEEDED_WARM 2 26 #define CXLMDEV_RESET_NEEDED_HOT 3 27 #define CXLMDEV_RESET_NEEDED_CXL 4 28 #define CXLMDEV_RESET_NEEDED(status) \ 29 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 30 CXLMDEV_RESET_NEEDED_NOT) 31 32 /** 33 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 34 * @dev: driver core device object 35 * @cdev: char dev core object for ioctl operations 36 * @cxlds: The device state backing this device 37 * @detach_work: active memdev lost a port in its ancestry 38 * @cxl_nvb: coordinate removal of @cxl_nvd if present 39 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 40 * @id: id number of this memdev instance. 41 * @depth: endpoint port depth 42 */ 43 struct cxl_memdev { 44 struct device dev; 45 struct cdev cdev; 46 struct cxl_dev_state *cxlds; 47 struct work_struct detach_work; 48 struct cxl_nvdimm_bridge *cxl_nvb; 49 struct cxl_nvdimm *cxl_nvd; 50 int id; 51 int depth; 52 }; 53 54 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 55 { 56 return container_of(dev, struct cxl_memdev, dev); 57 } 58 59 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 60 { 61 return to_cxl_port(cxled->cxld.dev.parent); 62 } 63 64 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 65 { 66 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 67 } 68 69 static inline struct cxl_memdev * 70 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 71 { 72 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 73 74 return to_cxl_memdev(port->uport); 75 } 76 77 bool is_cxl_memdev(struct device *dev); 78 static inline bool is_cxl_endpoint(struct cxl_port *port) 79 { 80 return is_cxl_memdev(port->uport); 81 } 82 83 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 84 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 85 resource_size_t base, resource_size_t len, 86 resource_size_t skipped); 87 88 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 89 struct cxl_memdev *cxlmd) 90 { 91 if (!port) 92 return NULL; 93 94 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 95 } 96 97 /** 98 * struct cxl_mbox_cmd - A command to be submitted to hardware. 99 * @opcode: (input) The command set and command submitted to hardware. 100 * @payload_in: (input) Pointer to the input payload. 101 * @payload_out: (output) Pointer to the output payload. Must be allocated by 102 * the caller. 103 * @size_in: (input) Number of bytes to load from @payload_in. 104 * @size_out: (input) Max number of bytes loaded into @payload_out. 105 * (output) Number of bytes generated by the device. For fixed size 106 * outputs commands this is always expected to be deterministic. For 107 * variable sized output commands, it tells the exact number of bytes 108 * written. 109 * @min_out: (input) internal command output payload size validation 110 * @return_code: (output) Error code returned from hardware. 111 * 112 * This is the primary mechanism used to send commands to the hardware. 113 * All the fields except @payload_* correspond exactly to the fields described in 114 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 115 * @payload_out are written to, and read from the Command Payload Registers 116 * defined in CXL 2.0 8.2.8.4.8. 117 */ 118 struct cxl_mbox_cmd { 119 u16 opcode; 120 void *payload_in; 121 void *payload_out; 122 size_t size_in; 123 size_t size_out; 124 size_t min_out; 125 u16 return_code; 126 }; 127 128 /* 129 * Per CXL 2.0 Section 8.2.8.4.5.1 130 */ 131 #define CMD_CMD_RC_TABLE \ 132 C(SUCCESS, 0, NULL), \ 133 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 134 C(INPUT, -ENXIO, "cmd input was invalid"), \ 135 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 136 C(INTERNAL, -ENXIO, "internal device error"), \ 137 C(RETRY, -ENXIO, "temporary error, retry once"), \ 138 C(BUSY, -ENXIO, "ongoing background operation"), \ 139 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 140 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 141 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 142 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 143 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 144 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 145 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 146 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 147 C(PADDR, -ENXIO, "physical address specified is invalid"), \ 148 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 149 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 150 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 151 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 152 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 153 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 154 C(PAYLOADLEN, -ENXIO, "invalid payload length") 155 156 #undef C 157 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 158 enum { CMD_CMD_RC_TABLE }; 159 #undef C 160 #define C(a, b, c) { b, c } 161 struct cxl_mbox_cmd_rc { 162 int err; 163 const char *desc; 164 }; 165 166 static const 167 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 168 #undef C 169 170 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 171 { 172 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 173 } 174 175 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 176 { 177 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 178 } 179 180 /* 181 * CXL 2.0 - Memory capacity multiplier 182 * See Section 8.2.9.5 183 * 184 * Volatile, Persistent, and Partition capacities are specified to be in 185 * multiples of 256MB - define a multiplier to convert to/from bytes. 186 */ 187 #define CXL_CAPACITY_MULTIPLIER SZ_256M 188 189 /** 190 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 191 * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE 192 * @ranges: Number of active HDM ranges this device uses. 193 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 194 */ 195 struct cxl_endpoint_dvsec_info { 196 bool mem_enabled; 197 int ranges; 198 struct range dvsec_range[2]; 199 }; 200 201 /** 202 * struct cxl_dev_state - The driver device state 203 * 204 * cxl_dev_state represents the CXL driver/device state. It provides an 205 * interface to mailbox commands as well as some cached data about the device. 206 * Currently only memory devices are represented. 207 * 208 * @dev: The device associated with this CXL state 209 * @cxlmd: The device representing the CXL.mem capabilities of @dev 210 * @regs: Parsed register blocks 211 * @cxl_dvsec: Offset to the PCIe device DVSEC 212 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 213 * @payload_size: Size of space for payload 214 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 215 * @lsa_size: Size of Label Storage Area 216 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 217 * @mbox_mutex: Mutex to synchronize mailbox access. 218 * @firmware_version: Firmware version for the memory device. 219 * @enabled_cmds: Hardware commands found enabled in CEL. 220 * @exclusive_cmds: Commands that are kernel-internal only 221 * @dpa_res: Overall DPA resource tree for the device 222 * @pmem_res: Active Persistent memory capacity configuration 223 * @ram_res: Active Volatile memory capacity configuration 224 * @total_bytes: sum of all possible capacities 225 * @volatile_only_bytes: hard volatile capacity 226 * @persistent_only_bytes: hard persistent capacity 227 * @partition_align_bytes: alignment size for partition-able capacity 228 * @active_volatile_bytes: sum of hard + soft volatile 229 * @active_persistent_bytes: sum of hard + soft persistent 230 * @next_volatile_bytes: volatile capacity change pending device reset 231 * @next_persistent_bytes: persistent capacity change pending device reset 232 * @component_reg_phys: register base of component registers 233 * @info: Cached DVSEC information about the device. 234 * @serial: PCIe Device Serial Number 235 * @doe_mbs: PCI DOE mailbox array 236 * @mbox_send: @dev specific transport for transmitting mailbox commands 237 * 238 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 239 * details on capacity parameters. 240 */ 241 struct cxl_dev_state { 242 struct device *dev; 243 struct cxl_memdev *cxlmd; 244 245 struct cxl_regs regs; 246 int cxl_dvsec; 247 248 bool rcd; 249 size_t payload_size; 250 size_t lsa_size; 251 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 252 char firmware_version[0x10]; 253 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 254 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 255 256 struct resource dpa_res; 257 struct resource pmem_res; 258 struct resource ram_res; 259 u64 total_bytes; 260 u64 volatile_only_bytes; 261 u64 persistent_only_bytes; 262 u64 partition_align_bytes; 263 264 u64 active_volatile_bytes; 265 u64 active_persistent_bytes; 266 u64 next_volatile_bytes; 267 u64 next_persistent_bytes; 268 269 resource_size_t component_reg_phys; 270 u64 serial; 271 272 struct xarray doe_mbs; 273 274 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); 275 }; 276 277 enum cxl_opcode { 278 CXL_MBOX_OP_INVALID = 0x0000, 279 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 280 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 281 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 282 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 283 CXL_MBOX_OP_GET_LOG = 0x0401, 284 CXL_MBOX_OP_IDENTIFY = 0x4000, 285 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 286 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 287 CXL_MBOX_OP_GET_LSA = 0x4102, 288 CXL_MBOX_OP_SET_LSA = 0x4103, 289 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 290 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 291 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 292 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 293 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 294 CXL_MBOX_OP_GET_POISON = 0x4300, 295 CXL_MBOX_OP_INJECT_POISON = 0x4301, 296 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 297 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 298 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 299 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 300 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 301 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 302 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 303 CXL_MBOX_OP_UNLOCK = 0x4503, 304 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 305 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 306 CXL_MBOX_OP_MAX = 0x10000 307 }; 308 309 #define DEFINE_CXL_CEL_UUID \ 310 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 311 0x3b, 0x3f, 0x17) 312 313 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 314 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 315 0x40, 0x3d, 0x86) 316 317 struct cxl_mbox_get_supported_logs { 318 __le16 entries; 319 u8 rsvd[6]; 320 struct cxl_gsl_entry { 321 uuid_t uuid; 322 __le32 size; 323 } __packed entry[]; 324 } __packed; 325 326 struct cxl_cel_entry { 327 __le16 opcode; 328 __le16 effect; 329 } __packed; 330 331 struct cxl_mbox_get_log { 332 uuid_t uuid; 333 __le32 offset; 334 __le32 length; 335 } __packed; 336 337 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 338 struct cxl_mbox_identify { 339 char fw_revision[0x10]; 340 __le64 total_capacity; 341 __le64 volatile_capacity; 342 __le64 persistent_capacity; 343 __le64 partition_align; 344 __le16 info_event_log_size; 345 __le16 warning_event_log_size; 346 __le16 failure_event_log_size; 347 __le16 fatal_event_log_size; 348 __le32 lsa_size; 349 u8 poison_list_max_mer[3]; 350 __le16 inject_poison_limit; 351 u8 poison_caps; 352 u8 qos_telemetry_caps; 353 } __packed; 354 355 struct cxl_mbox_get_partition_info { 356 __le64 active_volatile_cap; 357 __le64 active_persistent_cap; 358 __le64 next_volatile_cap; 359 __le64 next_persistent_cap; 360 } __packed; 361 362 struct cxl_mbox_get_lsa { 363 __le32 offset; 364 __le32 length; 365 } __packed; 366 367 struct cxl_mbox_set_lsa { 368 __le32 offset; 369 __le32 reserved; 370 u8 data[]; 371 } __packed; 372 373 struct cxl_mbox_set_partition_info { 374 __le64 volatile_capacity; 375 u8 flags; 376 } __packed; 377 378 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 379 380 /** 381 * struct cxl_mem_command - Driver representation of a memory device command 382 * @info: Command information as it exists for the UAPI 383 * @opcode: The actual bits used for the mailbox protocol 384 * @flags: Set of flags effecting driver behavior. 385 * 386 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 387 * will be enabled by the driver regardless of what hardware may have 388 * advertised. 389 * 390 * The cxl_mem_command is the driver's internal representation of commands that 391 * are supported by the driver. Some of these commands may not be supported by 392 * the hardware. The driver will use @info to validate the fields passed in by 393 * the user then submit the @opcode to the hardware. 394 * 395 * See struct cxl_command_info. 396 */ 397 struct cxl_mem_command { 398 struct cxl_command_info info; 399 enum cxl_opcode opcode; 400 u32 flags; 401 #define CXL_CMD_FLAG_NONE 0 402 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 403 }; 404 405 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 406 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 407 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 408 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 409 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 410 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 411 412 /* set passphrase input payload */ 413 struct cxl_set_pass { 414 u8 type; 415 u8 reserved[31]; 416 /* CXL field using NVDIMM define, same length */ 417 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 418 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 419 } __packed; 420 421 /* disable passphrase input payload */ 422 struct cxl_disable_pass { 423 u8 type; 424 u8 reserved[31]; 425 u8 pass[NVDIMM_PASSPHRASE_LEN]; 426 } __packed; 427 428 /* passphrase secure erase payload */ 429 struct cxl_pass_erase { 430 u8 type; 431 u8 reserved[31]; 432 u8 pass[NVDIMM_PASSPHRASE_LEN]; 433 } __packed; 434 435 enum { 436 CXL_PMEM_SEC_PASS_MASTER = 0, 437 CXL_PMEM_SEC_PASS_USER, 438 }; 439 440 int cxl_internal_send_cmd(struct cxl_dev_state *cxlds, 441 struct cxl_mbox_cmd *cmd); 442 int cxl_dev_state_identify(struct cxl_dev_state *cxlds); 443 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 444 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds); 445 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); 446 struct cxl_dev_state *cxl_dev_state_create(struct device *dev); 447 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 448 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 449 #ifdef CONFIG_CXL_SUSPEND 450 void cxl_mem_active_inc(void); 451 void cxl_mem_active_dec(void); 452 #else 453 static inline void cxl_mem_active_inc(void) 454 { 455 } 456 static inline void cxl_mem_active_dec(void) 457 { 458 } 459 #endif 460 461 struct cxl_hdm { 462 struct cxl_component_regs regs; 463 unsigned int decoder_count; 464 unsigned int target_count; 465 unsigned int interleave_mask; 466 struct cxl_port *port; 467 }; 468 469 struct seq_file; 470 struct dentry *cxl_debugfs_create_dir(const char *dir); 471 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 472 #endif /* __CXL_MEM_H__ */ 473