1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/pci.h> 7 #include <linux/cdev.h> 8 #include <linux/uuid.h> 9 #include <linux/node.h> 10 #include <cxl/event.h> 11 #include <cxl/mailbox.h> 12 #include "cxl.h" 13 14 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 15 #define CXLMDEV_STATUS_OFFSET 0x0 16 #define CXLMDEV_DEV_FATAL BIT(0) 17 #define CXLMDEV_FW_HALT BIT(1) 18 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 19 #define CXLMDEV_MS_NOT_READY 0 20 #define CXLMDEV_MS_READY 1 21 #define CXLMDEV_MS_ERROR 2 22 #define CXLMDEV_MS_DISABLED 3 23 #define CXLMDEV_READY(status) \ 24 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 25 CXLMDEV_MS_READY) 26 #define CXLMDEV_MBOX_IF_READY BIT(4) 27 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 28 #define CXLMDEV_RESET_NEEDED_NOT 0 29 #define CXLMDEV_RESET_NEEDED_COLD 1 30 #define CXLMDEV_RESET_NEEDED_WARM 2 31 #define CXLMDEV_RESET_NEEDED_HOT 3 32 #define CXLMDEV_RESET_NEEDED_CXL 4 33 #define CXLMDEV_RESET_NEEDED(status) \ 34 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 35 CXLMDEV_RESET_NEEDED_NOT) 36 37 /** 38 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 39 * @dev: driver core device object 40 * @cdev: char dev core object for ioctl operations 41 * @cxlds: The device state backing this device 42 * @detach_work: active memdev lost a port in its ancestry 43 * @cxl_nvb: coordinate removal of @cxl_nvd if present 44 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 45 * @endpoint: connection to the CXL port topology for this memory device 46 * @attach: creator of this memdev depends on CXL link attach to operate 47 * @id: id number of this memdev instance. 48 * @depth: endpoint port depth 49 * @scrub_cycle: current scrub cycle set for this device 50 * @scrub_region_id: id number of a backed region (if any) for which current scrub cycle set 51 * @err_rec_array: List of xarrarys to store the memdev error records to 52 * check attributes for a memory repair operation are from 53 * current boot. 54 */ 55 struct cxl_memdev { 56 struct device dev; 57 struct cdev cdev; 58 struct cxl_dev_state *cxlds; 59 struct work_struct detach_work; 60 struct cxl_nvdimm_bridge *cxl_nvb; 61 struct cxl_nvdimm *cxl_nvd; 62 struct cxl_port *endpoint; 63 const struct cxl_memdev_attach *attach; 64 int id; 65 int depth; 66 u8 scrub_cycle; 67 int scrub_region_id; 68 struct cxl_mem_err_rec *err_rec_array; 69 }; 70 71 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 72 { 73 return container_of(dev, struct cxl_memdev, dev); 74 } 75 76 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 77 { 78 return to_cxl_port(cxled->cxld.dev.parent); 79 } 80 81 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 82 { 83 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 84 } 85 86 static inline struct cxl_memdev * 87 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 88 { 89 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 90 91 return to_cxl_memdev(port->uport_dev); 92 } 93 94 bool is_cxl_memdev(const struct device *dev); 95 static inline bool is_cxl_endpoint(struct cxl_port *port) 96 { 97 return is_cxl_memdev(port->uport_dev); 98 } 99 100 struct cxl_memdev_attach { 101 int (*probe)(struct cxl_memdev *cxlmd); 102 }; 103 104 /** 105 * struct cxl_attach_region - coordinate mapping a region at memdev registration 106 * @attach: common core attachment descriptor 107 * @hpa_range: physical address range of the region 108 * 109 * For the common simple case of a CXL device with private (non-general purpose 110 * / "accelerator") memory, enumerate firmware instantiated region, or 111 * instantiate a region for the device's capacity. Destroy the region on detach. 112 */ 113 struct cxl_attach_region { 114 struct cxl_memdev_attach attach; 115 struct range hpa_range; 116 }; 117 118 #ifdef CONFIG_CXL_REGION 119 int cxl_memdev_attach_region(struct cxl_memdev *cxlmd); 120 #else 121 static inline int cxl_memdev_attach_region(struct cxl_memdev *cxlmd) 122 { 123 return -EOPNOTSUPP; 124 } 125 #endif 126 127 struct cxl_memdev *devm_cxl_add_classdev(struct cxl_dev_state *cxlds); 128 struct cxl_memdev *__devm_cxl_add_memdev(struct cxl_dev_state *cxlds, 129 const struct cxl_memdev_attach *attach); 130 int devm_cxl_sanitize_setup_notifier(struct device *host, 131 struct cxl_memdev *cxlmd); 132 struct cxl_memdev_state; 133 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds); 134 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 135 resource_size_t base, resource_size_t len, 136 resource_size_t skipped); 137 138 struct cxl_dpa_info { 139 u64 size; 140 struct cxl_dpa_part_info { 141 struct range range; 142 enum cxl_partition_mode mode; 143 } part[CXL_NR_PARTITIONS_MAX]; 144 int nr_partitions; 145 }; 146 147 int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info); 148 149 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 150 struct cxl_memdev *cxlmd) 151 { 152 if (!port) 153 return NULL; 154 155 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 156 } 157 158 /* 159 * Per CXL 3.0 Section 8.2.8.4.5.1 160 */ 161 #define CMD_CMD_RC_TABLE \ 162 C(SUCCESS, 0, NULL), \ 163 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 164 C(INPUT, -ENXIO, "cmd input was invalid"), \ 165 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 166 C(INTERNAL, -ENXIO, "internal device error"), \ 167 C(RETRY, -ENXIO, "temporary error, retry once"), \ 168 C(BUSY, -ENXIO, "ongoing background operation"), \ 169 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 170 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 171 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 172 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 173 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 174 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 175 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 176 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 177 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 178 C(POISONLMT, -EBUSY, "poison injection limit has been reached"), \ 179 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 180 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 181 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 182 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 183 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 184 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 185 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 186 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 187 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 188 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 189 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 190 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 191 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 192 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 193 194 #undef C 195 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 196 enum { CMD_CMD_RC_TABLE }; 197 #undef C 198 #define C(a, b, c) { b, c } 199 struct cxl_mbox_cmd_rc { 200 int err; 201 const char *desc; 202 }; 203 204 static const 205 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 206 #undef C 207 208 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 209 { 210 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 211 } 212 213 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 214 { 215 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 216 } 217 218 /* 219 * CXL 2.0 - Memory capacity multiplier 220 * See Section 8.2.9.5 221 * 222 * Volatile, Persistent, and Partition capacities are specified to be in 223 * multiples of 256MB - define a multiplier to convert to/from bytes. 224 */ 225 #define CXL_CAPACITY_MULTIPLIER SZ_256M 226 227 /* 228 * Event Interrupt Policy 229 * 230 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 231 */ 232 enum cxl_event_int_mode { 233 CXL_INT_NONE = 0x00, 234 CXL_INT_MSI_MSIX = 0x01, 235 CXL_INT_FW = 0x02 236 }; 237 struct cxl_event_interrupt_policy { 238 u8 info_settings; 239 u8 warn_settings; 240 u8 failure_settings; 241 u8 fatal_settings; 242 } __packed; 243 244 /** 245 * struct cxl_event_state - Event log driver state 246 * 247 * @buf: Buffer to receive event data 248 * @log_lock: Serialize event_buf and log use 249 */ 250 struct cxl_event_state { 251 struct cxl_get_event_payload *buf; 252 struct mutex log_lock; 253 }; 254 255 /* Device enabled poison commands */ 256 enum poison_cmd_enabled_bits { 257 CXL_POISON_ENABLED_LIST, 258 CXL_POISON_ENABLED_INJECT, 259 CXL_POISON_ENABLED_CLEAR, 260 CXL_POISON_ENABLED_SCAN_CAPS, 261 CXL_POISON_ENABLED_SCAN_MEDIA, 262 CXL_POISON_ENABLED_SCAN_RESULTS, 263 CXL_POISON_ENABLED_MAX 264 }; 265 266 /* Device enabled security commands */ 267 enum security_cmd_enabled_bits { 268 CXL_SEC_ENABLED_SANITIZE, 269 CXL_SEC_ENABLED_SECURE_ERASE, 270 CXL_SEC_ENABLED_GET_SECURITY_STATE, 271 CXL_SEC_ENABLED_SET_PASSPHRASE, 272 CXL_SEC_ENABLED_DISABLE_PASSPHRASE, 273 CXL_SEC_ENABLED_UNLOCK, 274 CXL_SEC_ENABLED_FREEZE_SECURITY, 275 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE, 276 CXL_SEC_ENABLED_MAX 277 }; 278 279 /** 280 * struct cxl_poison_state - Driver poison state info 281 * 282 * @max_errors: Maximum media error records held in device cache 283 * @enabled_cmds: All poison commands enabled in the CEL 284 * @list_out: The poison list payload returned by device 285 * @mutex: Protect reads of the poison list 286 * 287 * Reads of the poison list are synchronized to ensure that a reader 288 * does not get an incomplete list because their request overlapped 289 * (was interrupted or preceded by) another read request of the same 290 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 291 */ 292 struct cxl_poison_state { 293 u32 max_errors; 294 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 295 struct cxl_mbox_poison_out *list_out; 296 struct mutex mutex; /* Protect reads of poison list */ 297 }; 298 299 /* 300 * Get FW Info 301 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56 302 */ 303 struct cxl_mbox_get_fw_info { 304 u8 num_slots; 305 u8 slot_info; 306 u8 activation_cap; 307 u8 reserved[13]; 308 char slot_1_revision[16]; 309 char slot_2_revision[16]; 310 char slot_3_revision[16]; 311 char slot_4_revision[16]; 312 } __packed; 313 314 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0) 315 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3) 316 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 317 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0) 318 319 /* 320 * Transfer FW Input Payload 321 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57 322 */ 323 struct cxl_mbox_transfer_fw { 324 u8 action; 325 u8 slot; 326 u8 reserved[2]; 327 __le32 offset; 328 u8 reserved2[0x78]; 329 u8 data[]; 330 } __packed; 331 332 #define CXL_FW_TRANSFER_ACTION_FULL 0x0 333 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1 334 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2 335 #define CXL_FW_TRANSFER_ACTION_END 0x3 336 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4 337 338 /* 339 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages 340 * and for each part transferred in a Transfer FW command. 341 */ 342 #define CXL_FW_TRANSFER_ALIGNMENT 128 343 344 /* 345 * Activate FW Input Payload 346 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58 347 */ 348 struct cxl_mbox_activate_fw { 349 u8 action; 350 u8 slot; 351 } __packed; 352 353 #define CXL_FW_ACTIVATE_ONLINE 0x0 354 #define CXL_FW_ACTIVATE_OFFLINE 0x1 355 356 /* FW state bits */ 357 #define CXL_FW_STATE_BITS 32 358 #define CXL_FW_CANCEL 0 359 360 /** 361 * struct cxl_fw_state - Firmware upload / activation state 362 * 363 * @state: fw_uploader state bitmask 364 * @oneshot: whether the fw upload fits in a single transfer 365 * @num_slots: Number of FW slots available 366 * @cur_slot: Slot number currently active 367 * @next_slot: Slot number for the new firmware 368 */ 369 struct cxl_fw_state { 370 DECLARE_BITMAP(state, CXL_FW_STATE_BITS); 371 bool oneshot; 372 int num_slots; 373 int cur_slot; 374 int next_slot; 375 }; 376 377 /** 378 * struct cxl_security_state - Device security state 379 * 380 * @state: state of last security operation 381 * @enabled_cmds: All security commands enabled in the CEL 382 * @poll_tmo_secs: polling timeout 383 * @sanitize_active: sanitize completion pending 384 * @poll_dwork: polling work item 385 * @sanitize_node: sanitation sysfs file to notify 386 */ 387 struct cxl_security_state { 388 unsigned long state; 389 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX); 390 int poll_tmo_secs; 391 bool sanitize_active; 392 struct delayed_work poll_dwork; 393 struct kernfs_node *sanitize_node; 394 }; 395 396 static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds) 397 { 398 /* 399 * Static PMEM may be at partition index 0 when there is no static RAM 400 * capacity. 401 */ 402 for (int i = 0; i < cxlds->nr_partitions; i++) 403 if (cxlds->part[i].mode == CXL_PARTMODE_PMEM) 404 return resource_size(&cxlds->part[i].res); 405 return 0; 406 } 407 408 static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox) 409 { 410 return dev_get_drvdata(cxl_mbox->host); 411 } 412 413 /** 414 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data 415 * 416 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines 417 * common memory device functionality like the presence of a mailbox and 418 * the functionality related to that like Identify Memory Device and Get 419 * Partition Info 420 * @cxlds: Core driver state common across Type-2 and Type-3 devices 421 * @lsa_size: Size of Label Storage Area 422 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 423 * @firmware_version: Firmware version for the memory device. 424 * @total_bytes: sum of all possible capacities 425 * @volatile_only_bytes: hard volatile capacity 426 * @persistent_only_bytes: hard persistent capacity 427 * @partition_align_bytes: alignment size for partition-able capacity 428 * @active_volatile_bytes: sum of hard + soft volatile 429 * @active_persistent_bytes: sum of hard + soft persistent 430 * @event: event log driver state 431 * @poison: poison driver state info 432 * @security: security driver state info 433 * @fw: firmware upload / activation state 434 * @mce_notifier: MCE notifier 435 * 436 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for 437 * details on capacity parameters. 438 */ 439 struct cxl_memdev_state { 440 struct cxl_dev_state cxlds; 441 size_t lsa_size; 442 char firmware_version[0x10]; 443 u64 total_bytes; 444 u64 volatile_only_bytes; 445 u64 persistent_only_bytes; 446 u64 partition_align_bytes; 447 u64 active_volatile_bytes; 448 u64 active_persistent_bytes; 449 450 struct cxl_event_state event; 451 struct cxl_poison_state poison; 452 struct cxl_security_state security; 453 struct cxl_fw_state fw; 454 struct notifier_block mce_notifier; 455 }; 456 457 static inline struct cxl_memdev_state * 458 to_cxl_memdev_state(struct cxl_dev_state *cxlds) 459 { 460 if (cxlds->type != CXL_DEVTYPE_CLASSMEM) 461 return NULL; 462 return container_of(cxlds, struct cxl_memdev_state, cxlds); 463 } 464 465 enum cxl_opcode { 466 CXL_MBOX_OP_INVALID = 0x0000, 467 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 468 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 469 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 470 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 471 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 472 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 473 CXL_MBOX_OP_TRANSFER_FW = 0x0201, 474 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 475 CXL_MBOX_OP_GET_TIMESTAMP = 0x0300, 476 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 477 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 478 CXL_MBOX_OP_GET_LOG = 0x0401, 479 CXL_MBOX_OP_GET_LOG_CAPS = 0x0402, 480 CXL_MBOX_OP_CLEAR_LOG = 0x0403, 481 CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405, 482 CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, 483 CXL_MBOX_OP_GET_FEATURE = 0x0501, 484 CXL_MBOX_OP_SET_FEATURE = 0x0502, 485 CXL_MBOX_OP_DO_MAINTENANCE = 0x0600, 486 CXL_MBOX_OP_IDENTIFY = 0x4000, 487 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 488 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 489 CXL_MBOX_OP_GET_LSA = 0x4102, 490 CXL_MBOX_OP_SET_LSA = 0x4103, 491 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 492 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 493 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 494 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 495 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 496 CXL_MBOX_OP_GET_POISON = 0x4300, 497 CXL_MBOX_OP_INJECT_POISON = 0x4301, 498 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 499 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 500 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 501 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 502 CXL_MBOX_OP_SANITIZE = 0x4400, 503 CXL_MBOX_OP_SECURE_ERASE = 0x4401, 504 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 505 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 506 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 507 CXL_MBOX_OP_UNLOCK = 0x4503, 508 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 509 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 510 CXL_MBOX_OP_MAX = 0x10000 511 }; 512 513 #define DEFINE_CXL_CEL_UUID \ 514 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 515 0x3b, 0x3f, 0x17) 516 517 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 518 UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 519 0x40, 0x3d, 0x86) 520 521 struct cxl_mbox_get_supported_logs { 522 __le16 entries; 523 u8 rsvd[6]; 524 struct cxl_gsl_entry { 525 uuid_t uuid; 526 __le32 size; 527 } __packed entry[]; 528 } __packed; 529 530 struct cxl_cel_entry { 531 __le16 opcode; 532 __le16 effect; 533 } __packed; 534 535 struct cxl_mbox_get_log { 536 uuid_t uuid; 537 __le32 offset; 538 __le32 length; 539 } __packed; 540 541 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 542 struct cxl_mbox_identify { 543 char fw_revision[0x10]; 544 __le64 total_capacity; 545 __le64 volatile_capacity; 546 __le64 persistent_capacity; 547 __le64 partition_align; 548 __le16 info_event_log_size; 549 __le16 warning_event_log_size; 550 __le16 failure_event_log_size; 551 __le16 fatal_event_log_size; 552 __le32 lsa_size; 553 u8 poison_list_max_mer[3]; 554 __le16 inject_poison_limit; 555 u8 poison_caps; 556 u8 qos_telemetry_caps; 557 } __packed; 558 559 /* 560 * General Media Event Record UUID 561 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 562 */ 563 #define CXL_EVENT_GEN_MEDIA_UUID \ 564 UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \ 565 0x21, 0xeb, 0xa6) 566 567 /* 568 * DRAM Event Record UUID 569 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 570 */ 571 #define CXL_EVENT_DRAM_UUID \ 572 UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \ 573 0x5c, 0x96, 0x24) 574 575 /* 576 * Memory Module Event Record UUID 577 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 578 */ 579 #define CXL_EVENT_MEM_MODULE_UUID \ 580 UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \ 581 0x13, 0xb7, 0x74) 582 583 /* 584 * Memory Sparing Event Record UUID 585 * CXL rev 3.2 section 8.2.10.2.1.4: Table 8-60 586 */ 587 #define CXL_EVENT_MEM_SPARING_UUID \ 588 UUID_INIT(0xe71f3a40, 0x2d29, 0x4092, 0x8a, 0x39, 0x4d, 0x1c, 0x96, \ 589 0x6c, 0x7c, 0x65) 590 591 /* 592 * Get Event Records output payload 593 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 594 */ 595 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 596 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 597 struct cxl_get_event_payload { 598 u8 flags; 599 u8 reserved1; 600 __le16 overflow_err_count; 601 __le64 first_overflow_timestamp; 602 __le64 last_overflow_timestamp; 603 __le16 record_count; 604 u8 reserved2[10]; 605 struct cxl_event_record_raw records[]; 606 } __packed; 607 608 /* 609 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 610 */ 611 enum cxl_event_log_type { 612 CXL_EVENT_TYPE_INFO = 0x00, 613 CXL_EVENT_TYPE_WARN, 614 CXL_EVENT_TYPE_FAIL, 615 CXL_EVENT_TYPE_FATAL, 616 CXL_EVENT_TYPE_MAX 617 }; 618 619 /* 620 * Clear Event Records input payload 621 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 622 */ 623 struct cxl_mbox_clear_event_payload { 624 u8 event_log; /* enum cxl_event_log_type */ 625 u8 clear_flags; 626 u8 nr_recs; 627 u8 reserved[3]; 628 __le16 handles[]; 629 } __packed; 630 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 631 632 struct cxl_mbox_get_partition_info { 633 __le64 active_volatile_cap; 634 __le64 active_persistent_cap; 635 __le64 next_volatile_cap; 636 __le64 next_persistent_cap; 637 } __packed; 638 639 struct cxl_mbox_get_lsa { 640 __le32 offset; 641 __le32 length; 642 } __packed; 643 644 struct cxl_mbox_set_lsa { 645 __le32 offset; 646 __le32 reserved; 647 u8 data[]; 648 } __packed; 649 650 struct cxl_mbox_set_partition_info { 651 __le64 volatile_capacity; 652 u8 flags; 653 } __packed; 654 655 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 656 657 /* Get Health Info Output Payload CXL 3.2 Spec 8.2.10.9.3.1 Table 8-148 */ 658 struct cxl_mbox_get_health_info_out { 659 u8 health_status; 660 u8 media_status; 661 u8 additional_status; 662 u8 life_used; 663 __le16 device_temperature; 664 __le32 dirty_shutdown_cnt; 665 __le32 corrected_volatile_error_cnt; 666 __le32 corrected_persistent_error_cnt; 667 } __packed; 668 669 /* Set Shutdown State Input Payload CXL 3.2 Spec 8.2.10.9.3.5 Table 8-152 */ 670 struct cxl_mbox_set_shutdown_state_in { 671 u8 state; 672 } __packed; 673 674 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 675 struct cxl_mbox_set_timestamp_in { 676 __le64 timestamp; 677 678 } __packed; 679 680 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 681 struct cxl_mbox_poison_in { 682 __le64 offset; 683 __le64 length; 684 } __packed; 685 686 struct cxl_mbox_poison_out { 687 u8 flags; 688 u8 rsvd1; 689 __le64 overflow_ts; 690 __le16 count; 691 u8 rsvd2[20]; 692 struct cxl_poison_record { 693 __le64 address; 694 __le32 length; 695 __le32 rsvd; 696 } __packed record[]; 697 } __packed; 698 699 /* 700 * Get Poison List address field encodes the starting 701 * address of poison, and the source of the poison. 702 */ 703 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 704 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 705 706 /* Get Poison List record length is in units of 64 bytes */ 707 #define CXL_POISON_LEN_MULT 64 708 709 /* Kernel defined maximum for a list of poison errors */ 710 #define CXL_POISON_LIST_MAX 1024 711 712 /* Get Poison List: Payload out flags */ 713 #define CXL_POISON_FLAG_MORE BIT(0) 714 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 715 #define CXL_POISON_FLAG_SCANNING BIT(2) 716 717 /* Get Poison List: Poison Source */ 718 #define CXL_POISON_SOURCE_UNKNOWN 0 719 #define CXL_POISON_SOURCE_EXTERNAL 1 720 #define CXL_POISON_SOURCE_INTERNAL 2 721 #define CXL_POISON_SOURCE_INJECTED 3 722 #define CXL_POISON_SOURCE_VENDOR 7 723 724 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 725 struct cxl_mbox_inject_poison { 726 __le64 address; 727 }; 728 729 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 730 struct cxl_mbox_clear_poison { 731 __le64 address; 732 u8 write_data[CXL_POISON_LEN_MULT]; 733 } __packed; 734 735 /** 736 * struct cxl_mem_command - Driver representation of a memory device command 737 * @info: Command information as it exists for the UAPI 738 * @opcode: The actual bits used for the mailbox protocol 739 * @flags: Set of flags effecting driver behavior. 740 * 741 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 742 * will be enabled by the driver regardless of what hardware may have 743 * advertised. 744 * 745 * The cxl_mem_command is the driver's internal representation of commands that 746 * are supported by the driver. Some of these commands may not be supported by 747 * the hardware. The driver will use @info to validate the fields passed in by 748 * the user then submit the @opcode to the hardware. 749 * 750 * See struct cxl_command_info. 751 */ 752 struct cxl_mem_command { 753 struct cxl_command_info info; 754 enum cxl_opcode opcode; 755 u32 flags; 756 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 757 }; 758 759 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 760 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 761 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 762 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 763 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 764 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 765 766 /* set passphrase input payload */ 767 struct cxl_set_pass { 768 u8 type; 769 u8 reserved[31]; 770 /* CXL field using NVDIMM define, same length */ 771 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 772 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 773 } __packed; 774 775 /* disable passphrase input payload */ 776 struct cxl_disable_pass { 777 u8 type; 778 u8 reserved[31]; 779 u8 pass[NVDIMM_PASSPHRASE_LEN]; 780 } __packed; 781 782 /* passphrase secure erase payload */ 783 struct cxl_pass_erase { 784 u8 type; 785 u8 reserved[31]; 786 u8 pass[NVDIMM_PASSPHRASE_LEN]; 787 } __packed; 788 789 enum { 790 CXL_PMEM_SEC_PASS_MASTER = 0, 791 CXL_PMEM_SEC_PASS_USER, 792 }; 793 794 int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, 795 struct cxl_mbox_cmd *cmd); 796 int cxl_dev_state_identify(struct cxl_memdev_state *mds); 797 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 798 int cxl_enumerate_cmds(struct cxl_memdev_state *mds); 799 int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info); 800 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial, 801 u16 dvsec); 802 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 803 unsigned long *cmds); 804 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 805 unsigned long *cmds); 806 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status); 807 void cxl_event_trace_record(struct cxl_memdev *cxlmd, 808 enum cxl_event_log_type type, 809 enum cxl_event_type event_type, 810 const uuid_t *uuid, union cxl_event *evt); 811 int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count); 812 int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds); 813 int cxl_set_timestamp(struct cxl_memdev_state *mds); 814 int cxl_poison_state_init(struct cxl_memdev_state *mds); 815 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 816 struct cxl_region *cxlr); 817 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 818 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 819 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 820 int cxl_inject_poison_locked(struct cxl_memdev *cxlmd, u64 dpa); 821 int cxl_clear_poison_locked(struct cxl_memdev *cxlmd, u64 dpa); 822 823 #ifdef CONFIG_CXL_EDAC_MEM_FEATURES 824 int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd); 825 int devm_cxl_region_edac_register(struct cxl_region *cxlr); 826 int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, union cxl_event *evt); 827 int cxl_store_rec_dram(struct cxl_memdev *cxlmd, union cxl_event *evt); 828 #else 829 static inline int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd) 830 { return 0; } 831 static inline int devm_cxl_region_edac_register(struct cxl_region *cxlr) 832 { return 0; } 833 static inline int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, 834 union cxl_event *evt) 835 { return 0; } 836 static inline int cxl_store_rec_dram(struct cxl_memdev *cxlmd, 837 union cxl_event *evt) 838 { return 0; } 839 #endif 840 841 #ifdef CONFIG_CXL_SUSPEND 842 void cxl_mem_active_inc(void); 843 void cxl_mem_active_dec(void); 844 #else 845 static inline void cxl_mem_active_inc(void) 846 { 847 } 848 static inline void cxl_mem_active_dec(void) 849 { 850 } 851 #endif 852 853 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd); 854 855 /** 856 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities 857 * @regs: mapped registers, see devm_cxl_setup_hdm() 858 * @decoder_count: number of decoders for this port 859 * @target_count: for switch decoders, max downstream port targets 860 * @interleave_mask: interleave granularity capability, see check_interleave_cap() 861 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap() 862 * @port: mapped cxl_port, see devm_cxl_setup_hdm() 863 */ 864 struct cxl_hdm { 865 struct cxl_component_regs regs; 866 int decoder_count; 867 unsigned int target_count; 868 unsigned int interleave_mask; 869 unsigned long iw_cap_mask; 870 struct cxl_port *port; 871 }; 872 873 struct seq_file; 874 struct dentry *cxl_debugfs_create_dir(const char *dir); 875 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 876 #endif /* __CXL_MEM_H__ */ 877