1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/pci.h> 7 #include <linux/cdev.h> 8 #include <linux/uuid.h> 9 #include <linux/node.h> 10 #include <cxl/event.h> 11 #include <cxl/mailbox.h> 12 #include "cxl.h" 13 14 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 15 #define CXLMDEV_STATUS_OFFSET 0x0 16 #define CXLMDEV_DEV_FATAL BIT(0) 17 #define CXLMDEV_FW_HALT BIT(1) 18 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 19 #define CXLMDEV_MS_NOT_READY 0 20 #define CXLMDEV_MS_READY 1 21 #define CXLMDEV_MS_ERROR 2 22 #define CXLMDEV_MS_DISABLED 3 23 #define CXLMDEV_READY(status) \ 24 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 25 CXLMDEV_MS_READY) 26 #define CXLMDEV_MBOX_IF_READY BIT(4) 27 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 28 #define CXLMDEV_RESET_NEEDED_NOT 0 29 #define CXLMDEV_RESET_NEEDED_COLD 1 30 #define CXLMDEV_RESET_NEEDED_WARM 2 31 #define CXLMDEV_RESET_NEEDED_HOT 3 32 #define CXLMDEV_RESET_NEEDED_CXL 4 33 #define CXLMDEV_RESET_NEEDED(status) \ 34 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 35 CXLMDEV_RESET_NEEDED_NOT) 36 37 struct cxl_memdev_attach { 38 int (*probe)(struct cxl_memdev *cxlmd); 39 }; 40 41 /** 42 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 43 * @dev: driver core device object 44 * @cdev: char dev core object for ioctl operations 45 * @cxlds: The device state backing this device 46 * @detach_work: active memdev lost a port in its ancestry 47 * @cxl_nvb: coordinate removal of @cxl_nvd if present 48 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 49 * @endpoint: connection to the CXL port topology for this memory device 50 * @attach: creator of this memdev depends on CXL link attach to operate 51 * @id: id number of this memdev instance. 52 * @depth: endpoint port depth 53 * @scrub_cycle: current scrub cycle set for this device 54 * @scrub_region_id: id number of a backed region (if any) for which current scrub cycle set 55 * @err_rec_array: List of xarrarys to store the memdev error records to 56 * check attributes for a memory repair operation are from 57 * current boot. 58 */ 59 struct cxl_memdev { 60 struct device dev; 61 struct cdev cdev; 62 struct cxl_dev_state *cxlds; 63 struct work_struct detach_work; 64 struct cxl_nvdimm_bridge *cxl_nvb; 65 struct cxl_nvdimm *cxl_nvd; 66 struct cxl_port *endpoint; 67 const struct cxl_memdev_attach *attach; 68 int id; 69 int depth; 70 u8 scrub_cycle; 71 int scrub_region_id; 72 struct cxl_mem_err_rec *err_rec_array; 73 }; 74 75 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 76 { 77 return container_of(dev, struct cxl_memdev, dev); 78 } 79 80 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 81 { 82 return to_cxl_port(cxled->cxld.dev.parent); 83 } 84 85 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 86 { 87 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 88 } 89 90 static inline struct cxl_memdev * 91 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 92 { 93 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 94 95 return to_cxl_memdev(port->uport_dev); 96 } 97 98 bool is_cxl_memdev(const struct device *dev); 99 static inline bool is_cxl_endpoint(struct cxl_port *port) 100 { 101 return is_cxl_memdev(port->uport_dev); 102 } 103 104 struct cxl_memdev *__devm_cxl_add_memdev(struct cxl_dev_state *cxlds, 105 const struct cxl_memdev_attach *attach); 106 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds, 107 const struct cxl_memdev_attach *attach); 108 int devm_cxl_sanitize_setup_notifier(struct device *host, 109 struct cxl_memdev *cxlmd); 110 struct cxl_memdev_state; 111 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds); 112 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 113 resource_size_t base, resource_size_t len, 114 resource_size_t skipped); 115 116 struct cxl_dpa_info { 117 u64 size; 118 struct cxl_dpa_part_info { 119 struct range range; 120 enum cxl_partition_mode mode; 121 } part[CXL_NR_PARTITIONS_MAX]; 122 int nr_partitions; 123 }; 124 125 int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info); 126 127 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 128 struct cxl_memdev *cxlmd) 129 { 130 if (!port) 131 return NULL; 132 133 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 134 } 135 136 /* 137 * Per CXL 3.0 Section 8.2.8.4.5.1 138 */ 139 #define CMD_CMD_RC_TABLE \ 140 C(SUCCESS, 0, NULL), \ 141 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 142 C(INPUT, -ENXIO, "cmd input was invalid"), \ 143 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 144 C(INTERNAL, -ENXIO, "internal device error"), \ 145 C(RETRY, -ENXIO, "temporary error, retry once"), \ 146 C(BUSY, -ENXIO, "ongoing background operation"), \ 147 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 148 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 149 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 150 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 151 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 152 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 153 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 154 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 155 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 156 C(POISONLMT, -EBUSY, "poison injection limit has been reached"), \ 157 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 158 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 159 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 160 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 161 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 162 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 163 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 164 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 165 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 166 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 167 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 168 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 169 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 170 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 171 172 #undef C 173 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 174 enum { CMD_CMD_RC_TABLE }; 175 #undef C 176 #define C(a, b, c) { b, c } 177 struct cxl_mbox_cmd_rc { 178 int err; 179 const char *desc; 180 }; 181 182 static const 183 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 184 #undef C 185 186 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 187 { 188 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 189 } 190 191 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 192 { 193 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 194 } 195 196 /* 197 * CXL 2.0 - Memory capacity multiplier 198 * See Section 8.2.9.5 199 * 200 * Volatile, Persistent, and Partition capacities are specified to be in 201 * multiples of 256MB - define a multiplier to convert to/from bytes. 202 */ 203 #define CXL_CAPACITY_MULTIPLIER SZ_256M 204 205 /* 206 * Event Interrupt Policy 207 * 208 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 209 */ 210 enum cxl_event_int_mode { 211 CXL_INT_NONE = 0x00, 212 CXL_INT_MSI_MSIX = 0x01, 213 CXL_INT_FW = 0x02 214 }; 215 struct cxl_event_interrupt_policy { 216 u8 info_settings; 217 u8 warn_settings; 218 u8 failure_settings; 219 u8 fatal_settings; 220 } __packed; 221 222 /** 223 * struct cxl_event_state - Event log driver state 224 * 225 * @buf: Buffer to receive event data 226 * @log_lock: Serialize event_buf and log use 227 */ 228 struct cxl_event_state { 229 struct cxl_get_event_payload *buf; 230 struct mutex log_lock; 231 }; 232 233 /* Device enabled poison commands */ 234 enum poison_cmd_enabled_bits { 235 CXL_POISON_ENABLED_LIST, 236 CXL_POISON_ENABLED_INJECT, 237 CXL_POISON_ENABLED_CLEAR, 238 CXL_POISON_ENABLED_SCAN_CAPS, 239 CXL_POISON_ENABLED_SCAN_MEDIA, 240 CXL_POISON_ENABLED_SCAN_RESULTS, 241 CXL_POISON_ENABLED_MAX 242 }; 243 244 /* Device enabled security commands */ 245 enum security_cmd_enabled_bits { 246 CXL_SEC_ENABLED_SANITIZE, 247 CXL_SEC_ENABLED_SECURE_ERASE, 248 CXL_SEC_ENABLED_GET_SECURITY_STATE, 249 CXL_SEC_ENABLED_SET_PASSPHRASE, 250 CXL_SEC_ENABLED_DISABLE_PASSPHRASE, 251 CXL_SEC_ENABLED_UNLOCK, 252 CXL_SEC_ENABLED_FREEZE_SECURITY, 253 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE, 254 CXL_SEC_ENABLED_MAX 255 }; 256 257 /** 258 * struct cxl_poison_state - Driver poison state info 259 * 260 * @max_errors: Maximum media error records held in device cache 261 * @enabled_cmds: All poison commands enabled in the CEL 262 * @list_out: The poison list payload returned by device 263 * @mutex: Protect reads of the poison list 264 * 265 * Reads of the poison list are synchronized to ensure that a reader 266 * does not get an incomplete list because their request overlapped 267 * (was interrupted or preceded by) another read request of the same 268 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 269 */ 270 struct cxl_poison_state { 271 u32 max_errors; 272 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 273 struct cxl_mbox_poison_out *list_out; 274 struct mutex mutex; /* Protect reads of poison list */ 275 }; 276 277 /* 278 * Get FW Info 279 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56 280 */ 281 struct cxl_mbox_get_fw_info { 282 u8 num_slots; 283 u8 slot_info; 284 u8 activation_cap; 285 u8 reserved[13]; 286 char slot_1_revision[16]; 287 char slot_2_revision[16]; 288 char slot_3_revision[16]; 289 char slot_4_revision[16]; 290 } __packed; 291 292 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0) 293 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3) 294 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 295 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0) 296 297 /* 298 * Transfer FW Input Payload 299 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57 300 */ 301 struct cxl_mbox_transfer_fw { 302 u8 action; 303 u8 slot; 304 u8 reserved[2]; 305 __le32 offset; 306 u8 reserved2[0x78]; 307 u8 data[]; 308 } __packed; 309 310 #define CXL_FW_TRANSFER_ACTION_FULL 0x0 311 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1 312 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2 313 #define CXL_FW_TRANSFER_ACTION_END 0x3 314 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4 315 316 /* 317 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages 318 * and for each part transferred in a Transfer FW command. 319 */ 320 #define CXL_FW_TRANSFER_ALIGNMENT 128 321 322 /* 323 * Activate FW Input Payload 324 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58 325 */ 326 struct cxl_mbox_activate_fw { 327 u8 action; 328 u8 slot; 329 } __packed; 330 331 #define CXL_FW_ACTIVATE_ONLINE 0x0 332 #define CXL_FW_ACTIVATE_OFFLINE 0x1 333 334 /* FW state bits */ 335 #define CXL_FW_STATE_BITS 32 336 #define CXL_FW_CANCEL 0 337 338 /** 339 * struct cxl_fw_state - Firmware upload / activation state 340 * 341 * @state: fw_uploader state bitmask 342 * @oneshot: whether the fw upload fits in a single transfer 343 * @num_slots: Number of FW slots available 344 * @cur_slot: Slot number currently active 345 * @next_slot: Slot number for the new firmware 346 */ 347 struct cxl_fw_state { 348 DECLARE_BITMAP(state, CXL_FW_STATE_BITS); 349 bool oneshot; 350 int num_slots; 351 int cur_slot; 352 int next_slot; 353 }; 354 355 /** 356 * struct cxl_security_state - Device security state 357 * 358 * @state: state of last security operation 359 * @enabled_cmds: All security commands enabled in the CEL 360 * @poll_tmo_secs: polling timeout 361 * @sanitize_active: sanitize completion pending 362 * @poll_dwork: polling work item 363 * @sanitize_node: sanitation sysfs file to notify 364 */ 365 struct cxl_security_state { 366 unsigned long state; 367 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX); 368 int poll_tmo_secs; 369 bool sanitize_active; 370 struct delayed_work poll_dwork; 371 struct kernfs_node *sanitize_node; 372 }; 373 374 static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds) 375 { 376 /* 377 * Static PMEM may be at partition index 0 when there is no static RAM 378 * capacity. 379 */ 380 for (int i = 0; i < cxlds->nr_partitions; i++) 381 if (cxlds->part[i].mode == CXL_PARTMODE_PMEM) 382 return resource_size(&cxlds->part[i].res); 383 return 0; 384 } 385 386 static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox) 387 { 388 return dev_get_drvdata(cxl_mbox->host); 389 } 390 391 /** 392 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data 393 * 394 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines 395 * common memory device functionality like the presence of a mailbox and 396 * the functionality related to that like Identify Memory Device and Get 397 * Partition Info 398 * @cxlds: Core driver state common across Type-2 and Type-3 devices 399 * @lsa_size: Size of Label Storage Area 400 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 401 * @firmware_version: Firmware version for the memory device. 402 * @total_bytes: sum of all possible capacities 403 * @volatile_only_bytes: hard volatile capacity 404 * @persistent_only_bytes: hard persistent capacity 405 * @partition_align_bytes: alignment size for partition-able capacity 406 * @active_volatile_bytes: sum of hard + soft volatile 407 * @active_persistent_bytes: sum of hard + soft persistent 408 * @event: event log driver state 409 * @poison: poison driver state info 410 * @security: security driver state info 411 * @fw: firmware upload / activation state 412 * @mce_notifier: MCE notifier 413 * 414 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for 415 * details on capacity parameters. 416 */ 417 struct cxl_memdev_state { 418 struct cxl_dev_state cxlds; 419 size_t lsa_size; 420 char firmware_version[0x10]; 421 u64 total_bytes; 422 u64 volatile_only_bytes; 423 u64 persistent_only_bytes; 424 u64 partition_align_bytes; 425 u64 active_volatile_bytes; 426 u64 active_persistent_bytes; 427 428 struct cxl_event_state event; 429 struct cxl_poison_state poison; 430 struct cxl_security_state security; 431 struct cxl_fw_state fw; 432 struct notifier_block mce_notifier; 433 }; 434 435 static inline struct cxl_memdev_state * 436 to_cxl_memdev_state(struct cxl_dev_state *cxlds) 437 { 438 if (cxlds->type != CXL_DEVTYPE_CLASSMEM) 439 return NULL; 440 return container_of(cxlds, struct cxl_memdev_state, cxlds); 441 } 442 443 enum cxl_opcode { 444 CXL_MBOX_OP_INVALID = 0x0000, 445 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 446 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 447 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 448 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 449 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 450 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 451 CXL_MBOX_OP_TRANSFER_FW = 0x0201, 452 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 453 CXL_MBOX_OP_GET_TIMESTAMP = 0x0300, 454 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 455 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 456 CXL_MBOX_OP_GET_LOG = 0x0401, 457 CXL_MBOX_OP_GET_LOG_CAPS = 0x0402, 458 CXL_MBOX_OP_CLEAR_LOG = 0x0403, 459 CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405, 460 CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, 461 CXL_MBOX_OP_GET_FEATURE = 0x0501, 462 CXL_MBOX_OP_SET_FEATURE = 0x0502, 463 CXL_MBOX_OP_DO_MAINTENANCE = 0x0600, 464 CXL_MBOX_OP_IDENTIFY = 0x4000, 465 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 466 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 467 CXL_MBOX_OP_GET_LSA = 0x4102, 468 CXL_MBOX_OP_SET_LSA = 0x4103, 469 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 470 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 471 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 472 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 473 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 474 CXL_MBOX_OP_GET_POISON = 0x4300, 475 CXL_MBOX_OP_INJECT_POISON = 0x4301, 476 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 477 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 478 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 479 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 480 CXL_MBOX_OP_SANITIZE = 0x4400, 481 CXL_MBOX_OP_SECURE_ERASE = 0x4401, 482 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 483 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 484 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 485 CXL_MBOX_OP_UNLOCK = 0x4503, 486 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 487 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 488 CXL_MBOX_OP_MAX = 0x10000 489 }; 490 491 #define DEFINE_CXL_CEL_UUID \ 492 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 493 0x3b, 0x3f, 0x17) 494 495 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 496 UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 497 0x40, 0x3d, 0x86) 498 499 struct cxl_mbox_get_supported_logs { 500 __le16 entries; 501 u8 rsvd[6]; 502 struct cxl_gsl_entry { 503 uuid_t uuid; 504 __le32 size; 505 } __packed entry[]; 506 } __packed; 507 508 struct cxl_cel_entry { 509 __le16 opcode; 510 __le16 effect; 511 } __packed; 512 513 struct cxl_mbox_get_log { 514 uuid_t uuid; 515 __le32 offset; 516 __le32 length; 517 } __packed; 518 519 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 520 struct cxl_mbox_identify { 521 char fw_revision[0x10]; 522 __le64 total_capacity; 523 __le64 volatile_capacity; 524 __le64 persistent_capacity; 525 __le64 partition_align; 526 __le16 info_event_log_size; 527 __le16 warning_event_log_size; 528 __le16 failure_event_log_size; 529 __le16 fatal_event_log_size; 530 __le32 lsa_size; 531 u8 poison_list_max_mer[3]; 532 __le16 inject_poison_limit; 533 u8 poison_caps; 534 u8 qos_telemetry_caps; 535 } __packed; 536 537 /* 538 * General Media Event Record UUID 539 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 540 */ 541 #define CXL_EVENT_GEN_MEDIA_UUID \ 542 UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \ 543 0x21, 0xeb, 0xa6) 544 545 /* 546 * DRAM Event Record UUID 547 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 548 */ 549 #define CXL_EVENT_DRAM_UUID \ 550 UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \ 551 0x5c, 0x96, 0x24) 552 553 /* 554 * Memory Module Event Record UUID 555 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 556 */ 557 #define CXL_EVENT_MEM_MODULE_UUID \ 558 UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \ 559 0x13, 0xb7, 0x74) 560 561 /* 562 * Memory Sparing Event Record UUID 563 * CXL rev 3.2 section 8.2.10.2.1.4: Table 8-60 564 */ 565 #define CXL_EVENT_MEM_SPARING_UUID \ 566 UUID_INIT(0xe71f3a40, 0x2d29, 0x4092, 0x8a, 0x39, 0x4d, 0x1c, 0x96, \ 567 0x6c, 0x7c, 0x65) 568 569 /* 570 * Get Event Records output payload 571 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 572 */ 573 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 574 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 575 struct cxl_get_event_payload { 576 u8 flags; 577 u8 reserved1; 578 __le16 overflow_err_count; 579 __le64 first_overflow_timestamp; 580 __le64 last_overflow_timestamp; 581 __le16 record_count; 582 u8 reserved2[10]; 583 struct cxl_event_record_raw records[]; 584 } __packed; 585 586 /* 587 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 588 */ 589 enum cxl_event_log_type { 590 CXL_EVENT_TYPE_INFO = 0x00, 591 CXL_EVENT_TYPE_WARN, 592 CXL_EVENT_TYPE_FAIL, 593 CXL_EVENT_TYPE_FATAL, 594 CXL_EVENT_TYPE_MAX 595 }; 596 597 /* 598 * Clear Event Records input payload 599 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 600 */ 601 struct cxl_mbox_clear_event_payload { 602 u8 event_log; /* enum cxl_event_log_type */ 603 u8 clear_flags; 604 u8 nr_recs; 605 u8 reserved[3]; 606 __le16 handles[]; 607 } __packed; 608 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 609 610 struct cxl_mbox_get_partition_info { 611 __le64 active_volatile_cap; 612 __le64 active_persistent_cap; 613 __le64 next_volatile_cap; 614 __le64 next_persistent_cap; 615 } __packed; 616 617 struct cxl_mbox_get_lsa { 618 __le32 offset; 619 __le32 length; 620 } __packed; 621 622 struct cxl_mbox_set_lsa { 623 __le32 offset; 624 __le32 reserved; 625 u8 data[]; 626 } __packed; 627 628 struct cxl_mbox_set_partition_info { 629 __le64 volatile_capacity; 630 u8 flags; 631 } __packed; 632 633 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 634 635 /* Get Health Info Output Payload CXL 3.2 Spec 8.2.10.9.3.1 Table 8-148 */ 636 struct cxl_mbox_get_health_info_out { 637 u8 health_status; 638 u8 media_status; 639 u8 additional_status; 640 u8 life_used; 641 __le16 device_temperature; 642 __le32 dirty_shutdown_cnt; 643 __le32 corrected_volatile_error_cnt; 644 __le32 corrected_persistent_error_cnt; 645 } __packed; 646 647 /* Set Shutdown State Input Payload CXL 3.2 Spec 8.2.10.9.3.5 Table 8-152 */ 648 struct cxl_mbox_set_shutdown_state_in { 649 u8 state; 650 } __packed; 651 652 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 653 struct cxl_mbox_set_timestamp_in { 654 __le64 timestamp; 655 656 } __packed; 657 658 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 659 struct cxl_mbox_poison_in { 660 __le64 offset; 661 __le64 length; 662 } __packed; 663 664 struct cxl_mbox_poison_out { 665 u8 flags; 666 u8 rsvd1; 667 __le64 overflow_ts; 668 __le16 count; 669 u8 rsvd2[20]; 670 struct cxl_poison_record { 671 __le64 address; 672 __le32 length; 673 __le32 rsvd; 674 } __packed record[]; 675 } __packed; 676 677 /* 678 * Get Poison List address field encodes the starting 679 * address of poison, and the source of the poison. 680 */ 681 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 682 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 683 684 /* Get Poison List record length is in units of 64 bytes */ 685 #define CXL_POISON_LEN_MULT 64 686 687 /* Kernel defined maximum for a list of poison errors */ 688 #define CXL_POISON_LIST_MAX 1024 689 690 /* Get Poison List: Payload out flags */ 691 #define CXL_POISON_FLAG_MORE BIT(0) 692 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 693 #define CXL_POISON_FLAG_SCANNING BIT(2) 694 695 /* Get Poison List: Poison Source */ 696 #define CXL_POISON_SOURCE_UNKNOWN 0 697 #define CXL_POISON_SOURCE_EXTERNAL 1 698 #define CXL_POISON_SOURCE_INTERNAL 2 699 #define CXL_POISON_SOURCE_INJECTED 3 700 #define CXL_POISON_SOURCE_VENDOR 7 701 702 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 703 struct cxl_mbox_inject_poison { 704 __le64 address; 705 }; 706 707 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 708 struct cxl_mbox_clear_poison { 709 __le64 address; 710 u8 write_data[CXL_POISON_LEN_MULT]; 711 } __packed; 712 713 /** 714 * struct cxl_mem_command - Driver representation of a memory device command 715 * @info: Command information as it exists for the UAPI 716 * @opcode: The actual bits used for the mailbox protocol 717 * @flags: Set of flags effecting driver behavior. 718 * 719 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 720 * will be enabled by the driver regardless of what hardware may have 721 * advertised. 722 * 723 * The cxl_mem_command is the driver's internal representation of commands that 724 * are supported by the driver. Some of these commands may not be supported by 725 * the hardware. The driver will use @info to validate the fields passed in by 726 * the user then submit the @opcode to the hardware. 727 * 728 * See struct cxl_command_info. 729 */ 730 struct cxl_mem_command { 731 struct cxl_command_info info; 732 enum cxl_opcode opcode; 733 u32 flags; 734 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 735 }; 736 737 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 738 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 739 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 740 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 741 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 742 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 743 744 /* set passphrase input payload */ 745 struct cxl_set_pass { 746 u8 type; 747 u8 reserved[31]; 748 /* CXL field using NVDIMM define, same length */ 749 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 750 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 751 } __packed; 752 753 /* disable passphrase input payload */ 754 struct cxl_disable_pass { 755 u8 type; 756 u8 reserved[31]; 757 u8 pass[NVDIMM_PASSPHRASE_LEN]; 758 } __packed; 759 760 /* passphrase secure erase payload */ 761 struct cxl_pass_erase { 762 u8 type; 763 u8 reserved[31]; 764 u8 pass[NVDIMM_PASSPHRASE_LEN]; 765 } __packed; 766 767 enum { 768 CXL_PMEM_SEC_PASS_MASTER = 0, 769 CXL_PMEM_SEC_PASS_USER, 770 }; 771 772 int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, 773 struct cxl_mbox_cmd *cmd); 774 int cxl_dev_state_identify(struct cxl_memdev_state *mds); 775 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 776 int cxl_enumerate_cmds(struct cxl_memdev_state *mds); 777 int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info); 778 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial, 779 u16 dvsec); 780 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 781 unsigned long *cmds); 782 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 783 unsigned long *cmds); 784 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status); 785 void cxl_event_trace_record(struct cxl_memdev *cxlmd, 786 enum cxl_event_log_type type, 787 enum cxl_event_type event_type, 788 const uuid_t *uuid, union cxl_event *evt); 789 int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count); 790 int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds); 791 int cxl_set_timestamp(struct cxl_memdev_state *mds); 792 int cxl_poison_state_init(struct cxl_memdev_state *mds); 793 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 794 struct cxl_region *cxlr); 795 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 796 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 797 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 798 int cxl_inject_poison_locked(struct cxl_memdev *cxlmd, u64 dpa); 799 int cxl_clear_poison_locked(struct cxl_memdev *cxlmd, u64 dpa); 800 801 #ifdef CONFIG_CXL_EDAC_MEM_FEATURES 802 int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd); 803 int devm_cxl_region_edac_register(struct cxl_region *cxlr); 804 int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, union cxl_event *evt); 805 int cxl_store_rec_dram(struct cxl_memdev *cxlmd, union cxl_event *evt); 806 #else 807 static inline int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd) 808 { return 0; } 809 static inline int devm_cxl_region_edac_register(struct cxl_region *cxlr) 810 { return 0; } 811 static inline int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, 812 union cxl_event *evt) 813 { return 0; } 814 static inline int cxl_store_rec_dram(struct cxl_memdev *cxlmd, 815 union cxl_event *evt) 816 { return 0; } 817 #endif 818 819 #ifdef CONFIG_CXL_SUSPEND 820 void cxl_mem_active_inc(void); 821 void cxl_mem_active_dec(void); 822 #else 823 static inline void cxl_mem_active_inc(void) 824 { 825 } 826 static inline void cxl_mem_active_dec(void) 827 { 828 } 829 #endif 830 831 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd); 832 833 /** 834 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities 835 * @regs: mapped registers, see devm_cxl_setup_hdm() 836 * @decoder_count: number of decoders for this port 837 * @target_count: for switch decoders, max downstream port targets 838 * @interleave_mask: interleave granularity capability, see check_interleave_cap() 839 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap() 840 * @port: mapped cxl_port, see devm_cxl_setup_hdm() 841 */ 842 struct cxl_hdm { 843 struct cxl_component_regs regs; 844 int decoder_count; 845 unsigned int target_count; 846 unsigned int interleave_mask; 847 unsigned long iw_cap_mask; 848 struct cxl_port *port; 849 }; 850 851 struct seq_file; 852 struct dentry *cxl_debugfs_create_dir(const char *dir); 853 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 854 #endif /* __CXL_MEM_H__ */ 855