15161a55cSBen Widawsky /* SPDX-License-Identifier: GPL-2.0-only */ 25161a55cSBen Widawsky /* Copyright(c) 2020-2021 Intel Corporation. */ 35161a55cSBen Widawsky #ifndef __CXL_MEM_H__ 45161a55cSBen Widawsky #define __CXL_MEM_H__ 54faf31b4SDan Williams #include <uapi/linux/cxl_mem.h> 65161a55cSBen Widawsky #include <linux/cdev.h> 75161a55cSBen Widawsky #include "cxl.h" 85161a55cSBen Widawsky 95161a55cSBen Widawsky /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 105161a55cSBen Widawsky #define CXLMDEV_STATUS_OFFSET 0x0 115161a55cSBen Widawsky #define CXLMDEV_DEV_FATAL BIT(0) 125161a55cSBen Widawsky #define CXLMDEV_FW_HALT BIT(1) 135161a55cSBen Widawsky #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 145161a55cSBen Widawsky #define CXLMDEV_MS_NOT_READY 0 155161a55cSBen Widawsky #define CXLMDEV_MS_READY 1 165161a55cSBen Widawsky #define CXLMDEV_MS_ERROR 2 175161a55cSBen Widawsky #define CXLMDEV_MS_DISABLED 3 185161a55cSBen Widawsky #define CXLMDEV_READY(status) \ 195161a55cSBen Widawsky (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 205161a55cSBen Widawsky CXLMDEV_MS_READY) 215161a55cSBen Widawsky #define CXLMDEV_MBOX_IF_READY BIT(4) 225161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 235161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_NOT 0 245161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_COLD 1 255161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_WARM 2 265161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_HOT 3 275161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_CXL 4 285161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED(status) \ 295161a55cSBen Widawsky (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 305161a55cSBen Widawsky CXLMDEV_RESET_NEEDED_NOT) 315161a55cSBen Widawsky 325161a55cSBen Widawsky /** 335161a55cSBen Widawsky * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 345161a55cSBen Widawsky * @dev: driver core device object 355161a55cSBen Widawsky * @cdev: char dev core object for ioctl operations 365161a55cSBen Widawsky * @cxlm: pointer to the parent device driver data 375161a55cSBen Widawsky * @id: id number of this memdev instance. 385161a55cSBen Widawsky */ 395161a55cSBen Widawsky struct cxl_memdev { 405161a55cSBen Widawsky struct device dev; 415161a55cSBen Widawsky struct cdev cdev; 425161a55cSBen Widawsky struct cxl_mem *cxlm; 435161a55cSBen Widawsky int id; 445161a55cSBen Widawsky }; 455161a55cSBen Widawsky 463d135db5SBen Widawsky static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 473d135db5SBen Widawsky { 483d135db5SBen Widawsky return container_of(dev, struct cxl_memdev, dev); 493d135db5SBen Widawsky } 503d135db5SBen Widawsky 514faf31b4SDan Williams struct cxl_memdev *devm_cxl_add_memdev(struct cxl_mem *cxlm); 523d135db5SBen Widawsky 535161a55cSBen Widawsky /** 54b64955a9SDan Williams * struct cxl_mbox_cmd - A command to be submitted to hardware. 55b64955a9SDan Williams * @opcode: (input) The command set and command submitted to hardware. 56b64955a9SDan Williams * @payload_in: (input) Pointer to the input payload. 57b64955a9SDan Williams * @payload_out: (output) Pointer to the output payload. Must be allocated by 58b64955a9SDan Williams * the caller. 59b64955a9SDan Williams * @size_in: (input) Number of bytes to load from @payload_in. 60b64955a9SDan Williams * @size_out: (input) Max number of bytes loaded into @payload_out. 61b64955a9SDan Williams * (output) Number of bytes generated by the device. For fixed size 62b64955a9SDan Williams * outputs commands this is always expected to be deterministic. For 63b64955a9SDan Williams * variable sized output commands, it tells the exact number of bytes 64b64955a9SDan Williams * written. 65b64955a9SDan Williams * @return_code: (output) Error code returned from hardware. 66b64955a9SDan Williams * 67b64955a9SDan Williams * This is the primary mechanism used to send commands to the hardware. 68b64955a9SDan Williams * All the fields except @payload_* correspond exactly to the fields described in 69b64955a9SDan Williams * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 70b64955a9SDan Williams * @payload_out are written to, and read from the Command Payload Registers 71b64955a9SDan Williams * defined in CXL 2.0 8.2.8.4.8. 72b64955a9SDan Williams */ 73b64955a9SDan Williams struct cxl_mbox_cmd { 74b64955a9SDan Williams u16 opcode; 75b64955a9SDan Williams void *payload_in; 76b64955a9SDan Williams void *payload_out; 77b64955a9SDan Williams size_t size_in; 78b64955a9SDan Williams size_t size_out; 79b64955a9SDan Williams u16 return_code; 80b64955a9SDan Williams #define CXL_MBOX_SUCCESS 0 81b64955a9SDan Williams }; 82b64955a9SDan Williams 83b64955a9SDan Williams /* 84b64955a9SDan Williams * CXL 2.0 - Memory capacity multiplier 85b64955a9SDan Williams * See Section 8.2.9.5 86b64955a9SDan Williams * 87b64955a9SDan Williams * Volatile, Persistent, and Partition capacities are specified to be in 88b64955a9SDan Williams * multiples of 256MB - define a multiplier to convert to/from bytes. 89b64955a9SDan Williams */ 90b64955a9SDan Williams #define CXL_CAPACITY_MULTIPLIER SZ_256M 91b64955a9SDan Williams 92b64955a9SDan Williams /** 935161a55cSBen Widawsky * struct cxl_mem - A CXL memory device 9499e222a5SDan Williams * @dev: The device associated with this CXL device. 955161a55cSBen Widawsky * @cxlmd: Logical memory device chardev / interface 965161a55cSBen Widawsky * @regs: Parsed register blocks 975161a55cSBen Widawsky * @payload_size: Size of space for payload 985161a55cSBen Widawsky * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 995161a55cSBen Widawsky * @lsa_size: Size of Label Storage Area 1005161a55cSBen Widawsky * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 1015161a55cSBen Widawsky * @mbox_mutex: Mutex to synchronize mailbox access. 1025161a55cSBen Widawsky * @firmware_version: Firmware version for the memory device. 1035161a55cSBen Widawsky * @enabled_cmds: Hardware commands found enabled in CEL. 10413e7749dSDan Williams * @pmem_range: Active Persistent memory capacity configuration 10513e7749dSDan Williams * @ram_range: Active Volatile memory capacity configuration 10613e7749dSDan Williams * @total_bytes: sum of all possible capacities 10713e7749dSDan Williams * @volatile_only_bytes: hard volatile capacity 10813e7749dSDan Williams * @persistent_only_bytes: hard persistent capacity 10913e7749dSDan Williams * @partition_align_bytes: alignment size for partition-able capacity 11013e7749dSDan Williams * @active_volatile_bytes: sum of hard + soft volatile 11113e7749dSDan Williams * @active_persistent_bytes: sum of hard + soft persistent 11213e7749dSDan Williams * @next_volatile_bytes: volatile capacity change pending device reset 11313e7749dSDan Williams * @next_persistent_bytes: persistent capacity change pending device reset 114b64955a9SDan Williams * @mbox_send: @dev specific transport for transmitting mailbox commands 11513e7749dSDan Williams * 11613e7749dSDan Williams * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 11713e7749dSDan Williams * details on capacity parameters. 1185161a55cSBen Widawsky */ 1195161a55cSBen Widawsky struct cxl_mem { 12099e222a5SDan Williams struct device *dev; 1215161a55cSBen Widawsky struct cxl_memdev *cxlmd; 1225161a55cSBen Widawsky 1235161a55cSBen Widawsky struct cxl_regs regs; 1245161a55cSBen Widawsky 1255161a55cSBen Widawsky size_t payload_size; 1265161a55cSBen Widawsky size_t lsa_size; 1275161a55cSBen Widawsky struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 1285161a55cSBen Widawsky char firmware_version[0x10]; 129*ff56ab9eSDan Williams DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 1305161a55cSBen Widawsky 1315161a55cSBen Widawsky struct range pmem_range; 1325161a55cSBen Widawsky struct range ram_range; 1330b9159d0SIra Weiny u64 total_bytes; 1340b9159d0SIra Weiny u64 volatile_only_bytes; 1350b9159d0SIra Weiny u64 persistent_only_bytes; 1360b9159d0SIra Weiny u64 partition_align_bytes; 137f847502aSIra Weiny 138f847502aSIra Weiny u64 active_volatile_bytes; 139f847502aSIra Weiny u64 active_persistent_bytes; 140f847502aSIra Weiny u64 next_volatile_bytes; 141f847502aSIra Weiny u64 next_persistent_bytes; 142b64955a9SDan Williams 143b64955a9SDan Williams int (*mbox_send)(struct cxl_mem *cxlm, struct cxl_mbox_cmd *cmd); 1445161a55cSBen Widawsky }; 1454faf31b4SDan Williams 1464faf31b4SDan Williams enum cxl_opcode { 1474faf31b4SDan Williams CXL_MBOX_OP_INVALID = 0x0000, 1484faf31b4SDan Williams CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 1494faf31b4SDan Williams CXL_MBOX_OP_GET_FW_INFO = 0x0200, 1504faf31b4SDan Williams CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 1514faf31b4SDan Williams CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 1524faf31b4SDan Williams CXL_MBOX_OP_GET_LOG = 0x0401, 1534faf31b4SDan Williams CXL_MBOX_OP_IDENTIFY = 0x4000, 1544faf31b4SDan Williams CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 1554faf31b4SDan Williams CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 1564faf31b4SDan Williams CXL_MBOX_OP_GET_LSA = 0x4102, 1574faf31b4SDan Williams CXL_MBOX_OP_SET_LSA = 0x4103, 1584faf31b4SDan Williams CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 1594faf31b4SDan Williams CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 1604faf31b4SDan Williams CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 1614faf31b4SDan Williams CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 1624faf31b4SDan Williams CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 1634faf31b4SDan Williams CXL_MBOX_OP_GET_POISON = 0x4300, 1644faf31b4SDan Williams CXL_MBOX_OP_INJECT_POISON = 0x4301, 1654faf31b4SDan Williams CXL_MBOX_OP_CLEAR_POISON = 0x4302, 1664faf31b4SDan Williams CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 1674faf31b4SDan Williams CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 1684faf31b4SDan Williams CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 1694faf31b4SDan Williams CXL_MBOX_OP_MAX = 0x10000 1704faf31b4SDan Williams }; 1714faf31b4SDan Williams 1724faf31b4SDan Williams /** 1734faf31b4SDan Williams * struct cxl_mem_command - Driver representation of a memory device command 1744faf31b4SDan Williams * @info: Command information as it exists for the UAPI 1754faf31b4SDan Williams * @opcode: The actual bits used for the mailbox protocol 1764faf31b4SDan Williams * @flags: Set of flags effecting driver behavior. 1774faf31b4SDan Williams * 1784faf31b4SDan Williams * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 1794faf31b4SDan Williams * will be enabled by the driver regardless of what hardware may have 1804faf31b4SDan Williams * advertised. 1814faf31b4SDan Williams * 1824faf31b4SDan Williams * The cxl_mem_command is the driver's internal representation of commands that 1834faf31b4SDan Williams * are supported by the driver. Some of these commands may not be supported by 1844faf31b4SDan Williams * the hardware. The driver will use @info to validate the fields passed in by 1854faf31b4SDan Williams * the user then submit the @opcode to the hardware. 1864faf31b4SDan Williams * 1874faf31b4SDan Williams * See struct cxl_command_info. 1884faf31b4SDan Williams */ 1894faf31b4SDan Williams struct cxl_mem_command { 1904faf31b4SDan Williams struct cxl_command_info info; 1914faf31b4SDan Williams enum cxl_opcode opcode; 1924faf31b4SDan Williams u32 flags; 1934faf31b4SDan Williams #define CXL_CMD_FLAG_NONE 0 1944faf31b4SDan Williams #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 1954faf31b4SDan Williams }; 1964faf31b4SDan Williams 1974faf31b4SDan Williams int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, void *in, 1984faf31b4SDan Williams size_t in_size, void *out, size_t out_size); 1994faf31b4SDan Williams int cxl_mem_identify(struct cxl_mem *cxlm); 2004faf31b4SDan Williams int cxl_mem_enumerate_cmds(struct cxl_mem *cxlm); 2014faf31b4SDan Williams int cxl_mem_create_range_info(struct cxl_mem *cxlm); 2024faf31b4SDan Williams struct cxl_mem *cxl_mem_create(struct device *dev); 2035161a55cSBen Widawsky #endif /* __CXL_MEM_H__ */ 204